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cleanup: rename armv4_5 to arm for readability
[openocd.git] / src / target / armv4_5.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "arm.h"
31 #include "armv4_5.h"
32 #include "arm_jtag.h"
33 #include "breakpoints.h"
34 #include "arm_disassembler.h"
35 #include <helper/binarybuffer.h>
36 #include "algorithm.h"
37 #include "register.h"
38
39
40 /* offsets into armv4_5 core register cache */
41 enum {
42 // ARMV4_5_CPSR = 31,
43 ARMV4_5_SPSR_FIQ = 32,
44 ARMV4_5_SPSR_IRQ = 33,
45 ARMV4_5_SPSR_SVC = 34,
46 ARMV4_5_SPSR_ABT = 35,
47 ARMV4_5_SPSR_UND = 36,
48 ARM_SPSR_MON = 39,
49 };
50
51 static const uint8_t arm_usr_indices[17] = {
52 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
53 };
54
55 static const uint8_t arm_fiq_indices[8] = {
56 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
57 };
58
59 static const uint8_t arm_irq_indices[3] = {
60 23, 24, ARMV4_5_SPSR_IRQ,
61 };
62
63 static const uint8_t arm_svc_indices[3] = {
64 25, 26, ARMV4_5_SPSR_SVC,
65 };
66
67 static const uint8_t arm_abt_indices[3] = {
68 27, 28, ARMV4_5_SPSR_ABT,
69 };
70
71 static const uint8_t arm_und_indices[3] = {
72 29, 30, ARMV4_5_SPSR_UND,
73 };
74
75 static const uint8_t arm_mon_indices[3] = {
76 37, 38, ARM_SPSR_MON,
77 };
78
79 static const struct {
80 const char *name;
81 unsigned short psr;
82 /* For user and system modes, these list indices for all registers.
83 * otherwise they're just indices for the shadow registers and SPSR.
84 */
85 unsigned short n_indices;
86 const uint8_t *indices;
87 } arm_mode_data[] = {
88 /* Seven modes are standard from ARM7 on. "System" and "User" share
89 * the same registers; other modes shadow from 3 to 8 registers.
90 */
91 {
92 .name = "User",
93 .psr = ARM_MODE_USR,
94 .n_indices = ARRAY_SIZE(arm_usr_indices),
95 .indices = arm_usr_indices,
96 },
97 {
98 .name = "FIQ",
99 .psr = ARM_MODE_FIQ,
100 .n_indices = ARRAY_SIZE(arm_fiq_indices),
101 .indices = arm_fiq_indices,
102 },
103 {
104 .name = "Supervisor",
105 .psr = ARM_MODE_SVC,
106 .n_indices = ARRAY_SIZE(arm_svc_indices),
107 .indices = arm_svc_indices,
108 },
109 {
110 .name = "Abort",
111 .psr = ARM_MODE_ABT,
112 .n_indices = ARRAY_SIZE(arm_abt_indices),
113 .indices = arm_abt_indices,
114 },
115 {
116 .name = "IRQ",
117 .psr = ARM_MODE_IRQ,
118 .n_indices = ARRAY_SIZE(arm_irq_indices),
119 .indices = arm_irq_indices,
120 },
121 {
122 .name = "Undefined instruction",
123 .psr = ARM_MODE_UND,
124 .n_indices = ARRAY_SIZE(arm_und_indices),
125 .indices = arm_und_indices,
126 },
127 {
128 .name = "System",
129 .psr = ARM_MODE_SYS,
130 .n_indices = ARRAY_SIZE(arm_usr_indices),
131 .indices = arm_usr_indices,
132 },
133 /* TrustZone "Security Extensions" add a secure monitor mode.
134 * This is distinct from a "debug monitor" which can support
135 * non-halting debug, in conjunction with some debuggers.
136 */
137 {
138 .name = "Secure Monitor",
139 .psr = ARM_MODE_MON,
140 .n_indices = ARRAY_SIZE(arm_mon_indices),
141 .indices = arm_mon_indices,
142 },
143 };
144
145 /** Map PSR mode bits to the name of an ARM processor operating mode. */
146 const char *arm_mode_name(unsigned psr_mode)
147 {
148 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
149 if (arm_mode_data[i].psr == psr_mode)
150 return arm_mode_data[i].name;
151 }
152 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
153 return "UNRECOGNIZED";
154 }
155
156 /** Return true iff the parameter denotes a valid ARM processor mode. */
157 bool is_arm_mode(unsigned psr_mode)
158 {
159 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
160 if (arm_mode_data[i].psr == psr_mode)
161 return true;
162 }
163 return false;
164 }
165
166 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
167 int arm_mode_to_number(enum arm_mode mode)
168 {
169 switch (mode) {
170 case ARM_MODE_ANY:
171 /* map MODE_ANY to user mode */
172 case ARM_MODE_USR:
173 return 0;
174 case ARM_MODE_FIQ:
175 return 1;
176 case ARM_MODE_IRQ:
177 return 2;
178 case ARM_MODE_SVC:
179 return 3;
180 case ARM_MODE_ABT:
181 return 4;
182 case ARM_MODE_UND:
183 return 5;
184 case ARM_MODE_SYS:
185 return 6;
186 case ARM_MODE_MON:
187 return 7;
188 default:
189 LOG_ERROR("invalid mode value encountered %d", mode);
190 return -1;
191 }
192 }
193
194 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
195 enum arm_mode armv4_5_number_to_mode(int number)
196 {
197 switch (number) {
198 case 0:
199 return ARM_MODE_USR;
200 case 1:
201 return ARM_MODE_FIQ;
202 case 2:
203 return ARM_MODE_IRQ;
204 case 3:
205 return ARM_MODE_SVC;
206 case 4:
207 return ARM_MODE_ABT;
208 case 5:
209 return ARM_MODE_UND;
210 case 6:
211 return ARM_MODE_SYS;
212 case 7:
213 return ARM_MODE_MON;
214 default:
215 LOG_ERROR("mode index out of bounds %d", number);
216 return ARM_MODE_ANY;
217 }
218 }
219
220 static const char *arm_state_strings[] =
221 {
222 "ARM", "Thumb", "Jazelle", "ThumbEE",
223 };
224
225 /* Templates for ARM core registers.
226 *
227 * NOTE: offsets in this table are coupled to the arm_mode_data
228 * table above, the armv4_5_core_reg_map array below, and also to
229 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
230 */
231 static const struct {
232 /* The name is used for e.g. the "regs" command. */
233 const char *name;
234
235 /* The {cookie, mode} tuple uniquely identifies one register.
236 * In a given mode, cookies 0..15 map to registers R0..R15,
237 * with R13..R15 usually called SP, LR, PC.
238 *
239 * MODE_ANY is used as *input* to the mapping, and indicates
240 * various special cases (sigh) and errors.
241 *
242 * Cookie 16 is (currently) confusing, since it indicates
243 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
244 * (Exception modes have both CPSR and SPSR registers ...)
245 */
246 unsigned cookie;
247 enum arm_mode mode;
248 } arm_core_regs[] = {
249 /* IMPORTANT: we guarantee that the first eight cached registers
250 * correspond to r0..r7, and the fifteenth to PC, so that callers
251 * don't need to map them.
252 */
253 { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, },
254 { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, },
255 { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, },
256 { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, },
257 { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, },
258 { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, },
259 { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, },
260 { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, },
261
262 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
263 * them as MODE_ANY creates special cases. (ANY means
264 * "not mapped" elsewhere; here it's "everything but FIQ".)
265 */
266 { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, },
267 { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, },
268 { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, },
269 { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, },
270 { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, },
271
272 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
273 { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, },
274 { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, },
275
276 /* guaranteed to be at index 15 */
277 { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, },
278
279 { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, },
280 { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, },
281 { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, },
282 { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, },
283 { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, },
284
285 { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, },
286 { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, },
287
288 { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, },
289 { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, },
290
291 { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, },
292 { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, },
293
294 { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, },
295 { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, },
296
297 { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, },
298 { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, },
299
300 { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, },
301 { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, },
302 { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, },
303 { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, },
304 { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, },
305 { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, },
306
307 { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, },
308 { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, },
309 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
310 };
311
312 /* map core mode (USR, FIQ, ...) and register number to
313 * indices into the register cache
314 */
315 const int armv4_5_core_reg_map[8][17] =
316 {
317 { /* USR */
318 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
319 },
320 { /* FIQ (8 shadows of USR, vs normal 3) */
321 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
322 },
323 { /* IRQ */
324 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
325 },
326 { /* SVC */
327 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
328 },
329 { /* ABT */
330 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
331 },
332 { /* UND */
333 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
334 },
335 { /* SYS (same registers as USR) */
336 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
337 },
338 { /* MON */
339 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
340 }
341 };
342
343 /**
344 * Configures host-side ARM records to reflect the specified CPSR.
345 * Later, code can use arm_reg_current() to map register numbers
346 * according to how they are exposed by this mode.
347 */
348 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
349 {
350 enum arm_mode mode = cpsr & 0x1f;
351 int num;
352
353 /* NOTE: this may be called very early, before the register
354 * cache is set up. We can't defend against many errors, in
355 * particular against CPSRs that aren't valid *here* ...
356 */
357 if (arm->cpsr) {
358 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
359 arm->cpsr->valid = 1;
360 arm->cpsr->dirty = 0;
361 }
362
363 arm->core_mode = mode;
364
365 /* mode_to_number() warned; set up a somewhat-sane mapping */
366 num = arm_mode_to_number(mode);
367 if (num < 0) {
368 mode = ARM_MODE_USR;
369 num = 0;
370 }
371
372 arm->map = &armv4_5_core_reg_map[num][0];
373 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
374 ? NULL
375 : arm->core_cache->reg_list + arm->map[16];
376
377 /* Older ARMs won't have the J bit */
378 enum arm_state state;
379
380 if (cpsr & (1 << 5)) { /* T */
381 if (cpsr & (1 << 24)) { /* J */
382 LOG_WARNING("ThumbEE -- incomplete support");
383 state = ARM_STATE_THUMB_EE;
384 } else
385 state = ARM_STATE_THUMB;
386 } else {
387 if (cpsr & (1 << 24)) { /* J */
388 LOG_ERROR("Jazelle state handling is BROKEN!");
389 state = ARM_STATE_JAZELLE;
390 } else
391 state = ARM_STATE_ARM;
392 }
393 arm->core_state = state;
394
395 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
396 arm_mode_name(mode),
397 arm_state_strings[arm->core_state]);
398 }
399
400 /**
401 * Returns handle to the register currently mapped to a given number.
402 * Someone must have called arm_set_cpsr() before.
403 *
404 * \param arm This core's state and registers are used.
405 * \param regnum From 0..15 corresponding to R0..R14 and PC.
406 * Note that R0..R7 don't require mapping; you may access those
407 * as the first eight entries in the register cache. Likewise
408 * R15 (PC) doesn't need mapping; you may also access it directly.
409 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
410 * CPSR (arm->cpsr) is also not mapped.
411 */
412 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
413 {
414 struct reg *r;
415
416 if (regnum > 16)
417 return NULL;
418
419 r = arm->core_cache->reg_list + arm->map[regnum];
420
421 /* e.g. invalid CPSR said "secure monitor" mode on a core
422 * that doesn't support it...
423 */
424 if (!r) {
425 LOG_ERROR("Invalid CPSR mode");
426 r = arm->core_cache->reg_list + regnum;
427 }
428
429 return r;
430 }
431
432 static const uint8_t arm_gdb_dummy_fp_value[12];
433
434 /**
435 * Dummy FPA registers are required to support GDB on ARM.
436 * Register packets require eight obsolete FPA register values.
437 * Modern ARM cores use Vector Floating Point (VFP), if they
438 * have any floating point support. VFP is not FPA-compatible.
439 */
440 struct reg arm_gdb_dummy_fp_reg =
441 {
442 .name = "GDB dummy FPA register",
443 .value = (uint8_t *) arm_gdb_dummy_fp_value,
444 .valid = 1,
445 .size = 96,
446 };
447
448 static const uint8_t arm_gdb_dummy_fps_value[4];
449
450 /**
451 * Dummy FPA status registers are required to support GDB on ARM.
452 * Register packets require an obsolete FPA status register.
453 */
454 struct reg arm_gdb_dummy_fps_reg =
455 {
456 .name = "GDB dummy FPA status register",
457 .value = (uint8_t *) arm_gdb_dummy_fps_value,
458 .valid = 1,
459 .size = 32,
460 };
461
462 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
463
464 static void arm_gdb_dummy_init(void)
465 {
466 register_init_dummy(&arm_gdb_dummy_fp_reg);
467 register_init_dummy(&arm_gdb_dummy_fps_reg);
468 }
469
470 static int armv4_5_get_core_reg(struct reg *reg)
471 {
472 int retval;
473 struct arm_reg *reg_arch_info = reg->arch_info;
474 struct target *target = reg_arch_info->target;
475
476 if (target->state != TARGET_HALTED)
477 {
478 LOG_ERROR("Target not halted");
479 return ERROR_TARGET_NOT_HALTED;
480 }
481
482 retval = reg_arch_info->arm->read_core_reg(target, reg,
483 reg_arch_info->num, reg_arch_info->mode);
484 if (retval == ERROR_OK) {
485 reg->valid = 1;
486 reg->dirty = 0;
487 }
488
489 return retval;
490 }
491
492 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
493 {
494 struct arm_reg *reg_arch_info = reg->arch_info;
495 struct target *target = reg_arch_info->target;
496 struct arm *armv4_5_target = target_to_arm(target);
497 uint32_t value = buf_get_u32(buf, 0, 32);
498
499 if (target->state != TARGET_HALTED)
500 {
501 LOG_ERROR("Target not halted");
502 return ERROR_TARGET_NOT_HALTED;
503 }
504
505 /* Except for CPSR, the "reg" command exposes a writeback model
506 * for the register cache.
507 */
508 if (reg == armv4_5_target->cpsr) {
509 arm_set_cpsr(armv4_5_target, value);
510
511 /* Older cores need help to be in ARM mode during halt
512 * mode debug, so we clear the J and T bits if we flush.
513 * For newer cores (v6/v7a/v7r) we don't need that, but
514 * it won't hurt since CPSR is always flushed anyway.
515 */
516 if (armv4_5_target->core_mode !=
517 (enum arm_mode)(value & 0x1f)) {
518 LOG_DEBUG("changing ARM core mode to '%s'",
519 arm_mode_name(value & 0x1f));
520 value &= ~((1 << 24) | (1 << 5));
521 armv4_5_target->write_core_reg(target, reg,
522 16, ARM_MODE_ANY, value);
523 }
524 } else {
525 buf_set_u32(reg->value, 0, 32, value);
526 reg->valid = 1;
527 }
528 reg->dirty = 1;
529
530 return ERROR_OK;
531 }
532
533 static const struct reg_arch_type arm_reg_type = {
534 .get = armv4_5_get_core_reg,
535 .set = armv4_5_set_core_reg,
536 };
537
538 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
539 {
540 int num_regs = ARRAY_SIZE(arm_core_regs);
541 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
542 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
543 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
544 int i;
545
546 if (!cache || !reg_list || !reg_arch_info) {
547 free(cache);
548 free(reg_list);
549 free(reg_arch_info);
550 return NULL;
551 }
552
553 cache->name = "ARM registers";
554 cache->next = NULL;
555 cache->reg_list = reg_list;
556 cache->num_regs = 0;
557
558 for (i = 0; i < num_regs; i++)
559 {
560 /* Skip registers this core doesn't expose */
561 if (arm_core_regs[i].mode == ARM_MODE_MON
562 && arm->core_type != ARM_MODE_MON)
563 continue;
564
565 /* REVISIT handle Cortex-M, which only shadows R13/SP */
566
567 reg_arch_info[i].num = arm_core_regs[i].cookie;
568 reg_arch_info[i].mode = arm_core_regs[i].mode;
569 reg_arch_info[i].target = target;
570 reg_arch_info[i].arm = arm;
571
572 reg_list[i].name = (char *) arm_core_regs[i].name;
573 reg_list[i].size = 32;
574 reg_list[i].value = &reg_arch_info[i].value;
575 reg_list[i].type = &arm_reg_type;
576 reg_list[i].arch_info = &reg_arch_info[i];
577
578 cache->num_regs++;
579 }
580
581 arm->pc = reg_list + 15;
582 arm->cpsr = reg_list + ARMV4_5_CPSR;
583 arm->core_cache = cache;
584 return cache;
585 }
586
587 int arm_arch_state(struct target *target)
588 {
589 struct arm *arm = target_to_arm(target);
590
591 if (arm->common_magic != ARM_COMMON_MAGIC)
592 {
593 LOG_ERROR("BUG: called for a non-ARM target");
594 return ERROR_FAIL;
595 }
596
597 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
598 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
599 arm_state_strings[arm->core_state],
600 debug_reason_name(target),
601 arm_mode_name(arm->core_mode),
602 buf_get_u32(arm->cpsr->value, 0, 32),
603 buf_get_u32(arm->pc->value, 0, 32),
604 arm->is_semihosting ? ", semihosting" : "");
605
606 return ERROR_OK;
607 }
608
609 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
610 cache->reg_list[armv4_5_core_reg_map[mode][num]]
611
612 COMMAND_HANDLER(handle_armv4_5_reg_command)
613 {
614 struct target *target = get_current_target(CMD_CTX);
615 struct arm *arm = target_to_arm(target);
616 struct reg *regs;
617
618 if (!is_arm(arm))
619 {
620 command_print(CMD_CTX, "current target isn't an ARM");
621 return ERROR_FAIL;
622 }
623
624 if (target->state != TARGET_HALTED)
625 {
626 command_print(CMD_CTX, "error: target must be halted for register accesses");
627 return ERROR_FAIL;
628 }
629
630 if (arm->core_type != ARM_MODE_ANY)
631 {
632 command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd");
633 return ERROR_OK;
634 }
635
636 if (!is_arm_mode(arm->core_mode))
637 {
638 LOG_ERROR("not a valid arm core mode - communication failure?");
639 return ERROR_FAIL;
640 }
641
642 if (!arm->full_context) {
643 command_print(CMD_CTX, "error: target doesn't support %s",
644 CMD_NAME);
645 return ERROR_FAIL;
646 }
647
648 regs = arm->core_cache->reg_list;
649
650 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
651 const char *name;
652 char *sep = "\n";
653 char *shadow = "";
654
655 /* label this bank of registers (or shadows) */
656 switch (arm_mode_data[mode].psr) {
657 case ARM_MODE_SYS:
658 continue;
659 case ARM_MODE_USR:
660 name = "System and User";
661 sep = "";
662 break;
663 case ARM_MODE_MON:
664 if (arm->core_type != ARM_MODE_MON)
665 continue;
666 /* FALLTHROUGH */
667 default:
668 name = arm_mode_data[mode].name;
669 shadow = "shadow ";
670 break;
671 }
672 command_print(CMD_CTX, "%s%s mode %sregisters",
673 sep, name, shadow);
674
675 /* display N rows of up to 4 registers each */
676 for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) {
677 char output[80];
678 int output_len = 0;
679
680 for (unsigned j = 0; j < 4; j++, i++) {
681 uint32_t value;
682 struct reg *reg = regs;
683
684 if (i >= arm_mode_data[mode].n_indices)
685 break;
686
687 reg += arm_mode_data[mode].indices[i];
688
689 /* REVISIT be smarter about faults... */
690 if (!reg->valid)
691 arm->full_context(target);
692
693 value = buf_get_u32(reg->value, 0, 32);
694 output_len += snprintf(output + output_len,
695 sizeof(output) - output_len,
696 "%8s: %8.8" PRIx32 " ",
697 reg->name, value);
698 }
699 command_print(CMD_CTX, "%s", output);
700 }
701 }
702
703 return ERROR_OK;
704 }
705
706 COMMAND_HANDLER(handle_armv4_5_core_state_command)
707 {
708 struct target *target = get_current_target(CMD_CTX);
709 struct arm *arm = target_to_arm(target);
710
711 if (!is_arm(arm))
712 {
713 command_print(CMD_CTX, "current target isn't an ARM");
714 return ERROR_FAIL;
715 }
716
717 if (arm->core_type == ARM_MODE_THREAD)
718 {
719 /* armv7m not supported */
720 command_print(CMD_CTX, "Unsupported Command");
721 return ERROR_OK;
722 }
723
724 if (CMD_ARGC > 0)
725 {
726 if (strcmp(CMD_ARGV[0], "arm") == 0)
727 {
728 arm->core_state = ARM_STATE_ARM;
729 }
730 if (strcmp(CMD_ARGV[0], "thumb") == 0)
731 {
732 arm->core_state = ARM_STATE_THUMB;
733 }
734 }
735
736 command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
737
738 return ERROR_OK;
739 }
740
741 COMMAND_HANDLER(handle_arm_disassemble_command)
742 {
743 int retval = ERROR_OK;
744 struct target *target = get_current_target(CMD_CTX);
745
746 if (target == NULL) {
747 LOG_ERROR("No target selected");
748 return ERROR_FAIL;
749 }
750
751 struct arm *arm = target_to_arm(target);
752 uint32_t address;
753 int count = 1;
754 int thumb = 0;
755
756 if (!is_arm(arm)) {
757 command_print(CMD_CTX, "current target isn't an ARM");
758 return ERROR_FAIL;
759 }
760
761 if (arm->core_type == ARM_MODE_THREAD)
762 {
763 /* armv7m is always thumb mode */
764 thumb = 1;
765 }
766
767 switch (CMD_ARGC) {
768 case 3:
769 if (strcmp(CMD_ARGV[2], "thumb") != 0)
770 goto usage;
771 thumb = 1;
772 /* FALL THROUGH */
773 case 2:
774 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
775 /* FALL THROUGH */
776 case 1:
777 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
778 if (address & 0x01) {
779 if (!thumb) {
780 command_print(CMD_CTX, "Disassemble as Thumb");
781 thumb = 1;
782 }
783 address &= ~1;
784 }
785 break;
786 default:
787 usage:
788 count = 0;
789 retval = ERROR_COMMAND_SYNTAX_ERROR;
790 }
791
792 while (count-- > 0) {
793 struct arm_instruction cur_instruction;
794
795 if (thumb) {
796 /* Always use Thumb2 disassembly for best handling
797 * of 32-bit BL/BLX, and to work with newer cores
798 * (some ARMv6, all ARMv7) that use Thumb2.
799 */
800 retval = thumb2_opcode(target, address,
801 &cur_instruction);
802 if (retval != ERROR_OK)
803 break;
804 } else {
805 uint32_t opcode;
806
807 retval = target_read_u32(target, address, &opcode);
808 if (retval != ERROR_OK)
809 break;
810 retval = arm_evaluate_opcode(opcode, address,
811 &cur_instruction) != ERROR_OK;
812 if (retval != ERROR_OK)
813 break;
814 }
815 command_print(CMD_CTX, "%s", cur_instruction.text);
816 address += cur_instruction.instruction_size;
817 }
818
819 return retval;
820 }
821
822 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
823 {
824 struct command_context *context;
825 struct target *target;
826 struct arm *arm;
827 int retval;
828
829 context = current_command_context(interp);
830 assert( context != NULL);
831
832 target = get_current_target(context);
833 if (target == NULL) {
834 LOG_ERROR("%s: no current target", __func__);
835 return JIM_ERR;
836 }
837 if (!target_was_examined(target)) {
838 LOG_ERROR("%s: not yet examined", target_name(target));
839 return JIM_ERR;
840 }
841 arm = target_to_arm(target);
842 if (!is_arm(arm)) {
843 LOG_ERROR("%s: not an ARM", target_name(target));
844 return JIM_ERR;
845 }
846
847 if ((argc < 6) || (argc > 7)) {
848 /* FIXME use the command name to verify # params... */
849 LOG_ERROR("%s: wrong number of arguments", __func__);
850 return JIM_ERR;
851 }
852
853 int cpnum;
854 uint32_t op1;
855 uint32_t op2;
856 uint32_t CRn;
857 uint32_t CRm;
858 uint32_t value;
859 long l;
860
861 /* NOTE: parameter sequence matches ARM instruction set usage:
862 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
863 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
864 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
865 */
866 retval = Jim_GetLong(interp, argv[1], &l);
867 if (retval != JIM_OK)
868 return retval;
869 if (l & ~0xf) {
870 LOG_ERROR("%s: %s %d out of range", __func__,
871 "coprocessor", (int) l);
872 return JIM_ERR;
873 }
874 cpnum = l;
875
876 retval = Jim_GetLong(interp, argv[2], &l);
877 if (retval != JIM_OK)
878 return retval;
879 if (l & ~0x7) {
880 LOG_ERROR("%s: %s %d out of range", __func__,
881 "op1", (int) l);
882 return JIM_ERR;
883 }
884 op1 = l;
885
886 retval = Jim_GetLong(interp, argv[3], &l);
887 if (retval != JIM_OK)
888 return retval;
889 if (l & ~0xf) {
890 LOG_ERROR("%s: %s %d out of range", __func__,
891 "CRn", (int) l);
892 return JIM_ERR;
893 }
894 CRn = l;
895
896 retval = Jim_GetLong(interp, argv[4], &l);
897 if (retval != JIM_OK)
898 return retval;
899 if (l & ~0xf) {
900 LOG_ERROR("%s: %s %d out of range", __func__,
901 "CRm", (int) l);
902 return JIM_ERR;
903 }
904 CRm = l;
905
906 retval = Jim_GetLong(interp, argv[5], &l);
907 if (retval != JIM_OK)
908 return retval;
909 if (l & ~0x7) {
910 LOG_ERROR("%s: %s %d out of range", __func__,
911 "op2", (int) l);
912 return JIM_ERR;
913 }
914 op2 = l;
915
916 value = 0;
917
918 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
919 * that could easily be a typo! Check both...
920 *
921 * FIXME change the call syntax here ... simplest to just pass
922 * the MRC() or MCR() instruction to be executed. That will also
923 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
924 * if that's ever needed.
925 */
926 if (argc == 7) {
927 retval = Jim_GetLong(interp, argv[6], &l);
928 if (retval != JIM_OK) {
929 return retval;
930 }
931 value = l;
932
933 /* NOTE: parameters reordered! */
934 // ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2)
935 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
936 if (retval != ERROR_OK)
937 return JIM_ERR;
938 } else {
939 /* NOTE: parameters reordered! */
940 // ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2)
941 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
942 if (retval != ERROR_OK)
943 return JIM_ERR;
944
945 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
946 }
947
948 return JIM_OK;
949 }
950
951 COMMAND_HANDLER(handle_arm_semihosting_command)
952 {
953 struct target *target = get_current_target(CMD_CTX);
954
955 if (target == NULL) {
956 LOG_ERROR("No target selected");
957 return ERROR_FAIL;
958 }
959
960 struct arm *arm = target_to_arm(target);
961
962 if (!is_arm(arm)) {
963 command_print(CMD_CTX, "current target isn't an ARM");
964 return ERROR_FAIL;
965 }
966
967 if (!arm->setup_semihosting)
968 {
969 command_print(CMD_CTX, "semihosting not supported for current target");
970 return ERROR_FAIL;
971 }
972
973 if (CMD_ARGC > 0)
974 {
975 int semihosting;
976
977 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
978
979 if (!target_was_examined(target))
980 {
981 LOG_ERROR("Target not examined yet");
982 return ERROR_FAIL;
983 }
984
985 if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
986 LOG_ERROR("Failed to Configure semihosting");
987 return ERROR_FAIL;
988 }
989
990 /* FIXME never let that "catch" be dropped! */
991 arm->is_semihosting = semihosting;
992 }
993
994 command_print(CMD_CTX, "semihosting is %s",
995 arm->is_semihosting
996 ? "enabled" : "disabled");
997
998 return ERROR_OK;
999 }
1000
1001 static const struct command_registration arm_exec_command_handlers[] = {
1002 {
1003 .name = "reg",
1004 .handler = handle_armv4_5_reg_command,
1005 .mode = COMMAND_EXEC,
1006 .help = "display ARM core registers",
1007 .usage = "",
1008 },
1009 {
1010 .name = "core_state",
1011 .handler = handle_armv4_5_core_state_command,
1012 .mode = COMMAND_EXEC,
1013 .usage = "['arm'|'thumb']",
1014 .help = "display/change ARM core state",
1015 },
1016 {
1017 .name = "disassemble",
1018 .handler = handle_arm_disassemble_command,
1019 .mode = COMMAND_EXEC,
1020 .usage = "address [count ['thumb']]",
1021 .help = "disassemble instructions ",
1022 },
1023 {
1024 .name = "mcr",
1025 .mode = COMMAND_EXEC,
1026 .jim_handler = &jim_mcrmrc,
1027 .help = "write coprocessor register",
1028 .usage = "cpnum op1 CRn op2 CRm value",
1029 },
1030 {
1031 .name = "mrc",
1032 .jim_handler = &jim_mcrmrc,
1033 .help = "read coprocessor register",
1034 .usage = "cpnum op1 CRn op2 CRm",
1035 },
1036 {
1037 "semihosting",
1038 .handler = handle_arm_semihosting_command,
1039 .mode = COMMAND_EXEC,
1040 .usage = "['enable'|'disable']",
1041 .help = "activate support for semihosting operations",
1042 },
1043
1044 COMMAND_REGISTRATION_DONE
1045 };
1046 const struct command_registration arm_command_handlers[] = {
1047 {
1048 .name = "arm",
1049 .mode = COMMAND_ANY,
1050 .help = "ARM command group",
1051 .usage = "",
1052 .chain = arm_exec_command_handlers,
1053 },
1054 COMMAND_REGISTRATION_DONE
1055 };
1056
1057 int arm_get_gdb_reg_list(struct target *target,
1058 struct reg **reg_list[], int *reg_list_size)
1059 {
1060 struct arm *arm = target_to_arm(target);
1061 int i;
1062
1063 if (!is_arm_mode(arm->core_mode))
1064 {
1065 LOG_ERROR("not a valid arm core mode - communication failure?");
1066 return ERROR_FAIL;
1067 }
1068
1069 *reg_list_size = 26;
1070 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
1071
1072 for (i = 0; i < 16; i++)
1073 (*reg_list)[i] = arm_reg_current(arm, i);
1074
1075 for (i = 16; i < 24; i++)
1076 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1077
1078 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1079 (*reg_list)[25] = arm->cpsr;
1080
1081 return ERROR_OK;
1082 }
1083
1084 /* wait for execution to complete and check exit point */
1085 static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
1086 {
1087 int retval;
1088 struct arm *arm = target_to_arm(target);
1089
1090 if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
1091 {
1092 return retval;
1093 }
1094 if (target->state != TARGET_HALTED)
1095 {
1096 if ((retval = target_halt(target)) != ERROR_OK)
1097 return retval;
1098 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
1099 {
1100 return retval;
1101 }
1102 return ERROR_TARGET_TIMEOUT;
1103 }
1104
1105 /* fast exit: ARMv5+ code can use BKPT */
1106 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point)
1107 {
1108 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1109 buf_get_u32(arm->pc->value, 0, 32));
1110 return ERROR_TARGET_TIMEOUT;
1111 }
1112
1113 return ERROR_OK;
1114 }
1115
1116 int armv4_5_run_algorithm_inner(struct target *target,
1117 int num_mem_params, struct mem_param *mem_params,
1118 int num_reg_params, struct reg_param *reg_params,
1119 uint32_t entry_point, uint32_t exit_point,
1120 int timeout_ms, void *arch_info,
1121 int (*run_it)(struct target *target, uint32_t exit_point,
1122 int timeout_ms, void *arch_info))
1123 {
1124 struct arm *arm = target_to_arm(target);
1125 struct arm_algorithm *arm_algorithm_info = arch_info;
1126 enum arm_state core_state = arm->core_state;
1127 uint32_t context[17];
1128 uint32_t cpsr;
1129 int exit_breakpoint_size = 0;
1130 int i;
1131 int retval = ERROR_OK;
1132
1133 LOG_DEBUG("Running algorithm");
1134
1135 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC)
1136 {
1137 LOG_ERROR("current target isn't an ARMV4/5 target");
1138 return ERROR_TARGET_INVALID;
1139 }
1140
1141 if (target->state != TARGET_HALTED)
1142 {
1143 LOG_WARNING("target not halted");
1144 return ERROR_TARGET_NOT_HALTED;
1145 }
1146
1147 if (!is_arm_mode(arm->core_mode))
1148 {
1149 LOG_ERROR("not a valid arm core mode - communication failure?");
1150 return ERROR_FAIL;
1151 }
1152
1153 /* armv5 and later can terminate with BKPT instruction; less overhead */
1154 if (!exit_point && arm->is_armv4)
1155 {
1156 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1157 return ERROR_FAIL;
1158 }
1159
1160 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1161 * they'll be restored later.
1162 */
1163 for (i = 0; i <= 16; i++)
1164 {
1165 struct reg *r;
1166
1167 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1168 arm_algorithm_info->core_mode, i);
1169 if (!r->valid)
1170 arm->read_core_reg(target, r, i,
1171 arm_algorithm_info->core_mode);
1172 context[i] = buf_get_u32(r->value, 0, 32);
1173 }
1174 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1175
1176 for (i = 0; i < num_mem_params; i++)
1177 {
1178 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
1179 {
1180 return retval;
1181 }
1182 }
1183
1184 for (i = 0; i < num_reg_params; i++)
1185 {
1186 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1187 if (!reg)
1188 {
1189 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1190 return ERROR_COMMAND_SYNTAX_ERROR;
1191 }
1192
1193 if (reg->size != reg_params[i].size)
1194 {
1195 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1196 return ERROR_COMMAND_SYNTAX_ERROR;
1197 }
1198
1199 if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
1200 {
1201 return retval;
1202 }
1203 }
1204
1205 arm->core_state = arm_algorithm_info->core_state;
1206 if (arm->core_state == ARM_STATE_ARM)
1207 exit_breakpoint_size = 4;
1208 else if (arm->core_state == ARM_STATE_THUMB)
1209 exit_breakpoint_size = 2;
1210 else
1211 {
1212 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1213 return ERROR_COMMAND_SYNTAX_ERROR;
1214 }
1215
1216 if (arm_algorithm_info->core_mode != ARM_MODE_ANY)
1217 {
1218 LOG_DEBUG("setting core_mode: 0x%2.2x",
1219 arm_algorithm_info->core_mode);
1220 buf_set_u32(arm->cpsr->value, 0, 5,
1221 arm_algorithm_info->core_mode);
1222 arm->cpsr->dirty = 1;
1223 arm->cpsr->valid = 1;
1224 }
1225
1226 /* terminate using a hardware or (ARMv5+) software breakpoint */
1227 if (exit_point && (retval = breakpoint_add(target, exit_point,
1228 exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1229 {
1230 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1231 return ERROR_TARGET_FAILURE;
1232 }
1233
1234 if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
1235 {
1236 return retval;
1237 }
1238 int retvaltemp;
1239 retval = run_it(target, exit_point, timeout_ms, arch_info);
1240
1241 if (exit_point)
1242 breakpoint_remove(target, exit_point);
1243
1244 if (retval != ERROR_OK)
1245 return retval;
1246
1247 for (i = 0; i < num_mem_params; i++)
1248 {
1249 if (mem_params[i].direction != PARAM_OUT)
1250 if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
1251 {
1252 retval = retvaltemp;
1253 }
1254 }
1255
1256 for (i = 0; i < num_reg_params; i++)
1257 {
1258 if (reg_params[i].direction != PARAM_OUT)
1259 {
1260
1261 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1262 if (!reg)
1263 {
1264 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1265 retval = ERROR_COMMAND_SYNTAX_ERROR;
1266 continue;
1267 }
1268
1269 if (reg->size != reg_params[i].size)
1270 {
1271 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1272 retval = ERROR_COMMAND_SYNTAX_ERROR;
1273 continue;
1274 }
1275
1276 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1277 }
1278 }
1279
1280 /* restore everything we saved before (17 or 18 registers) */
1281 for (i = 0; i <= 16; i++)
1282 {
1283 uint32_t regvalue;
1284 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1285 arm_algorithm_info->core_mode, i).value, 0, 32);
1286 if (regvalue != context[i])
1287 {
1288 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1289 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1290 arm_algorithm_info->core_mode, i).name, context[i]);
1291 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1292 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1293 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).valid = 1;
1294 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).dirty = 1;
1295 }
1296 }
1297
1298 arm_set_cpsr(arm, cpsr);
1299 arm->cpsr->dirty = 1;
1300
1301 arm->core_state = core_state;
1302
1303 return retval;
1304 }
1305
1306 int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
1307 {
1308 return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
1309 }
1310
1311 /**
1312 * Runs ARM code in the target to calculate a CRC32 checksum.
1313 *
1314 */
1315 int arm_checksum_memory(struct target *target,
1316 uint32_t address, uint32_t count, uint32_t *checksum)
1317 {
1318 struct working_area *crc_algorithm;
1319 struct arm_algorithm armv4_5_info;
1320 struct arm *arm = target_to_arm(target);
1321 struct reg_param reg_params[2];
1322 int retval;
1323 uint32_t i;
1324 uint32_t exit_var = 0;
1325
1326 /* see contib/loaders/checksum/armv4_5_crc.s for src */
1327
1328 static const uint32_t arm_crc_code[] = {
1329 0xE1A02000, /* mov r2, r0 */
1330 0xE3E00000, /* mov r0, #0xffffffff */
1331 0xE1A03001, /* mov r3, r1 */
1332 0xE3A04000, /* mov r4, #0 */
1333 0xEA00000B, /* b ncomp */
1334 /* nbyte: */
1335 0xE7D21004, /* ldrb r1, [r2, r4] */
1336 0xE59F7030, /* ldr r7, CRC32XOR */
1337 0xE0200C01, /* eor r0, r0, r1, asl 24 */
1338 0xE3A05000, /* mov r5, #0 */
1339 /* loop: */
1340 0xE3500000, /* cmp r0, #0 */
1341 0xE1A06080, /* mov r6, r0, asl #1 */
1342 0xE2855001, /* add r5, r5, #1 */
1343 0xE1A00006, /* mov r0, r6 */
1344 0xB0260007, /* eorlt r0, r6, r7 */
1345 0xE3550008, /* cmp r5, #8 */
1346 0x1AFFFFF8, /* bne loop */
1347 0xE2844001, /* add r4, r4, #1 */
1348 /* ncomp: */
1349 0xE1540003, /* cmp r4, r3 */
1350 0x1AFFFFF1, /* bne nbyte */
1351 /* end: */
1352 0xe1200070, /* bkpt #0 */
1353 /* CRC32XOR: */
1354 0x04C11DB7 /* .word 0x04C11DB7 */
1355 };
1356
1357 retval = target_alloc_working_area(target,
1358 sizeof(arm_crc_code), &crc_algorithm);
1359 if (retval != ERROR_OK)
1360 return retval;
1361
1362 /* convert code into a buffer in target endianness */
1363 for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
1364 retval = target_write_u32(target,
1365 crc_algorithm->address + i * sizeof(uint32_t),
1366 arm_crc_code[i]);
1367 if (retval != ERROR_OK)
1368 return retval;
1369 }
1370
1371 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1372 armv4_5_info.core_mode = ARM_MODE_SVC;
1373 armv4_5_info.core_state = ARM_STATE_ARM;
1374
1375 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
1376 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1377
1378 buf_set_u32(reg_params[0].value, 0, 32, address);
1379 buf_set_u32(reg_params[1].value, 0, 32, count);
1380
1381 /* 20 second timeout/megabyte */
1382 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1383
1384 /* armv4 must exit using a hardware breakpoint */
1385 if (arm->is_armv4)
1386 exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
1387
1388 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1389 crc_algorithm->address,
1390 exit_var,
1391 timeout, &armv4_5_info);
1392 if (retval != ERROR_OK) {
1393 LOG_ERROR("error executing ARM crc algorithm");
1394 destroy_reg_param(&reg_params[0]);
1395 destroy_reg_param(&reg_params[1]);
1396 target_free_working_area(target, crc_algorithm);
1397 return retval;
1398 }
1399
1400 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1401
1402 destroy_reg_param(&reg_params[0]);
1403 destroy_reg_param(&reg_params[1]);
1404
1405 target_free_working_area(target, crc_algorithm);
1406
1407 return ERROR_OK;
1408 }
1409
1410 /**
1411 * Runs ARM code in the target to check whether a memory block holds
1412 * all ones. NOR flash which has been erased, and thus may be written,
1413 * holds all ones.
1414 *
1415 */
1416 int arm_blank_check_memory(struct target *target,
1417 uint32_t address, uint32_t count, uint32_t *blank)
1418 {
1419 struct working_area *check_algorithm;
1420 struct reg_param reg_params[3];
1421 struct arm_algorithm armv4_5_info;
1422 struct arm *arm = target_to_arm(target);
1423 int retval;
1424 uint32_t i;
1425 uint32_t exit_var = 0;
1426
1427 static const uint32_t check_code[] = {
1428 /* loop: */
1429 0xe4d03001, /* ldrb r3, [r0], #1 */
1430 0xe0022003, /* and r2, r2, r3 */
1431 0xe2511001, /* subs r1, r1, #1 */
1432 0x1afffffb, /* bne loop */
1433 /* end: */
1434 0xe1200070, /* bkpt #0 */
1435 };
1436
1437 /* make sure we have a working area */
1438 retval = target_alloc_working_area(target,
1439 sizeof(check_code), &check_algorithm);
1440 if (retval != ERROR_OK)
1441 return retval;
1442
1443 /* convert code into a buffer in target endianness */
1444 for (i = 0; i < ARRAY_SIZE(check_code); i++) {
1445 retval = target_write_u32(target,
1446 check_algorithm->address
1447 + i * sizeof(uint32_t),
1448 check_code[i]);
1449 if (retval != ERROR_OK)
1450 return retval;
1451 }
1452
1453 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1454 armv4_5_info.core_mode = ARM_MODE_SVC;
1455 armv4_5_info.core_state = ARM_STATE_ARM;
1456
1457 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1458 buf_set_u32(reg_params[0].value, 0, 32, address);
1459
1460 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1461 buf_set_u32(reg_params[1].value, 0, 32, count);
1462
1463 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1464 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
1465
1466 /* armv4 must exit using a hardware breakpoint */
1467 if (arm->is_armv4)
1468 exit_var = check_algorithm->address + sizeof(check_code) - 4;
1469
1470 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1471 check_algorithm->address,
1472 exit_var,
1473 10000, &armv4_5_info);
1474 if (retval != ERROR_OK) {
1475 destroy_reg_param(&reg_params[0]);
1476 destroy_reg_param(&reg_params[1]);
1477 destroy_reg_param(&reg_params[2]);
1478 target_free_working_area(target, check_algorithm);
1479 return retval;
1480 }
1481
1482 *blank = buf_get_u32(reg_params[2].value, 0, 32);
1483
1484 destroy_reg_param(&reg_params[0]);
1485 destroy_reg_param(&reg_params[1]);
1486 destroy_reg_param(&reg_params[2]);
1487
1488 target_free_working_area(target, check_algorithm);
1489
1490 return ERROR_OK;
1491 }
1492
1493 static int arm_full_context(struct target *target)
1494 {
1495 struct arm *arm = target_to_arm(target);
1496 unsigned num_regs = arm->core_cache->num_regs;
1497 struct reg *reg = arm->core_cache->reg_list;
1498 int retval = ERROR_OK;
1499
1500 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1501 if (reg->valid)
1502 continue;
1503 retval = armv4_5_get_core_reg(reg);
1504 }
1505 return retval;
1506 }
1507
1508 static int arm_default_mrc(struct target *target, int cpnum,
1509 uint32_t op1, uint32_t op2,
1510 uint32_t CRn, uint32_t CRm,
1511 uint32_t *value)
1512 {
1513 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1514 return ERROR_FAIL;
1515 }
1516
1517 static int arm_default_mcr(struct target *target, int cpnum,
1518 uint32_t op1, uint32_t op2,
1519 uint32_t CRn, uint32_t CRm,
1520 uint32_t value)
1521 {
1522 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1523 return ERROR_FAIL;
1524 }
1525
1526 int arm_init_arch_info(struct target *target, struct arm *arm)
1527 {
1528 target->arch_info = arm;
1529 arm->target = target;
1530
1531 arm->common_magic = ARM_COMMON_MAGIC;
1532
1533 /* core_type may be overridden by subtype logic */
1534 if (arm->core_type != ARM_MODE_THREAD) {
1535 arm->core_type = ARM_MODE_ANY;
1536 arm_set_cpsr(arm, ARM_MODE_USR);
1537 }
1538
1539 /* default full_context() has no core-specific optimizations */
1540 if (!arm->full_context && arm->read_core_reg)
1541 arm->full_context = arm_full_context;
1542
1543 if (!arm->mrc)
1544 arm->mrc = arm_default_mrc;
1545 if (!arm->mcr)
1546 arm->mcr = arm_default_mcr;
1547
1548 return ERROR_OK;
1549 }
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