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ARM: define two register utilities
[openocd.git] / src / target / armv4_5.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "armv4_5.h"
31 #include "arm_jtag.h"
32 #include "breakpoints.h"
33 #include "arm_disassembler.h"
34 #include "binarybuffer.h"
35 #include "algorithm.h"
36 #include "register.h"
37
38
39 /* offsets into armv4_5 core register cache */
40 enum {
41 // ARMV4_5_CPSR = 31,
42 ARMV4_5_SPSR_FIQ = 32,
43 ARMV4_5_SPSR_IRQ = 33,
44 ARMV4_5_SPSR_SVC = 34,
45 ARMV4_5_SPSR_ABT = 35,
46 ARMV4_5_SPSR_UND = 36,
47 ARM_SPSR_MON = 39,
48 };
49
50 static const uint8_t arm_usr_indices[17] = {
51 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
52 };
53
54 static const uint8_t arm_fiq_indices[8] = {
55 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
56 };
57
58 static const uint8_t arm_irq_indices[3] = {
59 23, 24, ARMV4_5_SPSR_IRQ,
60 };
61
62 static const uint8_t arm_svc_indices[3] = {
63 25, 26, ARMV4_5_SPSR_SVC,
64 };
65
66 static const uint8_t arm_abt_indices[3] = {
67 27, 28, ARMV4_5_SPSR_ABT,
68 };
69
70 static const uint8_t arm_und_indices[3] = {
71 29, 30, ARMV4_5_SPSR_UND,
72 };
73
74 static const uint8_t arm_mon_indices[3] = {
75 37, 38, ARM_SPSR_MON,
76 };
77
78 static const struct {
79 const char *name;
80 unsigned short psr;
81 /* For user and system modes, these list indices for all registers.
82 * otherwise they're just indices for the shadow registers and SPSR.
83 */
84 unsigned short n_indices;
85 const uint8_t *indices;
86 } arm_mode_data[] = {
87 /* Seven modes are standard from ARM7 on. "System" and "User" share
88 * the same registers; other modes shadow from 3 to 8 registers.
89 */
90 {
91 .name = "User",
92 .psr = ARMV4_5_MODE_USR,
93 .n_indices = ARRAY_SIZE(arm_usr_indices),
94 .indices = arm_usr_indices,
95 },
96 {
97 .name = "FIQ",
98 .psr = ARMV4_5_MODE_FIQ,
99 .n_indices = ARRAY_SIZE(arm_fiq_indices),
100 .indices = arm_fiq_indices,
101 },
102 {
103 .name = "Supervisor",
104 .psr = ARMV4_5_MODE_SVC,
105 .n_indices = ARRAY_SIZE(arm_svc_indices),
106 .indices = arm_svc_indices,
107 },
108 {
109 .name = "Abort",
110 .psr = ARMV4_5_MODE_ABT,
111 .n_indices = ARRAY_SIZE(arm_abt_indices),
112 .indices = arm_abt_indices,
113 },
114 {
115 .name = "IRQ",
116 .psr = ARMV4_5_MODE_IRQ,
117 .n_indices = ARRAY_SIZE(arm_irq_indices),
118 .indices = arm_irq_indices,
119 },
120 {
121 .name = "Undefined instruction",
122 .psr = ARMV4_5_MODE_UND,
123 .n_indices = ARRAY_SIZE(arm_und_indices),
124 .indices = arm_und_indices,
125 },
126 {
127 .name = "System",
128 .psr = ARMV4_5_MODE_SYS,
129 .n_indices = ARRAY_SIZE(arm_usr_indices),
130 .indices = arm_usr_indices,
131 },
132 /* TrustZone "Security Extensions" add a secure monitor mode.
133 * This is distinct from a "debug monitor" which can support
134 * non-halting debug, in conjunction with some debuggers.
135 */
136 {
137 .name = "Secure Monitor",
138 .psr = ARM_MODE_MON,
139 .n_indices = ARRAY_SIZE(arm_mon_indices),
140 .indices = arm_mon_indices,
141 },
142 };
143
144 /** Map PSR mode bits to the name of an ARM processor operating mode. */
145 const char *arm_mode_name(unsigned psr_mode)
146 {
147 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
148 if (arm_mode_data[i].psr == psr_mode)
149 return arm_mode_data[i].name;
150 }
151 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
152 return "UNRECOGNIZED";
153 }
154
155 /** Return true iff the parameter denotes a valid ARM processor mode. */
156 bool is_arm_mode(unsigned psr_mode)
157 {
158 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
159 if (arm_mode_data[i].psr == psr_mode)
160 return true;
161 }
162 return false;
163 }
164
165 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
166 int armv4_5_mode_to_number(enum armv4_5_mode mode)
167 {
168 switch (mode) {
169 case ARMV4_5_MODE_ANY:
170 /* map MODE_ANY to user mode */
171 case ARMV4_5_MODE_USR:
172 return 0;
173 case ARMV4_5_MODE_FIQ:
174 return 1;
175 case ARMV4_5_MODE_IRQ:
176 return 2;
177 case ARMV4_5_MODE_SVC:
178 return 3;
179 case ARMV4_5_MODE_ABT:
180 return 4;
181 case ARMV4_5_MODE_UND:
182 return 5;
183 case ARMV4_5_MODE_SYS:
184 return 6;
185 case ARM_MODE_MON:
186 return 7;
187 default:
188 LOG_ERROR("invalid mode value encountered %d", mode);
189 return -1;
190 }
191 }
192
193 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
194 enum armv4_5_mode armv4_5_number_to_mode(int number)
195 {
196 switch (number) {
197 case 0:
198 return ARMV4_5_MODE_USR;
199 case 1:
200 return ARMV4_5_MODE_FIQ;
201 case 2:
202 return ARMV4_5_MODE_IRQ;
203 case 3:
204 return ARMV4_5_MODE_SVC;
205 case 4:
206 return ARMV4_5_MODE_ABT;
207 case 5:
208 return ARMV4_5_MODE_UND;
209 case 6:
210 return ARMV4_5_MODE_SYS;
211 case 7:
212 return ARM_MODE_MON;
213 default:
214 LOG_ERROR("mode index out of bounds %d", number);
215 return ARMV4_5_MODE_ANY;
216 }
217 }
218
219 char* armv4_5_state_strings[] =
220 {
221 "ARM", "Thumb", "Jazelle", "ThumbEE",
222 };
223
224 /* Templates for ARM core registers.
225 *
226 * NOTE: offsets in this table are coupled to the arm_mode_data
227 * table above, the armv4_5_core_reg_map array below, and also to
228 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
229 */
230 static const struct {
231 /* The name is used for e.g. the "regs" command. */
232 const char *name;
233
234 /* The {cookie, mode} tuple uniquely identifies one register.
235 * In a given mode, cookies 0..15 map to registers R0..R15,
236 * with R13..R15 usually called SP, LR, PC.
237 *
238 * MODE_ANY is used as *input* to the mapping, and indicates
239 * various special cases (sigh) and errors.
240 *
241 * Cookie 16 is (currently) confusing, since it indicates
242 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
243 * (Exception modes have both CPSR and SPSR registers ...)
244 */
245 unsigned cookie;
246 enum armv4_5_mode mode;
247 } arm_core_regs[] = {
248 /* IMPORTANT: we guarantee that the first eight cached registers
249 * correspond to r0..r7, and the fifteenth to PC, so that callers
250 * don't need to map them.
251 */
252 { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
253 { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
254 { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
255 { .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, },
256 { .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, },
257 { .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, },
258 { .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, },
259 { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
260
261 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
262 * them as MODE_ANY creates special cases. (ANY means
263 * "not mapped" elsewhere; here it's "everything but FIQ".)
264 */
265 { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
266 { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
267 { .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, },
268 { .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, },
269 { .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, },
270
271 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
272 { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
273 { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
274
275 /* guaranteed to be at index 15 */
276 { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
277
278 { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
279 { .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, },
280 { .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, },
281 { .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, },
282 { .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, },
283
284 { .name = "lr_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, },
285 { .name = "sp_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, },
286
287 { .name = "lr_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, },
288 { .name = "sp_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, },
289
290 { .name = "lr_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, },
291 { .name = "sp_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, },
292
293 { .name = "lr_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, },
294 { .name = "sp_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, },
295
296 { .name = "lr_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, },
297 { .name = "sp_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, },
298
299 { .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, },
300 { .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, },
301 { .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, },
302 { .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, },
303 { .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, },
304 { .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, },
305
306 { .name = "lr_mon", .cookie = 13, .mode = ARM_MODE_MON, },
307 { .name = "sp_mon", .cookie = 14, .mode = ARM_MODE_MON, },
308 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
309 };
310
311 /* map core mode (USR, FIQ, ...) and register number to
312 * indices into the register cache
313 */
314 const int armv4_5_core_reg_map[8][17] =
315 {
316 { /* USR */
317 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
318 },
319 { /* FIQ (8 shadows of USR, vs normal 3) */
320 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
321 },
322 { /* IRQ */
323 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
324 },
325 { /* SVC */
326 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
327 },
328 { /* ABT */
329 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
330 },
331 { /* UND */
332 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
333 },
334 { /* SYS (same registers as USR) */
335 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
336 },
337 { /* MON */
338 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
339 }
340 };
341
342 /**
343 * Configures host-side ARM records to reflect the specified CPSR.
344 * Later, code can use arm_reg_current() to map register numbers
345 * according to how they are exposed by this mode.
346 */
347 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
348 {
349 enum armv4_5_mode mode = cpsr & 0x1f;
350 int num;
351
352 /* NOTE: this may be called very early, before the register
353 * cache is set up. We can't defend against many errors, in
354 * particular against CPSRs that aren't valid *here* ...
355 */
356 if (arm->cpsr) {
357 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
358 arm->cpsr->valid = 1;
359 arm->cpsr->dirty = 0;
360 }
361
362 arm->core_mode = mode;
363
364 /* mode_to_number() warned; set up a somewhat-sane mapping */
365 num = armv4_5_mode_to_number(mode);
366 if (num < 0) {
367 mode = ARMV4_5_MODE_USR;
368 num = 0;
369 }
370
371 arm->map = &armv4_5_core_reg_map[num][0];
372 arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS)
373 ? NULL
374 : arm->core_cache->reg_list + arm->map[16];
375 }
376
377 /**
378 * Returns handle to the register currently mapped to a given number.
379 * Someone must have called arm_set_cpsr() before.
380 *
381 * \param arm This core's state and registers are used.
382 * \param regnum From 0..15 corresponding to R0..R14 and PC.
383 * Note that R0..R7 don't require mapping; you may access those
384 * as the first eight entries in the register cache. Likewise
385 * R15 (PC) doesn't need mapping; you may also access it directly.
386 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
387 * CPSR (arm->cpsr) is also not mapped.
388 */
389 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
390 {
391 struct reg *r;
392
393 if (regnum > 16)
394 return NULL;
395
396 r = arm->core_cache->reg_list + arm->map[regnum];
397
398 /* e.g. invalid CPSR said "secure monitor" mode on a core
399 * that doesn't support it...
400 */
401 if (!r) {
402 LOG_ERROR("Invalid CPSR mode");
403 r = arm->core_cache->reg_list + regnum;
404 }
405
406 return r;
407 }
408
409 static const uint8_t arm_gdb_dummy_fp_value[12];
410
411 /**
412 * Dummy FPA registers are required to support GDB on ARM.
413 * Register packets require eight obsolete FPA register values.
414 * Modern ARM cores use Vector Floating Point (VFP), if they
415 * have any floating point support. VFP is not FPA-compatible.
416 */
417 struct reg arm_gdb_dummy_fp_reg =
418 {
419 .name = "GDB dummy FPA register",
420 .value = (uint8_t *) arm_gdb_dummy_fp_value,
421 .valid = 1,
422 .size = 96,
423 };
424
425 static const uint8_t arm_gdb_dummy_fps_value[4];
426
427 /**
428 * Dummy FPA status registers are required to support GDB on ARM.
429 * Register packets require an obsolete FPA status register.
430 */
431 struct reg arm_gdb_dummy_fps_reg =
432 {
433 .name = "GDB dummy FPA status register",
434 .value = (uint8_t *) arm_gdb_dummy_fps_value,
435 .valid = 1,
436 .size = 32,
437 };
438
439 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
440
441 static void arm_gdb_dummy_init(void)
442 {
443 register_init_dummy(&arm_gdb_dummy_fp_reg);
444 register_init_dummy(&arm_gdb_dummy_fps_reg);
445 }
446
447 static int armv4_5_get_core_reg(struct reg *reg)
448 {
449 int retval;
450 struct arm_reg *armv4_5 = reg->arch_info;
451 struct target *target = armv4_5->target;
452
453 if (target->state != TARGET_HALTED)
454 {
455 LOG_ERROR("Target not halted");
456 return ERROR_TARGET_NOT_HALTED;
457 }
458
459 retval = armv4_5->armv4_5_common->read_core_reg(target, reg, armv4_5->num, armv4_5->mode);
460 if (retval == ERROR_OK) {
461 reg->valid = 1;
462 reg->dirty = 0;
463 }
464
465 return retval;
466 }
467
468 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
469 {
470 struct arm_reg *armv4_5 = reg->arch_info;
471 struct target *target = armv4_5->target;
472 struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
473 uint32_t value = buf_get_u32(buf, 0, 32);
474
475 if (target->state != TARGET_HALTED)
476 {
477 LOG_ERROR("Target not halted");
478 return ERROR_TARGET_NOT_HALTED;
479 }
480
481 /* Except for CPSR, the "reg" command exposes a writeback model
482 * for the register cache.
483 */
484 buf_set_u32(reg->value, 0, 32, value);
485 reg->dirty = 1;
486 reg->valid = 1;
487
488 if (reg == armv4_5_target->cpsr)
489 {
490 /* FIXME handle J bit too; mostly for ThumbEE, also Jazelle */
491 if (value & 0x20)
492 {
493 /* T bit should be set */
494 if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
495 {
496 /* change state to Thumb */
497 LOG_DEBUG("changing to Thumb state");
498 armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
499 }
500 }
501 else
502 {
503 /* T bit should be cleared */
504 if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
505 {
506 /* change state to ARM */
507 LOG_DEBUG("changing to ARM state");
508 armv4_5_target->core_state = ARMV4_5_STATE_ARM;
509 }
510 }
511
512 /* REVISIT Why only update core for mode change, not also
513 * for state changes? Possibly older cores need to stay
514 * in ARM mode during halt mode debug, not execute Thumb;
515 * v6/v7a/v7r seem to do that automatically...
516 */
517
518 if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
519 {
520 LOG_DEBUG("changing ARM core mode to '%s'",
521 arm_mode_name(value & 0x1f));
522 armv4_5_target->write_core_reg(target, reg,
523 16, ARMV4_5_MODE_ANY, value);
524 arm_set_cpsr(armv4_5_target, value);
525 }
526 }
527
528 return ERROR_OK;
529 }
530
531 static const struct reg_arch_type arm_reg_type = {
532 .get = armv4_5_get_core_reg,
533 .set = armv4_5_set_core_reg,
534 };
535
536 struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
537 {
538 int num_regs = ARRAY_SIZE(arm_core_regs);
539 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
540 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
541 struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
542 int i;
543
544 if (!cache || !reg_list || !arch_info) {
545 free(cache);
546 free(reg_list);
547 free(arch_info);
548 return NULL;
549 }
550
551 cache->name = "ARM registers";
552 cache->next = NULL;
553 cache->reg_list = reg_list;
554 cache->num_regs = 0;
555
556 for (i = 0; i < num_regs; i++)
557 {
558 /* Skip registers this core doesn't expose */
559 if (arm_core_regs[i].mode == ARM_MODE_MON
560 && armv4_5_common->core_type != ARM_MODE_MON)
561 continue;
562
563 /* REVISIT handle Cortex-M, which only shadows R13/SP */
564
565 arch_info[i].num = arm_core_regs[i].cookie;
566 arch_info[i].mode = arm_core_regs[i].mode;
567 arch_info[i].target = target;
568 arch_info[i].armv4_5_common = armv4_5_common;
569
570 reg_list[i].name = (char *) arm_core_regs[i].name;
571 reg_list[i].size = 32;
572 reg_list[i].value = &arch_info[i].value;
573 reg_list[i].type = &arm_reg_type;
574 reg_list[i].arch_info = &arch_info[i];
575
576 cache->num_regs++;
577 }
578
579 armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
580 armv4_5_common->core_cache = cache;
581 return cache;
582 }
583
584 int armv4_5_arch_state(struct target *target)
585 {
586 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
587
588 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
589 {
590 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
591 return ERROR_FAIL;
592 }
593
594 LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
595 armv4_5_state_strings[armv4_5->core_state],
596 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
597 arm_mode_name(armv4_5->core_mode),
598 buf_get_u32(armv4_5->cpsr->value, 0, 32),
599 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
600
601 return ERROR_OK;
602 }
603
604 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
605 cache->reg_list[armv4_5_core_reg_map[mode][num]]
606
607 COMMAND_HANDLER(handle_armv4_5_reg_command)
608 {
609 struct target *target = get_current_target(CMD_CTX);
610 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
611 unsigned num_regs;
612 struct reg *regs;
613
614 if (!is_arm(armv4_5))
615 {
616 command_print(CMD_CTX, "current target isn't an ARM");
617 return ERROR_FAIL;
618 }
619
620 if (target->state != TARGET_HALTED)
621 {
622 command_print(CMD_CTX, "error: target must be halted for register accesses");
623 return ERROR_FAIL;
624 }
625
626 if (!is_arm_mode(armv4_5->core_mode))
627 return ERROR_FAIL;
628
629 if (!armv4_5->full_context) {
630 command_print(CMD_CTX, "error: target doesn't support %s",
631 CMD_NAME);
632 return ERROR_FAIL;
633 }
634
635 num_regs = armv4_5->core_cache->num_regs;
636 regs = armv4_5->core_cache->reg_list;
637
638 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
639 const char *name;
640 char *sep = "\n";
641 char *shadow = "";
642
643 /* label this bank of registers (or shadows) */
644 switch (arm_mode_data[mode].psr) {
645 case ARMV4_5_MODE_SYS:
646 continue;
647 case ARMV4_5_MODE_USR:
648 name = "System and User";
649 sep = "";
650 break;
651 case ARM_MODE_MON:
652 if (armv4_5->core_type != ARM_MODE_MON)
653 continue;
654 /* FALLTHROUGH */
655 default:
656 name = arm_mode_data[mode].name;
657 shadow = "shadow ";
658 break;
659 }
660 command_print(CMD_CTX, "%s%s mode %sregisters",
661 sep, name, shadow);
662
663 /* display N rows of up to 4 registers each */
664 for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) {
665 char output[80];
666 int output_len = 0;
667
668 for (unsigned j = 0; j < 4; j++, i++) {
669 uint32_t value;
670 struct reg *reg = regs;
671
672 if (i >= arm_mode_data[mode].n_indices)
673 break;
674
675 reg += arm_mode_data[mode].indices[i];
676
677 /* REVISIT be smarter about faults... */
678 if (!reg->valid)
679 armv4_5->full_context(target);
680
681 value = buf_get_u32(reg->value, 0, 32);
682 output_len += snprintf(output + output_len,
683 sizeof(output) - output_len,
684 "%8s: %8.8" PRIx32 " ",
685 reg->name, value);
686 }
687 command_print(CMD_CTX, "%s", output);
688 }
689 }
690
691 return ERROR_OK;
692 }
693
694 COMMAND_HANDLER(handle_armv4_5_core_state_command)
695 {
696 struct target *target = get_current_target(CMD_CTX);
697 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
698
699 if (!is_arm(armv4_5))
700 {
701 command_print(CMD_CTX, "current target isn't an ARM");
702 return ERROR_FAIL;
703 }
704
705 if (CMD_ARGC > 0)
706 {
707 if (strcmp(CMD_ARGV[0], "arm") == 0)
708 {
709 armv4_5->core_state = ARMV4_5_STATE_ARM;
710 }
711 if (strcmp(CMD_ARGV[0], "thumb") == 0)
712 {
713 armv4_5->core_state = ARMV4_5_STATE_THUMB;
714 }
715 }
716
717 command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
718
719 return ERROR_OK;
720 }
721
722 COMMAND_HANDLER(handle_armv4_5_disassemble_command)
723 {
724 int retval = ERROR_OK;
725 struct target *target = get_current_target(CMD_CTX);
726 struct arm *arm = target ? target_to_arm(target) : NULL;
727 uint32_t address;
728 int count = 1;
729 int thumb = 0;
730
731 if (!is_arm(arm)) {
732 command_print(CMD_CTX, "current target isn't an ARM");
733 return ERROR_FAIL;
734 }
735
736 switch (CMD_ARGC) {
737 case 3:
738 if (strcmp(CMD_ARGV[2], "thumb") != 0)
739 goto usage;
740 thumb = 1;
741 /* FALL THROUGH */
742 case 2:
743 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
744 /* FALL THROUGH */
745 case 1:
746 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
747 if (address & 0x01) {
748 if (!thumb) {
749 command_print(CMD_CTX, "Disassemble as Thumb");
750 thumb = 1;
751 }
752 address &= ~1;
753 }
754 break;
755 default:
756 usage:
757 command_print(CMD_CTX,
758 "usage: arm disassemble <address> [<count> ['thumb']]");
759 count = 0;
760 retval = ERROR_FAIL;
761 }
762
763 while (count-- > 0) {
764 struct arm_instruction cur_instruction;
765
766 if (thumb) {
767 /* Always use Thumb2 disassembly for best handling
768 * of 32-bit BL/BLX, and to work with newer cores
769 * (some ARMv6, all ARMv7) that use Thumb2.
770 */
771 retval = thumb2_opcode(target, address,
772 &cur_instruction);
773 if (retval != ERROR_OK)
774 break;
775 } else {
776 uint32_t opcode;
777
778 retval = target_read_u32(target, address, &opcode);
779 if (retval != ERROR_OK)
780 break;
781 retval = arm_evaluate_opcode(opcode, address,
782 &cur_instruction) != ERROR_OK;
783 if (retval != ERROR_OK)
784 break;
785 }
786 command_print(CMD_CTX, "%s", cur_instruction.text);
787 address += cur_instruction.instruction_size;
788 }
789
790 return retval;
791 }
792
793 int armv4_5_register_commands(struct command_context *cmd_ctx)
794 {
795 struct command *armv4_5_cmd;
796
797 armv4_5_cmd = register_command(cmd_ctx, NULL, "arm",
798 NULL, COMMAND_ANY,
799 "generic ARM commands");
800
801 register_command(cmd_ctx, armv4_5_cmd, "reg",
802 handle_armv4_5_reg_command, COMMAND_EXEC,
803 "display ARM core registers");
804 register_command(cmd_ctx, armv4_5_cmd, "core_state",
805 handle_armv4_5_core_state_command, COMMAND_EXEC,
806 "display/change ARM core state <arm | thumb>");
807 register_command(cmd_ctx, armv4_5_cmd, "disassemble",
808 handle_armv4_5_disassemble_command, COMMAND_EXEC,
809 "disassemble instructions "
810 "<address> [<count> ['thumb']]");
811
812 return ERROR_OK;
813 }
814
815 int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
816 {
817 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
818 int i;
819
820 if (!is_arm_mode(armv4_5->core_mode))
821 return ERROR_FAIL;
822
823 *reg_list_size = 26;
824 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
825
826 for (i = 0; i < 16; i++)
827 (*reg_list)[i] = arm_reg_current(armv4_5, i);
828
829 for (i = 16; i < 24; i++)
830 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
831
832 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
833 (*reg_list)[25] = armv4_5->cpsr;
834
835 return ERROR_OK;
836 }
837
838 /* wait for execution to complete and check exit point */
839 static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
840 {
841 int retval;
842 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
843
844 if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
845 {
846 return retval;
847 }
848 if (target->state != TARGET_HALTED)
849 {
850 if ((retval = target_halt(target)) != ERROR_OK)
851 return retval;
852 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
853 {
854 return retval;
855 }
856 return ERROR_TARGET_TIMEOUT;
857 }
858
859 /* fast exit: ARMv5+ code can use BKPT */
860 if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
861 0, 32) != exit_point)
862 {
863 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
864 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
865 return ERROR_TARGET_TIMEOUT;
866 }
867
868 return ERROR_OK;
869 }
870
871 int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
872 {
873 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
874 struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
875 enum armv4_5_state core_state = armv4_5->core_state;
876 uint32_t context[17];
877 uint32_t cpsr;
878 int exit_breakpoint_size = 0;
879 int i;
880 int retval = ERROR_OK;
881 LOG_DEBUG("Running algorithm");
882
883 if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
884 {
885 LOG_ERROR("current target isn't an ARMV4/5 target");
886 return ERROR_TARGET_INVALID;
887 }
888
889 if (target->state != TARGET_HALTED)
890 {
891 LOG_WARNING("target not halted");
892 return ERROR_TARGET_NOT_HALTED;
893 }
894
895 if (!is_arm_mode(armv4_5->core_mode))
896 return ERROR_FAIL;
897
898 /* armv5 and later can terminate with BKPT instruction; less overhead */
899 if (!exit_point && armv4_5->is_armv4)
900 {
901 LOG_ERROR("ARMv4 target needs HW breakpoint location");
902 return ERROR_FAIL;
903 }
904
905 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
906 * they'll be restored later.
907 */
908 for (i = 0; i <= 16; i++)
909 {
910 struct reg *r;
911
912 r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
913 armv4_5_algorithm_info->core_mode, i);
914 if (!r->valid)
915 armv4_5->read_core_reg(target, r, i,
916 armv4_5_algorithm_info->core_mode);
917 context[i] = buf_get_u32(r->value, 0, 32);
918 }
919 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
920
921 for (i = 0; i < num_mem_params; i++)
922 {
923 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
924 {
925 return retval;
926 }
927 }
928
929 for (i = 0; i < num_reg_params; i++)
930 {
931 struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
932 if (!reg)
933 {
934 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
935 return ERROR_INVALID_ARGUMENTS;
936 }
937
938 if (reg->size != reg_params[i].size)
939 {
940 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
941 return ERROR_INVALID_ARGUMENTS;
942 }
943
944 if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
945 {
946 return retval;
947 }
948 }
949
950 armv4_5->core_state = armv4_5_algorithm_info->core_state;
951 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
952 exit_breakpoint_size = 4;
953 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
954 exit_breakpoint_size = 2;
955 else
956 {
957 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
958 return ERROR_INVALID_ARGUMENTS;
959 }
960
961 if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
962 {
963 LOG_DEBUG("setting core_mode: 0x%2.2x",
964 armv4_5_algorithm_info->core_mode);
965 buf_set_u32(armv4_5->cpsr->value, 0, 5,
966 armv4_5_algorithm_info->core_mode);
967 armv4_5->cpsr->dirty = 1;
968 armv4_5->cpsr->valid = 1;
969 }
970
971 /* terminate using a hardware or (ARMv5+) software breakpoint */
972 if (exit_point && (retval = breakpoint_add(target, exit_point,
973 exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
974 {
975 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
976 return ERROR_TARGET_FAILURE;
977 }
978
979 if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
980 {
981 return retval;
982 }
983 int retvaltemp;
984 retval = run_it(target, exit_point, timeout_ms, arch_info);
985
986 if (exit_point)
987 breakpoint_remove(target, exit_point);
988
989 if (retval != ERROR_OK)
990 return retval;
991
992 for (i = 0; i < num_mem_params; i++)
993 {
994 if (mem_params[i].direction != PARAM_OUT)
995 if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
996 {
997 retval = retvaltemp;
998 }
999 }
1000
1001 for (i = 0; i < num_reg_params; i++)
1002 {
1003 if (reg_params[i].direction != PARAM_OUT)
1004 {
1005
1006 struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
1007 if (!reg)
1008 {
1009 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1010 retval = ERROR_INVALID_ARGUMENTS;
1011 continue;
1012 }
1013
1014 if (reg->size != reg_params[i].size)
1015 {
1016 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1017 retval = ERROR_INVALID_ARGUMENTS;
1018 continue;
1019 }
1020
1021 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1022 }
1023 }
1024
1025 /* restore everything we saved before (17 or 18 registers) */
1026 for (i = 0; i <= 16; i++)
1027 {
1028 uint32_t regvalue;
1029 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
1030 if (regvalue != context[i])
1031 {
1032 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
1033 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1034 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
1035 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
1036 }
1037 }
1038
1039 arm_set_cpsr(armv4_5, cpsr);
1040 armv4_5->cpsr->dirty = 1;
1041
1042 armv4_5->core_state = core_state;
1043
1044 return retval;
1045 }
1046
1047 int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
1048 {
1049 return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
1050 }
1051
1052 /**
1053 * Runs ARM code in the target to calculate a CRC32 checksum.
1054 *
1055 * \todo On ARMv5+, rely on BKPT termination for reduced overhead.
1056 */
1057 int arm_checksum_memory(struct target *target,
1058 uint32_t address, uint32_t count, uint32_t *checksum)
1059 {
1060 struct working_area *crc_algorithm;
1061 struct armv4_5_algorithm armv4_5_info;
1062 struct reg_param reg_params[2];
1063 int retval;
1064 uint32_t i;
1065
1066 static const uint32_t arm_crc_code[] = {
1067 0xE1A02000, /* mov r2, r0 */
1068 0xE3E00000, /* mov r0, #0xffffffff */
1069 0xE1A03001, /* mov r3, r1 */
1070 0xE3A04000, /* mov r4, #0 */
1071 0xEA00000B, /* b ncomp */
1072 /* nbyte: */
1073 0xE7D21004, /* ldrb r1, [r2, r4] */
1074 0xE59F7030, /* ldr r7, CRC32XOR */
1075 0xE0200C01, /* eor r0, r0, r1, asl 24 */
1076 0xE3A05000, /* mov r5, #0 */
1077 /* loop: */
1078 0xE3500000, /* cmp r0, #0 */
1079 0xE1A06080, /* mov r6, r0, asl #1 */
1080 0xE2855001, /* add r5, r5, #1 */
1081 0xE1A00006, /* mov r0, r6 */
1082 0xB0260007, /* eorlt r0, r6, r7 */
1083 0xE3550008, /* cmp r5, #8 */
1084 0x1AFFFFF8, /* bne loop */
1085 0xE2844001, /* add r4, r4, #1 */
1086 /* ncomp: */
1087 0xE1540003, /* cmp r4, r3 */
1088 0x1AFFFFF1, /* bne nbyte */
1089 /* end: */
1090 0xEAFFFFFE, /* b end */
1091 /* CRC32XOR: */
1092 0x04C11DB7 /* .word 0x04C11DB7 */
1093 };
1094
1095 retval = target_alloc_working_area(target,
1096 sizeof(arm_crc_code), &crc_algorithm);
1097 if (retval != ERROR_OK)
1098 return retval;
1099
1100 /* convert code into a buffer in target endianness */
1101 for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
1102 retval = target_write_u32(target,
1103 crc_algorithm->address + i * sizeof(uint32_t),
1104 arm_crc_code[i]);
1105 if (retval != ERROR_OK)
1106 return retval;
1107 }
1108
1109 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1110 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1111 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1112
1113 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
1114 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1115
1116 buf_set_u32(reg_params[0].value, 0, 32, address);
1117 buf_set_u32(reg_params[1].value, 0, 32, count);
1118
1119 /* 20 second timeout/megabyte */
1120 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1121
1122 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1123 crc_algorithm->address,
1124 crc_algorithm->address + sizeof(arm_crc_code) - 8,
1125 timeout, &armv4_5_info);
1126 if (retval != ERROR_OK) {
1127 LOG_ERROR("error executing ARM crc algorithm");
1128 destroy_reg_param(&reg_params[0]);
1129 destroy_reg_param(&reg_params[1]);
1130 target_free_working_area(target, crc_algorithm);
1131 return retval;
1132 }
1133
1134 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1135
1136 destroy_reg_param(&reg_params[0]);
1137 destroy_reg_param(&reg_params[1]);
1138
1139 target_free_working_area(target, crc_algorithm);
1140
1141 return ERROR_OK;
1142 }
1143
1144 /**
1145 * Runs ARM code in the target to check whether a memory block holds
1146 * all ones. NOR flash which has been erased, and thus may be written,
1147 * holds all ones.
1148 *
1149 * \todo On ARMv5+, rely on BKPT termination for reduced overhead.
1150 */
1151 int arm_blank_check_memory(struct target *target,
1152 uint32_t address, uint32_t count, uint32_t *blank)
1153 {
1154 struct working_area *check_algorithm;
1155 struct reg_param reg_params[3];
1156 struct armv4_5_algorithm armv4_5_info;
1157 int retval;
1158 uint32_t i;
1159
1160 static const uint32_t check_code[] = {
1161 /* loop: */
1162 0xe4d03001, /* ldrb r3, [r0], #1 */
1163 0xe0022003, /* and r2, r2, r3 */
1164 0xe2511001, /* subs r1, r1, #1 */
1165 0x1afffffb, /* bne loop */
1166 /* end: */
1167 0xeafffffe /* b end */
1168 };
1169
1170 /* make sure we have a working area */
1171 retval = target_alloc_working_area(target,
1172 sizeof(check_code), &check_algorithm);
1173 if (retval != ERROR_OK)
1174 return retval;
1175
1176 /* convert code into a buffer in target endianness */
1177 for (i = 0; i < ARRAY_SIZE(check_code); i++) {
1178 retval = target_write_u32(target,
1179 check_algorithm->address
1180 + i * sizeof(uint32_t),
1181 check_code[i]);
1182 if (retval != ERROR_OK)
1183 return retval;
1184 }
1185
1186 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1187 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1188 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1189
1190 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1191 buf_set_u32(reg_params[0].value, 0, 32, address);
1192
1193 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1194 buf_set_u32(reg_params[1].value, 0, 32, count);
1195
1196 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1197 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
1198
1199 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1200 check_algorithm->address,
1201 check_algorithm->address + sizeof(check_code) - 4,
1202 10000, &armv4_5_info);
1203 if (retval != ERROR_OK) {
1204 destroy_reg_param(&reg_params[0]);
1205 destroy_reg_param(&reg_params[1]);
1206 destroy_reg_param(&reg_params[2]);
1207 target_free_working_area(target, check_algorithm);
1208 return retval;
1209 }
1210
1211 *blank = buf_get_u32(reg_params[2].value, 0, 32);
1212
1213 destroy_reg_param(&reg_params[0]);
1214 destroy_reg_param(&reg_params[1]);
1215 destroy_reg_param(&reg_params[2]);
1216
1217 target_free_working_area(target, check_algorithm);
1218
1219 return ERROR_OK;
1220 }
1221
1222 static int arm_full_context(struct target *target)
1223 {
1224 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
1225 unsigned num_regs = armv4_5->core_cache->num_regs;
1226 struct reg *reg = armv4_5->core_cache->reg_list;
1227 int retval = ERROR_OK;
1228
1229 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1230 if (reg->valid)
1231 continue;
1232 retval = armv4_5_get_core_reg(reg);
1233 }
1234 return retval;
1235 }
1236
1237 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
1238 {
1239 target->arch_info = armv4_5;
1240
1241 armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
1242 arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR);
1243 armv4_5->core_state = ARMV4_5_STATE_ARM;
1244
1245 /* core_type may be overridden by subtype logic */
1246 armv4_5->core_type = ARMV4_5_MODE_ANY;
1247
1248 /* default full_context() has no core-specific optimizations */
1249 if (!armv4_5->full_context && armv4_5->read_core_reg)
1250 armv4_5->full_context = arm_full_context;
1251
1252 return ERROR_OK;
1253 }
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