02105e5f3eee34df362f1884352001813b0e8cb2
[openocd.git] / src / target / armv4_5.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "armv4_5.h"
31 #include "arm_disassembler.h"
32 #include "binarybuffer.h"
33
34
35 struct bitfield_desc armv4_5_psr_bitfield_desc[] =
36 {
37 {"M[4:0]", 5},
38 {"T", 1},
39 {"F", 1},
40 {"I", 1},
41 {"reserved", 16},
42 {"J", 1},
43 {"reserved", 2},
44 {"Q", 1},
45 {"V", 1},
46 {"C", 1},
47 {"Z", 1},
48 {"N", 1},
49 };
50
51 char* armv4_5_core_reg_list[] =
52 {
53 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
54
55 "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
56
57 "r13_irq", "lr_irq",
58
59 "r13_svc", "lr_svc",
60
61 "r13_abt", "lr_abt",
62
63 "r13_und", "lr_und",
64
65 "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
66 };
67
68 char * armv4_5_mode_strings_list[] =
69 {
70 "Illegal mode value", "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System"
71 };
72
73 /* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */
74 char** armv4_5_mode_strings = armv4_5_mode_strings_list + 1;
75
76 char* armv4_5_state_strings[] =
77 {
78 "ARM", "Thumb", "Jazelle"
79 };
80
81 int armv4_5_core_reg_arch_type = -1;
82
83 struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
84 {
85 {0, ARMV4_5_MODE_ANY, NULL, NULL},
86 {1, ARMV4_5_MODE_ANY, NULL, NULL},
87 {2, ARMV4_5_MODE_ANY, NULL, NULL},
88 {3, ARMV4_5_MODE_ANY, NULL, NULL},
89 {4, ARMV4_5_MODE_ANY, NULL, NULL},
90 {5, ARMV4_5_MODE_ANY, NULL, NULL},
91 {6, ARMV4_5_MODE_ANY, NULL, NULL},
92 {7, ARMV4_5_MODE_ANY, NULL, NULL},
93 {8, ARMV4_5_MODE_ANY, NULL, NULL},
94 {9, ARMV4_5_MODE_ANY, NULL, NULL},
95 {10, ARMV4_5_MODE_ANY, NULL, NULL},
96 {11, ARMV4_5_MODE_ANY, NULL, NULL},
97 {12, ARMV4_5_MODE_ANY, NULL, NULL},
98 {13, ARMV4_5_MODE_USR, NULL, NULL},
99 {14, ARMV4_5_MODE_USR, NULL, NULL},
100 {15, ARMV4_5_MODE_ANY, NULL, NULL},
101
102 {8, ARMV4_5_MODE_FIQ, NULL, NULL},
103 {9, ARMV4_5_MODE_FIQ, NULL, NULL},
104 {10, ARMV4_5_MODE_FIQ, NULL, NULL},
105 {11, ARMV4_5_MODE_FIQ, NULL, NULL},
106 {12, ARMV4_5_MODE_FIQ, NULL, NULL},
107 {13, ARMV4_5_MODE_FIQ, NULL, NULL},
108 {14, ARMV4_5_MODE_FIQ, NULL, NULL},
109
110 {13, ARMV4_5_MODE_IRQ, NULL, NULL},
111 {14, ARMV4_5_MODE_IRQ, NULL, NULL},
112
113 {13, ARMV4_5_MODE_SVC, NULL, NULL},
114 {14, ARMV4_5_MODE_SVC, NULL, NULL},
115
116 {13, ARMV4_5_MODE_ABT, NULL, NULL},
117 {14, ARMV4_5_MODE_ABT, NULL, NULL},
118
119 {13, ARMV4_5_MODE_UND, NULL, NULL},
120 {14, ARMV4_5_MODE_UND, NULL, NULL},
121
122 {16, ARMV4_5_MODE_ANY, NULL, NULL},
123 {16, ARMV4_5_MODE_FIQ, NULL, NULL},
124 {16, ARMV4_5_MODE_IRQ, NULL, NULL},
125 {16, ARMV4_5_MODE_SVC, NULL, NULL},
126 {16, ARMV4_5_MODE_ABT, NULL, NULL},
127 {16, ARMV4_5_MODE_UND, NULL, NULL}
128 };
129
130 /* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
131 int armv4_5_core_reg_map[7][17] =
132 {
133 { /* USR */
134 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
135 },
136 { /* FIQ */
137 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
138 },
139 { /* IRQ */
140 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
141 },
142 { /* SVC */
143 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
144 },
145 { /* ABT */
146 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
147 },
148 { /* UND */
149 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
150 },
151 { /* SYS */
152 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
153 }
154 };
155
156 uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
157
158 struct reg armv4_5_gdb_dummy_fp_reg =
159 {
160 "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
161 };
162
163 uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
164
165 struct reg armv4_5_gdb_dummy_fps_reg =
166 {
167 "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
168 };
169
170 int armv4_5_get_core_reg(struct reg *reg)
171 {
172 int retval;
173 struct armv4_5_core_reg *armv4_5 = reg->arch_info;
174 target_t *target = armv4_5->target;
175
176 if (target->state != TARGET_HALTED)
177 {
178 LOG_ERROR("Target not halted");
179 return ERROR_TARGET_NOT_HALTED;
180 }
181
182 /* retval = armv4_5->armv4_5_common->full_context(target); */
183 retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
184
185 return retval;
186 }
187
188 int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
189 {
190 struct armv4_5_core_reg *armv4_5 = reg->arch_info;
191 target_t *target = armv4_5->target;
192 struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
193 uint32_t value = buf_get_u32(buf, 0, 32);
194
195 if (target->state != TARGET_HALTED)
196 {
197 return ERROR_TARGET_NOT_HALTED;
198 }
199
200 if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
201 {
202 if (value & 0x20)
203 {
204 /* T bit should be set */
205 if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
206 {
207 /* change state to Thumb */
208 LOG_DEBUG("changing to Thumb state");
209 armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
210 }
211 }
212 else
213 {
214 /* T bit should be cleared */
215 if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
216 {
217 /* change state to ARM */
218 LOG_DEBUG("changing to ARM state");
219 armv4_5_target->core_state = ARMV4_5_STATE_ARM;
220 }
221 }
222
223 if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
224 {
225 LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
226 armv4_5_target->core_mode = value & 0x1f;
227 armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
228 }
229 }
230
231 buf_set_u32(reg->value, 0, 32, value);
232 reg->dirty = 1;
233 reg->valid = 1;
234
235 return ERROR_OK;
236 }
237
238 int armv4_5_invalidate_core_regs(target_t *target)
239 {
240 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
241 int i;
242
243 for (i = 0; i < 37; i++)
244 {
245 armv4_5->core_cache->reg_list[i].valid = 0;
246 armv4_5->core_cache->reg_list[i].dirty = 0;
247 }
248
249 return ERROR_OK;
250 }
251
252 struct reg_cache* armv4_5_build_reg_cache(target_t *target, struct arm *armv4_5_common)
253 {
254 int num_regs = 37;
255 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
256 struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
257 struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
258 int i;
259
260 cache->name = "arm v4/5 registers";
261 cache->next = NULL;
262 cache->reg_list = reg_list;
263 cache->num_regs = num_regs;
264
265 if (armv4_5_core_reg_arch_type == -1)
266 armv4_5_core_reg_arch_type = register_reg_arch_type(armv4_5_get_core_reg, armv4_5_set_core_reg);
267
268 register_init_dummy(&armv4_5_gdb_dummy_fp_reg);
269 register_init_dummy(&armv4_5_gdb_dummy_fps_reg);
270
271 for (i = 0; i < 37; i++)
272 {
273 arch_info[i] = armv4_5_core_reg_list_arch_info[i];
274 arch_info[i].target = target;
275 arch_info[i].armv4_5_common = armv4_5_common;
276 reg_list[i].name = armv4_5_core_reg_list[i];
277 reg_list[i].size = 32;
278 reg_list[i].value = calloc(1, 4);
279 reg_list[i].dirty = 0;
280 reg_list[i].valid = 0;
281 reg_list[i].bitfield_desc = NULL;
282 reg_list[i].num_bitfields = 0;
283 reg_list[i].arch_type = armv4_5_core_reg_arch_type;
284 reg_list[i].arch_info = &arch_info[i];
285 }
286
287 return cache;
288 }
289
290 int armv4_5_arch_state(struct target_s *target)
291 {
292 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
293
294 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
295 {
296 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
297 exit(-1);
298 }
299
300 LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
301 armv4_5_state_strings[armv4_5->core_state],
302 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
303 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
304 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
305 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
306
307 return ERROR_OK;
308 }
309
310 COMMAND_HANDLER(handle_armv4_5_reg_command)
311 {
312 char output[128];
313 int output_len;
314 int mode, num;
315 target_t *target = get_current_target(cmd_ctx);
316 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
317
318 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
319 {
320 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
321 return ERROR_OK;
322 }
323
324 if (target->state != TARGET_HALTED)
325 {
326 command_print(cmd_ctx, "error: target must be halted for register accesses");
327 return ERROR_OK;
328 }
329
330 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
331 return ERROR_FAIL;
332
333 for (num = 0; num <= 15; num++)
334 {
335 output_len = 0;
336 for (mode = 0; mode < 6; mode++)
337 {
338 if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
339 {
340 armv4_5->full_context(target);
341 }
342 output_len += snprintf(output + output_len,
343 128 - output_len,
344 "%8s: %8.8" PRIx32 " ",
345 ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
346 buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
347 }
348 command_print(cmd_ctx, "%s", output);
349 }
350 command_print(cmd_ctx,
351 " cpsr: %8.8" PRIx32 " spsr_fiq: %8.8" PRIx32 " spsr_irq: %8.8" PRIx32 " spsr_svc: %8.8" PRIx32 " spsr_abt: %8.8" PRIx32 " spsr_und: %8.8" PRIx32 "",
352 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
353 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
354 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
355 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
356 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
357 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
358
359 return ERROR_OK;
360 }
361
362 COMMAND_HANDLER(handle_armv4_5_core_state_command)
363 {
364 target_t *target = get_current_target(cmd_ctx);
365 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
366
367 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
368 {
369 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
370 return ERROR_OK;
371 }
372
373 if (argc > 0)
374 {
375 if (strcmp(args[0], "arm") == 0)
376 {
377 armv4_5->core_state = ARMV4_5_STATE_ARM;
378 }
379 if (strcmp(args[0], "thumb") == 0)
380 {
381 armv4_5->core_state = ARMV4_5_STATE_THUMB;
382 }
383 }
384
385 command_print(cmd_ctx, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
386
387 return ERROR_OK;
388 }
389
390 COMMAND_HANDLER(handle_armv4_5_disassemble_command)
391 {
392 int retval = ERROR_OK;
393 target_t *target = get_current_target(cmd_ctx);
394 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
395 uint32_t address;
396 int count = 1;
397 int i;
398 struct arm_instruction cur_instruction;
399 uint32_t opcode;
400 uint16_t thumb_opcode;
401 int thumb = 0;
402
403 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
404 {
405 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
406 return ERROR_OK;
407 }
408
409 switch (argc) {
410 case 3:
411 if (strcmp(args[2], "thumb") != 0)
412 goto usage;
413 thumb = 1;
414 /* FALL THROUGH */
415 case 2:
416 COMMAND_PARSE_NUMBER(int, args[1], count);
417 /* FALL THROUGH */
418 case 1:
419 COMMAND_PARSE_NUMBER(u32, args[0], address);
420 if (address & 0x01) {
421 if (!thumb) {
422 command_print(cmd_ctx, "Disassemble as Thumb");
423 thumb = 1;
424 }
425 address &= ~1;
426 }
427 break;
428 default:
429 usage:
430 command_print(cmd_ctx,
431 "usage: armv4_5 disassemble <address> [<count> ['thumb']]");
432 return ERROR_OK;
433 }
434
435 for (i = 0; i < count; i++)
436 {
437 if (thumb)
438 {
439 if ((retval = target_read_u16(target, address, &thumb_opcode)) != ERROR_OK)
440 {
441 return retval;
442 }
443 if ((retval = thumb_evaluate_opcode(thumb_opcode, address, &cur_instruction)) != ERROR_OK)
444 {
445 return retval;
446 }
447 }
448 else {
449 if ((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
450 {
451 return retval;
452 }
453 if ((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
454 {
455 return retval;
456 }
457 }
458 command_print(cmd_ctx, "%s", cur_instruction.text);
459 address += (thumb) ? 2 : 4;
460 }
461
462 return ERROR_OK;
463 }
464
465 int armv4_5_register_commands(struct command_context_s *cmd_ctx)
466 {
467 command_t *armv4_5_cmd;
468
469 armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5",
470 NULL, COMMAND_ANY,
471 "armv4/5 specific commands");
472
473 register_command(cmd_ctx, armv4_5_cmd, "reg",
474 handle_armv4_5_reg_command, COMMAND_EXEC,
475 "display ARM core registers");
476 register_command(cmd_ctx, armv4_5_cmd, "core_state",
477 handle_armv4_5_core_state_command, COMMAND_EXEC,
478 "display/change ARM core state <arm | thumb>");
479 register_command(cmd_ctx, armv4_5_cmd, "disassemble",
480 handle_armv4_5_disassemble_command, COMMAND_EXEC,
481 "disassemble instructions <address> [<count> ['thumb']]");
482
483 return ERROR_OK;
484 }
485
486 int armv4_5_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
487 {
488 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
489 int i;
490
491 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
492 return ERROR_FAIL;
493
494 *reg_list_size = 26;
495 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
496
497 for (i = 0; i < 16; i++)
498 {
499 (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
500 }
501
502 for (i = 16; i < 24; i++)
503 {
504 (*reg_list)[i] = &armv4_5_gdb_dummy_fp_reg;
505 }
506
507 (*reg_list)[24] = &armv4_5_gdb_dummy_fps_reg;
508 (*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
509
510 return ERROR_OK;
511 }
512
513 /* wait for execution to complete and check exit point */
514 static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
515 {
516 int retval;
517 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
518
519 if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
520 {
521 return retval;
522 }
523 if (target->state != TARGET_HALTED)
524 {
525 if ((retval = target_halt(target)) != ERROR_OK)
526 return retval;
527 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
528 {
529 return retval;
530 }
531 return ERROR_TARGET_TIMEOUT;
532 }
533
534 /* fast exit: ARMv5+ code can use BKPT */
535 if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
536 0, 32) != exit_point)
537 {
538 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
539 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
540 return ERROR_TARGET_TIMEOUT;
541 }
542
543 return ERROR_OK;
544 }
545
546 int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info))
547 {
548 struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
549 struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
550 enum armv4_5_state core_state = armv4_5->core_state;
551 enum armv4_5_mode core_mode = armv4_5->core_mode;
552 uint32_t context[17];
553 uint32_t cpsr;
554 int exit_breakpoint_size = 0;
555 int i;
556 int retval = ERROR_OK;
557 LOG_DEBUG("Running algorithm");
558
559 if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
560 {
561 LOG_ERROR("current target isn't an ARMV4/5 target");
562 return ERROR_TARGET_INVALID;
563 }
564
565 if (target->state != TARGET_HALTED)
566 {
567 LOG_WARNING("target not halted");
568 return ERROR_TARGET_NOT_HALTED;
569 }
570
571 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
572 return ERROR_FAIL;
573
574 /* armv5 and later can terminate with BKPT instruction; less overhead */
575 if (!exit_point && armv4_5->is_armv4)
576 {
577 LOG_ERROR("ARMv4 target needs HW breakpoint location");
578 return ERROR_FAIL;
579 }
580
581 for (i = 0; i <= 16; i++)
582 {
583 if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
584 armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
585 context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
586 }
587 cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
588
589 for (i = 0; i < num_mem_params; i++)
590 {
591 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
592 {
593 return retval;
594 }
595 }
596
597 for (i = 0; i < num_reg_params; i++)
598 {
599 struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
600 if (!reg)
601 {
602 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
603 exit(-1);
604 }
605
606 if (reg->size != reg_params[i].size)
607 {
608 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
609 exit(-1);
610 }
611
612 if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
613 {
614 return retval;
615 }
616 }
617
618 armv4_5->core_state = armv4_5_algorithm_info->core_state;
619 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
620 exit_breakpoint_size = 4;
621 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
622 exit_breakpoint_size = 2;
623 else
624 {
625 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
626 exit(-1);
627 }
628
629 if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
630 {
631 LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
632 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
633 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
634 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
635 }
636
637 /* terminate using a hardware or (ARMv5+) software breakpoint */
638 if (exit_point && (retval = breakpoint_add(target, exit_point,
639 exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
640 {
641 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
642 return ERROR_TARGET_FAILURE;
643 }
644
645 if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
646 {
647 return retval;
648 }
649 int retvaltemp;
650 retval = run_it(target, exit_point, timeout_ms, arch_info);
651
652 if (exit_point)
653 breakpoint_remove(target, exit_point);
654
655 if (retval != ERROR_OK)
656 return retval;
657
658 for (i = 0; i < num_mem_params; i++)
659 {
660 if (mem_params[i].direction != PARAM_OUT)
661 if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
662 {
663 retval = retvaltemp;
664 }
665 }
666
667 for (i = 0; i < num_reg_params; i++)
668 {
669 if (reg_params[i].direction != PARAM_OUT)
670 {
671
672 struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
673 if (!reg)
674 {
675 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
676 exit(-1);
677 }
678
679 if (reg->size != reg_params[i].size)
680 {
681 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
682 exit(-1);
683 }
684
685 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
686 }
687 }
688
689 for (i = 0; i <= 16; i++)
690 {
691 uint32_t regvalue;
692 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
693 if (regvalue != context[i])
694 {
695 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
696 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
697 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
698 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
699 }
700 }
701 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
702 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
703 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
704
705 armv4_5->core_state = core_state;
706 armv4_5->core_mode = core_mode;
707
708 return retval;
709 }
710
711 int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
712 {
713 return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
714 }
715
716 int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5)
717 {
718 target->arch_info = armv4_5;
719
720 armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
721 armv4_5->core_state = ARMV4_5_STATE_ARM;
722 armv4_5->core_mode = ARMV4_5_MODE_USR;
723
724 return ERROR_OK;
725 }