src/target/arm_opcodes.h

   1 /*
   2  * Copyright (C) 2005 by Dominic Rath
   3  * Dominic.Rath@gmx.de
   4  *
   5  * Copyright (C) 2008 by Spencer Oliver
   6  * spen@spen-soft.co.uk
   7  *
   8  * Copyright (C) 2009 by Øyvind Harboe
   9  * oyvind.harboe@zylin.com
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the
  23  * Free Software Foundation, Inc.,
  24  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  25  */
  26 #ifndef __ARM_OPCODES_H
  27 #define __ARM_OPCODES_H
  28
  29 /**
  30  * @file
  31  * Macros used to generate various ARM or Thumb opcodes.
  32  */
  33
  34 /* ARM mode instructions */
  35
  36 /* Store multiple increment after
  37  * Rn: base register
  38  * List: for each bit in list: store register
  39  * S: in priviledged mode: store user-mode registers
  40  * W = 1: update the base register. W = 0: leave the base register untouched
  41  */
  42 #define ARMV4_5_STMIA(Rn, List, S, W) \
  43         (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
  44
  45 /* Load multiple increment after
  46  * Rn: base register
  47  * List: for each bit in list: store register
  48  * S: in priviledged mode: store user-mode registers
  49  * W = 1: update the base register. W = 0: leave the base register untouched
  50  */
  51 #define ARMV4_5_LDMIA(Rn, List, S, W) \
  52         (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
  53
  54 /* MOV r8, r8 */
  55 #define ARMV4_5_NOP                                     (0xe1a08008)
  56
  57 /* Move PSR to general purpose register
  58  * R = 1: SPSR R = 0: CPSR
  59  * Rn: target register
  60  */
  61 #define ARMV4_5_MRS(Rn, R)      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
  62
  63 /* Store register
  64  * Rd: register to store
  65  * Rn: base register
  66  */
  67 #define ARMV4_5_STR(Rd, Rn)     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
  68
  69 /* Load register
  70  * Rd: register to load
  71  * Rn: base register
  72  */
  73 #define ARMV4_5_LDR(Rd, Rn)     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
  74
  75 /* Move general purpose register to PSR
  76  * R = 1: SPSR R = 0: CPSR
  77  * Field: Field mask
  78  * 1: control field 2: extension field 4: status field 8: flags field
  79  * Rm: source register
  80  */
  81 #define ARMV4_5_MSR_GP(Rm, Field, R) \
  82         (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
  83 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
  84         (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
  85
  86 /* Load Register Halfword Immediate Post-Index
  87  * Rd: register to load
  88  * Rn: base register
  89  */
  90 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
  91
  92 /* Load Register Byte Immediate Post-Index
  93  * Rd: register to load
  94  * Rn: base register
  95  */
  96 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
  97
  98 /* Store register Halfword Immediate Post-Index
  99  * Rd: register to store
 100  * Rn: base register
 101  */
 102 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 103
 104 /* Store register Byte Immediate Post-Index
 105  * Rd: register to store
 106  * Rn: base register
 107  */
 108 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 109
 110 /* Branch (and Link)
 111  * Im: Branch target (left-shifted by 2 bits, added to PC)
 112  * L: 1: branch and link 0: branch only
 113  */
 114 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 115
 116 /* Branch and exchange (ARM state)
 117  * Rm: register holding branch target address
 118  */
 119 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 120
 121 /* Move to ARM register from coprocessor
 122  * CP: Coprocessor number
 123  * op1: Coprocessor opcode
 124  * Rd: destination register
 125  * CRn: first coprocessor operand
 126  * CRm: second coprocessor operand
 127  * op2: Second coprocessor opcode
 128  */
 129 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
 130         (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
 131         | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 132
 133 /* Move to coprocessor from ARM register
 134  * CP: Coprocessor number
 135  * op1: Coprocessor opcode
 136  * Rd: destination register
 137  * CRn: first coprocessor operand
 138  * CRm: second coprocessor operand
 139  * op2: Second coprocessor opcode
 140  */
 141 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
 142         (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
 143         | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 144
 145 /* Breakpoint instruction (ARMv5)
 146  * Im: 16-bit immediate
 147  */
 148 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 149
 150
 151 /* Thumb mode instructions
 152  *
 153  * NOTE: these 16-bit opcodes fill both halves of a word with the same
 154  * value.  The reason for this is that when we need to execute Thumb
 155  * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
 156  * we must shift 32 bits to the bus using scan chain 1 ... if we write
 157  * both halves, we don't need to track which half matters.  On ARMv6 and
 158  * ARMv7 we don't execute Thumb instructions in debug mode; the ITR
 159  * register does not accept Thumb (or Thumb2) opcodes.
 160  */
 161
 162 /* Store register (Thumb mode)
 163  * Rd: source register
 164  * Rn: base register
 165  */
 166 #define ARMV4_5_T_STR(Rd, Rn) \
 167         ((0x6000 | (Rd) | ((Rn) << 3)) | \
 168         ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 169
 170 /* Load register (Thumb state)
 171  * Rd: destination register
 172  * Rn: base register
 173  */
 174 #define ARMV4_5_T_LDR(Rd, Rn) \
 175         ((0x6800 | ((Rn) << 3) | (Rd)) \
 176         | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 177
 178 /* Load multiple (Thumb state)
 179  * Rn: base register
 180  * List: for each bit in list: store register
 181  */
 182 #define ARMV4_5_T_LDMIA(Rn, List) \
 183         ((0xc800 | ((Rn) << 8) | (List)) \
 184         | ((0xc800 | ((Rn) << 8) | (List)) << 16))
 185
 186 /* Load register with PC relative addressing
 187  * Rd: register to load
 188  */
 189 #define ARMV4_5_T_LDR_PCREL(Rd) \
 190         ((0x4800 | ((Rd) << 8)) \
 191         | ((0x4800 | ((Rd) << 8)) << 16))
 192
 193 /* Move hi register (Thumb mode)
 194  * Rd: destination register
 195  * Rm: source register
 196  */
 197 #define ARMV4_5_T_MOV(Rd, Rm) \
 198         ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
 199                 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
 200         | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
 201                 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 202
 203 /* No operation (Thumb mode)
 204  * NOTE:  this is "MOV r8, r8" ... Thumb2 adds two
 205  * architected NOPs, 16-bit and 32-bit.
 206  */
 207 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 208
 209 /* Move immediate to register (Thumb state)
 210  * Rd: destination register
 211  * Im: 8-bit immediate value
 212  */
 213 #define ARMV4_5_T_MOV_IM(Rd, Im) \
 214         ((0x2000 | ((Rd) << 8) | (Im)) \
 215         | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 216
 217 /* Branch and Exchange
 218  * Rm: register containing branch target
 219  */
 220 #define ARMV4_5_T_BX(Rm) \
 221         ((0x4700 | ((Rm) << 3)) \
 222         | ((0x4700 | ((Rm) << 3)) << 16))
 223
 224 /* Branch (Thumb state)
 225  * Imm: Branch target
 226  */
 227 #define ARMV4_5_T_B(Imm) \
 228         ((0xe000 | (Imm)) \
 229         | ((0xe000 | (Imm)) << 16))
 230
 231 /* Breakpoint instruction (ARMv5) (Thumb state)
 232  * Im: 8-bit immediate
 233  */
 234 #define ARMV5_T_BKPT(Im) \
 235         ((0xbe00 | (Im)) \
 236         | ((0xbe00 | (Im)) << 16))
 237
 238 /* Move to Register from Special Register
 239  *      32 bit Thumb2 instruction
 240  * Rd: destination register
 241  * SYSm: source special register
 242  */
 243 #define ARM_T2_MRS(Rd, SYSm) \
 244         ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
 245
 246 /* Move from Register from Special Register
 247  *      32 bit Thumb2 instruction
 248  * Rd: source register
 249  * SYSm: destination special register
 250  */
 251 #define ARM_T2_MSR(SYSm, Rn) \
 252         ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
 253
 254 /* Change Processor State.
 255  *      16 bit Thumb2 instruction
 256  * Rd: source register
 257  * IF: A_FLAG and/or I_FLAG and/or F_FLAG
 258  */
 259 #define A_FLAG 4
 260 #define I_FLAG 2
 261 #define F_FLAG 1
 262 #define ARM_T2_CPSID(IF) \
 263         ((0xB660 | (1 << 8) | ((IF)&0x3)) \
 264         | ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16))
 265 #define ARM_T2_CPSIE(IF) \
 266         ((0xB660 | (0 << 8) | ((IF)&0x3)) \
 267         | ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16))
 268
 269 #endif /* __ARM_OPCODES_H */