src/target/arm_dpm.h

   1 /*
   2  * Copyright (C) 2009 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef OPENOCD_TARGET_ARM_DPM_H
  19 #define OPENOCD_TARGET_ARM_DPM_H
  20
  21 /**
  22  * @file
  23  * This is the interface to the Debug Programmers Model for ARMv6 and
  24  * ARMv7 processors.  ARMv6 processors (such as ARM11xx implementations)
  25  * introduced a model which became part of the ARMv7-AR architecture
  26  * which is most familiar through the Cortex-A series parts.  While
  27  * specific details differ (like how to write the instruction register),
  28  * the high level models easily support shared code because those
  29  * registers are compatible.
  30  */
  31
  32 struct dpm_bpwp {
  33         unsigned number;
  34         uint32_t address;
  35         uint32_t control;
  36         /* true if hardware state needs flushing */
  37         bool dirty;
  38 };
  39
  40 struct dpm_bp {
  41         struct breakpoint *bp;
  42         struct dpm_bpwp bpwp;
  43 };
  44
  45 struct dpm_wp {
  46         struct watchpoint *wp;
  47         struct dpm_bpwp bpwp;
  48 };
  49
  50 /**
  51  * This wraps an implementation of DPM primitives.  Each interface
  52  * provider supplies a structure like this, which is the glue between
  53  * upper level code and the lower level hardware access.
  54  *
  55  * It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
  56  * support for CPU register access.
  57  */
  58 struct arm_dpm {
  59         struct arm *arm;
  60
  61         /** Cache of DIDR */
  62         uint32_t didr;
  63
  64         /** Invoke before a series of instruction operations */
  65         int (*prepare)(struct arm_dpm *);
  66
  67         /** Invoke after a series of instruction operations */
  68         int (*finish)(struct arm_dpm *);
  69
  70         /* WRITE TO CPU */
  71
  72         /** Runs one instruction, writing data to DCC before execution. */
  73         int (*instr_write_data_dcc)(struct arm_dpm *,
  74                         uint32_t opcode, uint32_t data);
  75
  76         /** Runs one instruction, writing data to R0 before execution. */
  77         int (*instr_write_data_r0)(struct arm_dpm *,
  78                         uint32_t opcode, uint32_t data);
  79
  80         /** Optional core-specific operation invoked after CPSR writes. */
  81         int (*instr_cpsr_sync)(struct arm_dpm *dpm);
  82
  83         /* READ FROM CPU */
  84
  85         /** Runs one instruction, reading data from dcc after execution. */
  86         int (*instr_read_data_dcc)(struct arm_dpm *,
  87                         uint32_t opcode, uint32_t *data);
  88
  89         int (*instr_read_data_dcc_64)(struct arm_dpm *,
  90                         uint32_t opcode, uint64_t *data);
  91
  92         /** Runs one instruction, reading data from r0 after execution. */
  93         int (*instr_read_data_r0)(struct arm_dpm *,
  94                         uint32_t opcode, uint32_t *data);
  95
  96         int (*instr_read_data_r0_64)(struct arm_dpm *,
  97                         uint32_t opcode, uint64_t *data);
  98
  99         struct reg *(*arm_reg_current)(struct arm *arm,
 100                         unsigned regnum);
 101
 102         /* BREAKPOINT/WATCHPOINT SUPPORT */
 103
 104         /**
 105          * Enables one breakpoint or watchpoint by writing to the
 106          * hardware registers.  The specified breakpoint/watchpoint
 107          * must currently be disabled.  Indices 0..15 are used for
 108          * breakpoints; indices 16..31 are for watchpoints.
 109          */
 110         int (*bpwp_enable)(struct arm_dpm *, unsigned index_value,
 111                         uint32_t addr, uint32_t control);
 112
 113         /**
 114          * Disables one breakpoint or watchpoint by clearing its
 115          * hardware control registers.  Indices are the same ones
 116          * accepted by bpwp_enable().
 117          */
 118         int (*bpwp_disable)(struct arm_dpm *, unsigned index_value);
 119
 120         /* The breakpoint and watchpoint arrays are private to the
 121          * DPM infrastructure.  There are nbp indices in the dbp
 122          * array.  There are nwp indices in the dwp array.
 123          */
 124
 125         unsigned nbp;
 126         unsigned nwp;
 127         struct dpm_bp *dbp;
 128         struct dpm_wp *dwp;
 129
 130         /** Address of the instruction which triggered a watchpoint. */
 131         uint32_t wp_pc;
 132
 133         /** Recent value of DSCR. */
 134         uint32_t dscr;
 135
 136         /* FIXME -- read/write DCSR methods and symbols */
 137 };
 138
 139 int arm_dpm_setup(struct arm_dpm *dpm);
 140 int arm_dpm_initialize(struct arm_dpm *dpm);
 141
 142 int arm_dpm_read_current_registers(struct arm_dpm *);
 143 int arm_dpm_read_current_registers_64(struct arm_dpm *);
 144 int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
 145
 146
 147 int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
 148
 149 void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
 150
 151 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
 152  * Not all v7 bits are valid in v6.
 153  */
 154 #define DSCR_CORE_HALTED            (0x1 <<  0)
 155 #define DSCR_CORE_RESTARTED         (0x1 <<  1)
 156 #define DSCR_ENTRY_MASK             (0xF <<  2)
 157 #define DSCR_STICKY_ABORT_PRECISE   (0x1 <<  6)
 158 #define DSCR_STICKY_ABORT_IMPRECISE (0x1 <<  7)
 159 #define DSCR_STICKY_UNDEFINED       (0x1 <<  8)
 160 #define DSCR_DBG_NOPWRDWN           (0x1 <<  9) /* v6 only */
 161 #define DSCR_DBG_ACK                (0x1 << 10)
 162 #define DSCR_INT_DIS                (0x1 << 11)
 163 #define DSCR_CP14_USR_COMMS         (0x1 << 12)
 164 #define DSCR_ITR_EN                 (0x1 << 13)
 165 #define DSCR_HALT_DBG_MODE          (0x1 << 14)
 166 #define DSCR_MON_DBG_MODE           (0x1 << 15)
 167 #define DSCR_SEC_PRIV_INVASV_DIS    (0x1 << 16)
 168 #define DSCR_SEC_PRIV_NINVASV_DIS   (0x1 << 17)
 169 #define DSCR_NON_SECURE             (0x1 << 18)
 170 #define DSCR_DSCRD_IMPRECISE_ABORT  (0x1 << 19)
 171 #define DSCR_EXT_DCC_MASK           (0x3 << 20) /* DTR mode */  /* bits 22, 23 are reserved */
 172 #define DSCR_INSTR_COMP             (0x1 << 24)
 173 #define DSCR_PIPE_ADVANCE           (0x1 << 25)
 174 #define DSCR_DTRTX_FULL_LATCHED     (0x1 << 26)
 175 #define DSCR_DTRRX_FULL_LATCHED     (0x1 << 27) /* bit 28 is reserved */
 176 #define DSCR_DTR_TX_FULL            (0x1 << 29)
 177 #define DSCR_DTR_RX_FULL            (0x1 << 30) /* bit 31 is reserved */
 178
 179 #define DSCR_ENTRY(dscr)            (((dscr) >> 2) & 0xf)
 180 #define DSCR_RUN_MODE(dscr)         ((dscr) & (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED))
 181
 182
 183 /* Methods of entry into debug mode */
 184 #define DSCR_ENTRY_HALT_REQ           (0x0 << 2)
 185 #define DSCR_ENTRY_BREAKPOINT         (0x1 << 2)
 186 #define DSCR_ENTRY_IMPRECISE_WATCHPT  (0x2 << 2)
 187 #define DSCR_ENTRY_BKPT_INSTR         (0x3 << 2)
 188 #define DSCR_ENTRY_EXT_DBG_REQ        (0x4 << 2)
 189 #define DSCR_ENTRY_VECT_CATCH         (0x5 << 2)
 190 #define DSCR_ENTRY_D_SIDE_ABORT       (0x6 << 2)  /* v6 only */
 191 #define DSCR_ENTRY_I_SIDE_ABORT       (0x7 << 2)  /* v6 only */
 192 #define DSCR_ENTRY_OS_UNLOCK          (0x8 << 2)
 193 #define DSCR_ENTRY_PRECISE_WATCHPT    (0xA << 2)
 194
 195 /* DTR modes */
 196 #define DSCR_EXT_DCC_NON_BLOCKING     (0x0 << 20)
 197 #define DSCR_EXT_DCC_STALL_MODE       (0x1 << 20)
 198 #define DSCR_EXT_DCC_FAST_MODE        (0x2 << 20)  /* bits 22, 23 are reserved */
 199
 200
 201
 202
 203
 204 /* DRCR (debug run control register) bits */
 205 #define DRCR_HALT                               (1 << 0)
 206 #define DRCR_RESTART                    (1 << 1)
 207 #define DRCR_CLEAR_EXCEPTIONS   (1 << 2)
 208
 209 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
 210
 211 /* PRCR (Device Power-down and Reset Control Register) bits */
 212 #define PRCR_DEBUG_NO_POWER_DOWN         (1 << 0)
 213 #define PRCR_WARM_RESET                  (1 << 1)
 214 #define PRCR_HOLD_NON_DEBUG_RESET        (1 << 2)
 215
 216 /* PRSR (Device Power-down and Reset Status Register) bits */
 217 #define PRSR_POWERUP_STATUS              (1 << 0)
 218 #define PRSR_STICKY_POWERDOWN_STATUS     (1 << 1)
 219 #define PRSR_RESET_STATUS                (1 << 2)
 220 #define PRSR_STICKY_RESET_STATUS         (1 << 3)
 221 #define PRSR_HALTED                      (1 << 4)  /* v7.1 Debug only */
 222 #define PRSR_OSLK                        (1 << 5)  /* v7.1 Debug only */
 223 #define PRSR_DLK                         (1 << 6)  /* v7.1 Debug only */
 224
 225 /* OSLSR (OS Lock Status Register) bits */
 226 #define OSLSR_OSLM0                      (1 << 0)
 227 #define OSLSR_OSLK                       (1 << 1)
 228 #define OSLSR_nTT                        (1 << 2)
 229 #define OSLSR_OSLM1                      (1 << 3)
 230 #define OSLSR_OSLM                       (OSLSR_OSLM0|OSLSR_OSLM1)
 231
 232 #endif /* OPENOCD_TARGET_ARM_DPM_H */