cortex_a : optimize apb read/write access.
[openocd.git] / src / target / arm_dpm.h
1 /*
2 * Copyright (C) 2009 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20 #ifndef __ARM_DPM_H
21 #define __ARM_DPM_H
22
23 /**
24 * @file
25 * This is the interface to the Debug Programmers Model for ARMv6 and
26 * ARMv7 processors. ARMv6 processors (such as ARM11xx implementations)
27 * introduced a model which became part of the ARMv7-AR architecture
28 * which is most familiar through the Cortex-A series parts. While
29 * specific details differ (like how to write the instruction register),
30 * the high level models easily support shared code because those
31 * registers are compatible.
32 */
33
34 struct dpm_bpwp {
35 unsigned number;
36 uint32_t address;
37 uint32_t control;
38 /* true if hardware state needs flushing */
39 bool dirty;
40 };
41
42 struct dpm_bp {
43 struct breakpoint *bp;
44 struct dpm_bpwp bpwp;
45 };
46
47 struct dpm_wp {
48 struct watchpoint *wp;
49 struct dpm_bpwp bpwp;
50 };
51
52 /**
53 * This wraps an implementation of DPM primitives. Each interface
54 * provider supplies a structure like this, which is the glue between
55 * upper level code and the lower level hardware access.
56 *
57 * It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
58 * support for CPU register access.
59 */
60 struct arm_dpm {
61 struct arm *arm;
62
63 /** Cache of DIDR */
64 uint32_t didr;
65
66 /** Invoke before a series of instruction operations */
67 int (*prepare)(struct arm_dpm *);
68
69 /** Invoke after a series of instruction operations */
70 int (*finish)(struct arm_dpm *);
71
72 /* WRITE TO CPU */
73
74 /** Runs one instruction, writing data to DCC before execution. */
75 int (*instr_write_data_dcc)(struct arm_dpm *,
76 uint32_t opcode, uint32_t data);
77
78 /** Runs one instruction, writing data to R0 before execution. */
79 int (*instr_write_data_r0)(struct arm_dpm *,
80 uint32_t opcode, uint32_t data);
81
82 /** Optional core-specific operation invoked after CPSR writes. */
83 int (*instr_cpsr_sync)(struct arm_dpm *dpm);
84
85 /* READ FROM CPU */
86
87 /** Runs one instruction, reading data from dcc after execution. */
88 int (*instr_read_data_dcc)(struct arm_dpm *,
89 uint32_t opcode, uint32_t *data);
90
91 /** Runs one instruction, reading data from r0 after execution. */
92 int (*instr_read_data_r0)(struct arm_dpm *,
93 uint32_t opcode, uint32_t *data);
94
95 /* BREAKPOINT/WATCHPOINT SUPPORT */
96
97 /**
98 * Enables one breakpoint or watchpoint by writing to the
99 * hardware registers. The specified breakpoint/watchpoint
100 * must currently be disabled. Indices 0..15 are used for
101 * breakpoints; indices 16..31 are for watchpoints.
102 */
103 int (*bpwp_enable)(struct arm_dpm *, unsigned index_value,
104 uint32_t addr, uint32_t control);
105
106 /**
107 * Disables one breakpoint or watchpoint by clearing its
108 * hardware control registers. Indices are the same ones
109 * accepted by bpwp_enable().
110 */
111 int (*bpwp_disable)(struct arm_dpm *, unsigned index_value);
112
113 /* The breakpoint and watchpoint arrays are private to the
114 * DPM infrastructure. There are nbp indices in the dbp
115 * array. There are nwp indices in the dwp array.
116 */
117
118 unsigned nbp;
119 unsigned nwp;
120 struct dpm_bp *dbp;
121 struct dpm_wp *dwp;
122
123 /** Address of the instruction which triggered a watchpoint. */
124 uint32_t wp_pc;
125
126 /** Recent value of DSCR. */
127 uint32_t dscr;
128
129 /* FIXME -- read/write DCSR methods and symbols */
130 };
131
132 int arm_dpm_setup(struct arm_dpm *dpm);
133 int arm_dpm_initialize(struct arm_dpm *dpm);
134
135 int arm_dpm_read_current_registers(struct arm_dpm *);
136 int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
137
138
139 int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
140
141 void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
142
143 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
144 * Not all v7 bits are valid in v6.
145 */
146 #define DSCR_CORE_HALTED (0x1 << 0)
147 #define DSCR_CORE_RESTARTED (0x1 << 1)
148 #define DSCR_ENTRY_MASK (0xF << 2)
149 #define DSCR_STICKY_ABORT_PRECISE (0x1 << 6)
150 #define DSCR_STICKY_ABORT_IMPRECISE (0x1 << 7)
151 #define DSCR_STICKY_UNDEFINED (0x1 << 8)
152 #define DSCR_DBG_NOPWRDWN (0x1 << 9) /* v6 only */
153 #define DSCR_DBG_ACK (0x1 << 10)
154 #define DSCR_INT_DIS (0x1 << 11)
155 #define DSCR_CP14_USR_COMMS (0x1 << 12)
156 #define DSCR_ITR_EN (0x1 << 13)
157 #define DSCR_HALT_DBG_MODE (0x1 << 14)
158 #define DSCR_MON_DBG_MODE (0x1 << 15)
159 #define DSCR_SEC_PRIV_INVASV_DIS (0x1 << 16)
160 #define DSCR_SEC_PRIV_NINVASV_DIS (0x1 << 17)
161 #define DSCR_NON_SECURE (0x1 << 18)
162 #define DSCR_DSCRD_IMPRECISE_ABORT (0x1 << 19)
163 #define DSCR_EXT_DCC_MASK (0x3 << 20) /* DTR mode */ /* bits 22, 23 are reserved */
164 #define DSCR_INSTR_COMP (0x1 << 24)
165 #define DSCR_PIPE_ADVANCE (0x1 << 25)
166 #define DSCR_DTRTX_FULL_LATCHED (0x1 << 26)
167 #define DSCR_DTRRX_FULL_LATCHED (0x1 << 27) /* bit 28 is reserved */
168 #define DSCR_DTR_TX_FULL (0x1 << 29)
169 #define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
170
171 #define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
172 #define DSCR_RUN_MODE(dscr) ((dscr) & (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED))
173
174
175 /* Methods of entry into debug mode */
176 #define DSCR_ENTRY_HALT_REQ (0x0 << 2)
177 #define DSCR_ENTRY_BREAKPOINT (0x1 << 2)
178 #define DSCR_ENTRY_IMPRECISE_WATCHPT (0x2 << 2)
179 #define DSCR_ENTRY_BKPT_INSTR (0x3 << 2)
180 #define DSCR_ENTRY_EXT_DBG_REQ (0x4 << 2)
181 #define DSCR_ENTRY_VECT_CATCH (0x5 << 2)
182 #define DSCR_ENTRY_D_SIDE_ABORT (0x6 << 2) /* v6 only */
183 #define DSCR_ENTRY_I_SIDE_ABORT (0x7 << 2) /* v6 only */
184 #define DSCR_ENTRY_OS_UNLOCK (0x8 << 2)
185 #define DSCR_ENTRY_PRECISE_WATCHPT (0xA << 2)
186
187 /* DTR modes */
188 #define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
189 #define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
190 #define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */
191
192
193
194
195
196 /* DRCR (debug run control register) bits */
197 #define DRCR_HALT (1 << 0)
198 #define DRCR_RESTART (1 << 1)
199 #define DRCR_CLEAR_EXCEPTIONS (1 << 2)
200
201 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
202
203 #endif /* __ARM_DPM_H */