1 /***************************************************************************
2 * Copyright (C) 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
20 #define OPENOCD_TARGET_ARM_DISASSEMBLER_H
22 enum arm_instruction_type
{
23 ARM_UNKNOWN_INSTUCTION
,
25 /* Branch instructions */
31 /* Data processing instructions */
49 /* Load/store instructions */
70 /* Status register access instructions */
74 /* Multiply instructions */
82 /* Miscellaneous instructions */
85 /* Exception return instructions */
88 /* Exception generating instructions */
94 /* Coprocessor instructions */
101 /* Semaphore instructions */
105 /* Enhanced DSP extensions */
122 ARM_UNDEFINED_INSTRUCTION
= 0xffffffff,
125 struct arm_b_bl_bx_blx_instr
{
127 uint32_t target_address
;
130 union arm_shifter_operand
{
136 uint8_t shift
; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
146 struct arm_data_proc_instr
{
147 int variant
; /* 0: immediate, 1: immediate_shift, 2: register_shift */
151 union arm_shifter_operand shifter_operand
;
154 struct arm_load_store_instr
{
158 int index_mode
; /* 0: offset, 1: pre-indexed, 2: post-indexed */
159 int offset_mode
; /* 0: immediate, 1: (scaled) register */
164 uint8_t shift
; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
170 struct arm_load_store_multiple_instr
{
172 uint32_t register_list
;
173 uint8_t addressing_mode
; /* 0: IA, 1: IB, 2: DA, 3: DB */
178 struct arm_instruction
{
179 enum arm_instruction_type type
;
183 /* return value ... Thumb-2 sizes vary */
184 unsigned instruction_size
;
187 struct arm_b_bl_bx_blx_instr b_bl_bx_blx
;
188 struct arm_data_proc_instr data_proc
;
189 struct arm_load_store_instr load_store
;
190 struct arm_load_store_multiple_instr load_store_multiple
;
195 int arm_evaluate_opcode(uint32_t opcode
, uint32_t address
,
196 struct arm_instruction
*instruction
);
197 int thumb_evaluate_opcode(uint16_t opcode
, uint32_t address
,
198 struct arm_instruction
*instruction
);
199 int thumb2_opcode(struct target
*target
, uint32_t address
,
200 struct arm_instruction
*instruction
);
201 int arm_access_size(struct arm_instruction
*instruction
);
203 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
205 #endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */
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