src/target/arm_disassembler.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2006 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
   9 #define OPENOCD_TARGET_ARM_DISASSEMBLER_H
  10
  11 enum arm_instruction_type {
  12         ARM_UNKNOWN_INSTRUCTION,
  13
  14         /* Branch instructions */
  15         ARM_B,
  16         ARM_BL,
  17         ARM_BX,
  18         ARM_BLX,
  19
  20         /* Data processing instructions */
  21         ARM_AND,
  22         ARM_EOR,
  23         ARM_SUB,
  24         ARM_RSB,
  25         ARM_ADD,
  26         ARM_ADC,
  27         ARM_SBC,
  28         ARM_RSC,
  29         ARM_TST,
  30         ARM_TEQ,
  31         ARM_CMP,
  32         ARM_CMN,
  33         ARM_ORR,
  34         ARM_MOV,
  35         ARM_BIC,
  36         ARM_MVN,
  37
  38         /* Load/store instructions */
  39         ARM_LDR,
  40         ARM_LDRB,
  41         ARM_LDRT,
  42         ARM_LDRBT,
  43
  44         ARM_LDRH,
  45         ARM_LDRSB,
  46         ARM_LDRSH,
  47
  48         ARM_LDM,
  49
  50         ARM_STR,
  51         ARM_STRB,
  52         ARM_STRT,
  53         ARM_STRBT,
  54
  55         ARM_STRH,
  56
  57         ARM_STM,
  58
  59         /* Status register access instructions */
  60         ARM_MRS,
  61         ARM_MSR,
  62
  63         /* Multiply instructions */
  64         ARM_MUL,
  65         ARM_MLA,
  66         ARM_SMULL,
  67         ARM_SMLAL,
  68         ARM_UMULL,
  69         ARM_UMLAL,
  70
  71         /* Miscellaneous instructions */
  72         ARM_CLZ,
  73
  74         /* Exception return instructions */
  75         ARM_ERET,
  76
  77         /* Exception generating instructions */
  78         ARM_BKPT,
  79         ARM_SWI,
  80         ARM_HVC,
  81         ARM_SMC,
  82
  83         /* Coprocessor instructions */
  84         ARM_CDP,
  85         ARM_LDC,
  86         ARM_STC,
  87         ARM_MCR,
  88         ARM_MRC,
  89
  90         /* Semaphore instructions */
  91         ARM_SWP,
  92         ARM_SWPB,
  93
  94         /* Enhanced DSP extensions */
  95         ARM_MCRR,
  96         ARM_MRRC,
  97         ARM_PLD,
  98         ARM_DSB,
  99         ARM_ISB,
 100         ARM_QADD,
 101         ARM_QDADD,
 102         ARM_QSUB,
 103         ARM_QDSUB,
 104         ARM_SMLAXY,
 105         ARM_SMLALXY,
 106         ARM_SMLAWY,
 107         ARM_SMULXY,
 108         ARM_SMULWY,
 109         ARM_LDRD,
 110         ARM_STRD,
 111
 112         ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 113 };
 114
 115 struct arm_b_bl_bx_blx_instr {
 116         int reg_operand;
 117         uint32_t target_address;
 118 };
 119
 120 union arm_shifter_operand {
 121         struct {
 122                 uint32_t immediate;
 123         } immediate;
 124         struct {
 125                 uint8_t rm;
 126                 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 127                 uint8_t shift_imm;
 128         } immediate_shift;
 129         struct {
 130                 uint8_t rm;
 131                 uint8_t shift;
 132                 uint8_t rs;
 133         } register_shift;
 134 };
 135
 136 struct arm_data_proc_instr {
 137         int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
 138         uint8_t s;
 139         uint8_t rn;
 140         uint8_t rd;
 141         union arm_shifter_operand shifter_operand;
 142 };
 143
 144 struct arm_load_store_instr {
 145         uint8_t rd;
 146         uint8_t rn;
 147         uint8_t u;
 148         int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
 149         int offset_mode; /* 0: immediate, 1: (scaled) register */
 150         union {
 151                 uint32_t offset;
 152                 struct {
 153                         uint8_t rm;
 154                         uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 155                         uint8_t shift_imm;
 156                 } reg;
 157         } offset;
 158 };
 159
 160 struct arm_load_store_multiple_instr {
 161         uint8_t rn;
 162         uint32_t register_list;
 163         uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
 164         uint8_t s;
 165         uint8_t w;
 166 };
 167
 168 struct arm_instruction {
 169         enum arm_instruction_type type;
 170         char text[128];
 171         uint32_t opcode;
 172
 173         /* return value ... Thumb-2 sizes vary */
 174         unsigned instruction_size;
 175
 176         union {
 177                 struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
 178                 struct arm_data_proc_instr data_proc;
 179                 struct arm_load_store_instr load_store;
 180                 struct arm_load_store_multiple_instr load_store_multiple;
 181         } info;
 182
 183 };
 184
 185 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
 186                 struct arm_instruction *instruction);
 187 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
 188                 struct arm_instruction *instruction);
 189 int arm_access_size(struct arm_instruction *instruction);
 190 #if HAVE_CAPSTONE
 191 int arm_disassemble(struct command_invocation *cmd, struct target *target,
 192                 target_addr_t address, size_t count, bool thumb_mode);
 193 #endif
 194
 195 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
 196
 197 #endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */