src/target/arm_disassembler.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifndef ARM_DISASSEMBLER_H
  21 #define ARM_DISASSEMBLER_H
  22
  23 #include "types.h"
  24
  25 enum arm_instruction_type
  26 {
  27         ARM_UNKNOWN_INSTUCTION,
  28
  29         /* Branch instructions */
  30         ARM_B,
  31         ARM_BL,
  32         ARM_BX,
  33         ARM_BLX,
  34
  35         /* Data processing instructions */
  36         ARM_AND,
  37         ARM_EOR,
  38         ARM_SUB,
  39         ARM_RSB,
  40         ARM_ADD,
  41         ARM_ADC,
  42         ARM_SBC,
  43         ARM_RSC,
  44         ARM_TST,
  45         ARM_TEQ,
  46         ARM_CMP,
  47         ARM_CMN,
  48         ARM_ORR,
  49         ARM_MOV,
  50         ARM_BIC,
  51         ARM_MVN,
  52
  53         /* Load/store instructions */
  54         ARM_LDR,
  55         ARM_LDRB,
  56         ARM_LDRT,
  57         ARM_LDRBT,
  58
  59         ARM_LDRH,
  60         ARM_LDRSB,
  61         ARM_LDRSH,
  62
  63         ARM_LDM,
  64
  65         ARM_STR,
  66         ARM_STRB,
  67         ARM_STRT,
  68         ARM_STRBT,
  69
  70         ARM_STRH,
  71
  72         ARM_STM,
  73
  74         /* Status register access instructions */
  75         ARM_MRS,
  76         ARM_MSR,
  77
  78         /* Multiply instructions */
  79         ARM_MUL,
  80         ARM_MLA,
  81         ARM_SMULL,
  82         ARM_SMLAL,
  83         ARM_UMULL,
  84         ARM_UMLAL,
  85
  86         /* Miscellaneous instructions */
  87         ARM_CLZ,
  88
  89         /* Exception generating instructions */
  90         ARM_BKPT,
  91         ARM_SWI,
  92
  93         /* Coprocessor instructions */
  94         ARM_CDP,
  95         ARM_LDC,
  96         ARM_STC,
  97         ARM_MCR,
  98         ARM_MRC,
  99
 100         /* Semaphore instructions */
 101         ARM_SWP,
 102         ARM_SWPB,
 103
 104         /* Enhanced DSP extensions */
 105         ARM_MCRR,
 106         ARM_MRRC,
 107         ARM_PLD,
 108         ARM_QADD,
 109         ARM_QDADD,
 110         ARM_QSUB,
 111         ARM_QDSUB,
 112         ARM_SMLAxy,
 113         ARM_SMLALxy,
 114         ARM_SMLAWy,
 115         ARM_SMULxy,
 116         ARM_SMULWy,
 117         ARM_LDRD,
 118         ARM_STRD,
 119
 120         ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 121 };
 122
 123 struct arm_b_bl_bx_blx_instr
 124 {
 125         int reg_operand;
 126         uint32_t target_address;
 127 };
 128
 129 union arm_shifter_operand
 130 {
 131         struct {
 132                 uint32_t immediate;
 133         } immediate;
 134         struct {
 135                 uint8_t Rm;
 136                 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 137                 uint8_t shift_imm;
 138         } immediate_shift;
 139         struct {
 140                 uint8_t Rm;
 141                 uint8_t shift;
 142                 uint8_t Rs;
 143         } register_shift;
 144 };
 145
 146 struct arm_data_proc_instr
 147 {
 148         int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
 149         uint8_t S;
 150         uint8_t Rn;
 151         uint8_t Rd;
 152         union arm_shifter_operand shifter_operand;
 153 };
 154
 155 typedef struct arm_load_store_instr_s
 156 {
 157         uint8_t Rd;
 158         uint8_t Rn;
 159         uint8_t U;
 160         int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
 161         int offset_mode; /* 0: immediate, 1: (scaled) register */
 162         union
 163         {
 164                 uint32_t offset;
 165                 struct {
 166                         uint8_t Rm;
 167                         uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 168                         uint8_t shift_imm;
 169                 } reg;
 170         } offset;
 171 } arm_load_store_instr_t;
 172
 173 typedef struct arm_load_store_multiple_instr_s
 174 {
 175         uint8_t Rn;
 176         uint32_t register_list;
 177         uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
 178         uint8_t S;
 179         uint8_t W;
 180 } arm_load_store_multiple_instr_t;
 181
 182 typedef struct arm_instruction_s
 183 {
 184         enum arm_instruction_type type;
 185         char text[128];
 186         uint32_t opcode;
 187
 188         /* return value ... Thumb-2 sizes vary */
 189         unsigned instruction_size;
 190
 191         union {
 192                 struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
 193                 struct arm_data_proc_instr data_proc;
 194                 arm_load_store_instr_t load_store;
 195                 arm_load_store_multiple_instr_t load_store_multiple;
 196         } info;
 197
 198 } arm_instruction_t;
 199
 200 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
 201                 arm_instruction_t *instruction);
 202 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
 203                 arm_instruction_t *instruction);
 204 int thumb2_opcode(target_t *target, uint32_t address,
 205                 arm_instruction_t *instruction);
 206 int arm_access_size(arm_instruction_t *instruction);
 207
 208 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
 209
 210 #endif /* ARM_DISASSEMBLER_H */