- split fileio handling into fileio part and image handling
[openocd.git] / src / target / arm_disassembler.h
1 /***************************************************************************
2 * Copyright (C) 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifndef ARM_DISASSEMBLER_H
21 #define ARM_DISASSEMBLER_H
22
23 #include "types.h"
24
25 enum arm_instruction_type
26 {
27 ARM_UNKNOWN_INSTUCTION,
28
29 /* Branch instructions */
30 ARM_B,
31 ARM_BL,
32 ARM_BX,
33 ARM_BLX,
34
35 /* Data processing instructions */
36 ARM_AND,
37 ARM_EOR,
38 ARM_SUB,
39 ARM_RSB,
40 ARM_ADD,
41 ARM_ADC,
42 ARM_SBC,
43 ARM_RSC,
44 ARM_TST,
45 ARM_TEQ,
46 ARM_CMP,
47 ARM_CMN,
48 ARM_ORR,
49 ARM_MOV,
50 ARM_BIC,
51 ARM_MVN,
52
53 /* Load/store instructions */
54 ARM_LDR,
55 ARM_LDRB,
56 ARM_LDRT,
57 ARM_LDRBT,
58
59 ARM_LDRH,
60 ARM_LDRSB,
61 ARM_LDRSH,
62
63 ARM_LDM,
64
65 ARM_STR,
66 ARM_STRB,
67 ARM_STRT,
68 ARM_STRBT,
69
70 ARM_STRH,
71
72 ARM_STM,
73
74 /* Status register access instructions */
75 ARM_MRS,
76 ARM_MSR,
77
78 /* Multiply instructions */
79 ARM_MUL,
80 ARM_MLA,
81 ARM_SMULL,
82 ARM_SMLAL,
83 ARM_UMULL,
84 ARM_UMLAL,
85
86 /* Miscellaneous instructions */
87 ARM_CLZ,
88
89 /* Exception generating instructions */
90 ARM_BKPT,
91 ARM_SWI,
92
93 /* Coprocessor instructions */
94 ARM_CDP,
95 ARM_LDC,
96 ARM_STC,
97 ARM_MCR,
98 ARM_MRC,
99
100 /* Semaphore instructions */
101 ARM_SWP,
102 ARM_SWPB,
103
104 /* Enhanced DSP extensions */
105 ARM_MCRR,
106 ARM_MRRC,
107 ARM_PLD,
108 ARM_QADD,
109 ARM_QDADD,
110 ARM_QSUB,
111 ARM_QDSUB,
112 ARM_SMLAxy,
113 ARM_SMLALxy,
114 ARM_SMLAWy,
115 ARM_SMULxy,
116 ARM_SMULWy,
117 ARM_LDRD,
118 ARM_STRD,
119
120 ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
121 };
122
123 typedef struct arm_b_bl_bx_blx_instr_s
124 {
125 int reg_operand;
126 u32 target_address;
127 } arm_b_bl_bx_blx_instr_t;
128
129 union arm_shifter_operand
130 {
131 struct {
132 u32 immediate;
133 } immediate;
134 struct {
135 u8 Rm;
136 u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
137 u8 shift_imm;
138 } immediate_shift;
139 struct {
140 u8 Rm;
141 u8 shift;
142 u8 Rs;
143 } register_shift;
144 };
145
146 typedef struct arm_data_proc_instr_s
147 {
148 int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
149 u8 S;
150 u8 Rn;
151 u8 Rd;
152 union arm_shifter_operand shifter_operand;
153 } arm_data_proc_instr_t;
154
155 typedef struct arm_load_store_instr_s
156 {
157 u8 Rd;
158 u8 Rn;
159 u8 U;
160 int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
161 int offset_mode; /* 0: immediate, 1: (scaled) register */
162 union
163 {
164 u32 offset;
165 struct {
166 u8 Rm;
167 u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
168 u8 shift_imm;
169 } reg;
170 } offset;
171 } arm_load_store_instr_t;
172
173 typedef struct arm_load_store_multiple_instr_s
174 {
175 u8 Rn;
176 u32 register_list;
177 u8 addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
178 u8 S;
179 u8 W;
180 } arm_load_store_multiple_instr_t;
181
182 typedef struct arm_instruction_s
183 {
184 enum arm_instruction_type type;
185 char text[128];
186 u32 opcode;
187
188 union {
189 arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
190 arm_data_proc_instr_t data_proc;
191 arm_load_store_instr_t load_store;
192 arm_load_store_multiple_instr_t load_store_multiple;
193 } info;
194
195 } arm_instruction_t;
196
197 extern int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
198 extern int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instruction);
199
200 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])
201
202 #endif /* ARM_DISASSEMBLER_H */