src/target/arm_adi_v5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  22  ***************************************************************************/
  23
  24 #ifndef ARM_ADI_V5_H
  25 #define ARM_ADI_V5_H
  26
  27 /**
  28  * @file
  29  * This defines formats and data structures used to talk to ADIv5 entities.
  30  * Those include a DAP, different types of Debug Port (DP), and memory mapped
  31  * resources accessed through a MEM-AP.
  32  */
  33
  34 #include <helper/list.h>
  35 #include "arm_jtag.h"
  36
  37 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
  38  * is no longer JTAG-specific
  39  */
  40 #define JTAG_DP_DPACC           0xA
  41 #define JTAG_DP_APACC           0xB
  42
  43 /* three-bit ACK values for SWD access (sent LSB first) */
  44 #define SWD_ACK_OK    0x1
  45 #define SWD_ACK_WAIT  0x2
  46 #define SWD_ACK_FAULT 0x4
  47
  48 #define DPAP_WRITE              0
  49 #define DPAP_READ               1
  50
  51 #define BANK_REG(bank, reg)     (((bank) << 4) | (reg))
  52
  53 /* A[3:0] for DP registers; A[1:0] are always zero.
  54  * - JTAG accesses all of these via JTAG_DP_DPACC, except for
  55  *   IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
  56  * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
  57  */
  58 #define DP_IDCODE               BANK_REG(0x0, 0x0)      /* SWD: read */
  59 #define DP_ABORT                BANK_REG(0x0, 0x0)      /* SWD: write */
  60 #define DP_CTRL_STAT            BANK_REG(0x0, 0x4)      /* r/w */
  61 #define DP_RESEND               BANK_REG(0x0, 0x8)      /* SWD: read */
  62 #define DP_SELECT               BANK_REG(0x0, 0x8)      /* JTAG: r/w; SWD: write */
  63 #define DP_RDBUFF               BANK_REG(0x0, 0xC)      /* read-only */
  64 #define DP_WCR                  BANK_REG(0x1, 0x4)      /* SWD: r/w */
  65
  66 #define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8)))    /* 1..4 clocks */
  67 #define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr))))          /* impl defined */
  68
  69 /* Fields of the DP's AP ABORT register */
  70 #define DAPABORT        (1UL << 0)
  71 #define STKCMPCLR       (1UL << 1) /* SWD-only */
  72 #define STKERRCLR       (1UL << 2) /* SWD-only */
  73 #define WDERRCLR        (1UL << 3) /* SWD-only */
  74 #define ORUNERRCLR      (1UL << 4) /* SWD-only */
  75
  76 /* Fields of the DP's CTRL/STAT register */
  77 #define CORUNDETECT     (1UL << 0)
  78 #define SSTICKYORUN     (1UL << 1)
  79 /* 3:2 - transaction mode (e.g. pushed compare) */
  80 #define SSTICKYCMP      (1UL << 4)
  81 #define SSTICKYERR      (1UL << 5)
  82 #define READOK          (1UL << 6) /* SWD-only */
  83 #define WDATAERR        (1UL << 7) /* SWD-only */
  84 /* 11:8 - mask lanes for pushed compare or verify ops */
  85 /* 21:12 - transaction counter */
  86 #define CDBGRSTREQ      (1UL << 26)
  87 #define CDBGRSTACK      (1UL << 27)
  88 #define CDBGPWRUPREQ    (1UL << 28)
  89 #define CDBGPWRUPACK    (1UL << 29)
  90 #define CSYSPWRUPREQ    (1UL << 30)
  91 #define CSYSPWRUPACK    (1UL << 31)
  92
  93 /* MEM-AP register addresses */
  94 #define MEM_AP_REG_CSW          0x00
  95 #define MEM_AP_REG_TAR          0x04
  96 #define MEM_AP_REG_TAR64        0x08            /* RW: Large Physical Address Extension */
  97 #define MEM_AP_REG_DRW          0x0C            /* RW: Data Read/Write register */
  98 #define MEM_AP_REG_BD0          0x10            /* RW: Banked Data register 0-3 */
  99 #define MEM_AP_REG_BD1          0x14
 100 #define MEM_AP_REG_BD2          0x18
 101 #define MEM_AP_REG_BD3          0x1C
 102 #define MEM_AP_REG_MBT          0x20            /* --: Memory Barrier Transfer register */
 103 #define MEM_AP_REG_BASE64       0xF0            /* RO: Debug Base Address (LA) register */
 104 #define MEM_AP_REG_CFG          0xF4            /* RO: Configuration register */
 105 #define MEM_AP_REG_BASE         0xF8            /* RO: Debug Base Address register */
 106 /* Generic AP register address */
 107 #define AP_REG_IDR                      0xFC            /* RO: Identification Register */
 108
 109 /* Fields of the MEM-AP's CSW register */
 110 #define CSW_8BIT                0
 111 #define CSW_16BIT               1
 112 #define CSW_32BIT               2
 113 #define CSW_ADDRINC_MASK    (3UL << 4)
 114 #define CSW_ADDRINC_OFF     0UL
 115 #define CSW_ADDRINC_SINGLE  (1UL << 4)
 116 #define CSW_ADDRINC_PACKED  (2UL << 4)
 117 #define CSW_DEVICE_EN       (1UL << 6)
 118 #define CSW_TRIN_PROG       (1UL << 7)
 119 #define CSW_SPIDEN          (1UL << 23)
 120 /* 30:24 - implementation-defined! */
 121 #define CSW_HPROT           (1UL << 25) /* ? */
 122 #define CSW_MASTER_DEBUG    (1UL << 29) /* ? */
 123 #define CSW_SPROT           (1UL << 30)
 124 #define CSW_DBGSWENABLE     (1UL << 31)
 125
 126 /* Fields of the MEM-AP's IDR register */
 127 #define IDR_REV     (0xFUL << 28)
 128 #define IDR_JEP106  (0x7FFUL << 17)
 129 #define IDR_CLASS   (0xFUL << 13)
 130 #define IDR_VARIANT (0xFUL << 4)
 131 #define IDR_TYPE    (0xFUL << 0)
 132
 133 #define IDR_JEP106_ARM 0x04760000
 134
 135 #define DP_SELECT_APSEL 0xFF000000
 136 #define DP_SELECT_APBANK 0x000000F0
 137 #define DP_SELECT_DPBANK 0x0000000F
 138 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
 139
 140 /**
 141  * This represents an ARM Debug Interface (v5) Access Port (AP).
 142  * Most common is a MEM-AP, for memory access.
 143  */
 144 struct adiv5_ap {
 145         /**
 146          * DAP this AP belongs to.
 147          */
 148         struct adiv5_dap *dap;
 149
 150         /**
 151          * Number of this AP.
 152          */
 153         uint8_t ap_num;
 154
 155         /**
 156          * Default value for (MEM-AP) AP_REG_CSW register.
 157          */
 158         uint32_t csw_default;
 159
 160         /**
 161          * Cache for (MEM-AP) AP_REG_CSW register value.  This is written to
 162          * configure an access mode, such as autoincrementing AP_REG_TAR during
 163          * word access.  "-1" indicates no cached value.
 164          */
 165         uint32_t csw_value;
 166
 167         /**
 168          * Cache for (MEM-AP) AP_REG_TAR register value This is written to
 169          * configure the address being read or written
 170          * "-1" indicates no cached value.
 171          */
 172         uint32_t tar_value;
 173
 174         /**
 175          * Configures how many extra tck clocks are added after starting a
 176          * MEM-AP access before we try to read its status (and/or result).
 177          */
 178         uint32_t memaccess_tck;
 179
 180         /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 181         uint32_t tar_autoincr_block;
 182
 183         /* true if packed transfers are supported by the MEM-AP */
 184         bool packed_transfers;
 185
 186         /* true if unaligned memory access is not supported by the MEM-AP */
 187         bool unaligned_access_bad;
 188 };
 189
 190
 191 /**
 192  * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
 193  * A DAP has two types of component:  one Debug Port (DP), which is a
 194  * transport agent; and at least one Access Port (AP), controlling
 195  * resource access.
 196  *
 197  * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
 198  * Accordingly, this interface is responsible for hiding the transport
 199  * differences so upper layer code can largely ignore them.
 200  *
 201  * When the chip is implemented with JTAG-DP or SW-DP, the transport is
 202  * fixed as JTAG or SWD, respectively.  Chips incorporating SWJ-DP permit
 203  * a choice made at board design time (by only using the SWD pins), or
 204  * as part of setting up a debug session (if all the dual-role JTAG/SWD
 205  * signals are available).
 206  */
 207 struct adiv5_dap {
 208         const struct dap_ops *ops;
 209
 210         /* dap transaction list for WAIT support */
 211         struct list_head cmd_journal;
 212
 213         struct jtag_tap *tap;
 214         /* Control config */
 215         uint32_t dp_ctrl_stat;
 216
 217         struct adiv5_ap ap[256];
 218
 219         /* The current manually selected AP by the "dap apsel" command */
 220         uint32_t apsel;
 221
 222         /**
 223          * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
 224          * indicates no cached value and forces rewrite of the register.
 225          */
 226         uint32_t select;
 227
 228         /* information about current pending SWjDP-AHBAP transaction */
 229         uint8_t  ack;
 230
 231         /**
 232          * Holds the pointer to the destination word for the last queued read,
 233          * for use with posted AP read sequence optimization.
 234          */
 235         uint32_t *last_read;
 236
 237         /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
 238          * despite lack of support in the ARMv7 architecture. Memory access through
 239          * the AHB-AP has strange byte ordering these processors, and we need to
 240          * swizzle appropriately. */
 241         bool ti_be_32_quirks;
 242
 243         /**
 244          * Signals that an attempt to reestablish communication afresh
 245          * should be performed before the next access.
 246          */
 247         bool do_reconnect;
 248 };
 249
 250 /**
 251  * Transport-neutral representation of queued DAP transactions, supporting
 252  * both JTAG and SWD transports.  All submitted transactions are logically
 253  * queued, until the queue is executed by run().  Some implementations might
 254  * execute transactions as soon as they're submitted, but no status is made
 255  * available until run().
 256  */
 257 struct dap_ops {
 258         /** DP register read. */
 259         int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
 260                         uint32_t *data);
 261         /** DP register write. */
 262         int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
 263                         uint32_t data);
 264
 265         /** AP register read. */
 266         int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
 267                         uint32_t *data);
 268         /** AP register write. */
 269         int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
 270                         uint32_t data);
 271
 272         /** AP operation abort. */
 273         int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
 274
 275         /** Executes all queued DAP operations. */
 276         int (*run)(struct adiv5_dap *dap);
 277 };
 278
 279 /*
 280  * Access Port classes
 281  */
 282 enum ap_class {
 283         AP_CLASS_NONE   = 0x00000,  /* No class defined */
 284         AP_CLASS_MEM_AP = 0x10000,  /* MEM-AP */
 285 };
 286
 287 /*
 288  * Access Port types
 289  */
 290 enum ap_type {
 291         AP_TYPE_JTAG_AP = 0x0,  /* JTAG-AP - JTAG master for controlling other JTAG devices */
 292         AP_TYPE_AHB_AP  = 0x1,  /* AHB Memory-AP */
 293         AP_TYPE_APB_AP  = 0x2,  /* APB Memory-AP */
 294         AP_TYPE_AXI_AP  = 0x4,  /* AXI Memory-AP */
 295 };
 296
 297 /**
 298  * Queue a DP register read.
 299  * Note that not all DP registers are readable; also, that JTAG and SWD
 300  * have slight differences in DP register support.
 301  *
 302  * @param dap The DAP used for reading.
 303  * @param reg The two-bit number of the DP register being read.
 304  * @param data Pointer saying where to store the register's value
 305  * (in host endianness).
 306  *
 307  * @return ERROR_OK for success, else a fault code.
 308  */
 309 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
 310                 unsigned reg, uint32_t *data)
 311 {
 312         assert(dap->ops != NULL);
 313         return dap->ops->queue_dp_read(dap, reg, data);
 314 }
 315
 316 /**
 317  * Queue a DP register write.
 318  * Note that not all DP registers are writable; also, that JTAG and SWD
 319  * have slight differences in DP register support.
 320  *
 321  * @param dap The DAP used for writing.
 322  * @param reg The two-bit number of the DP register being written.
 323  * @param data Value being written (host endianness)
 324  *
 325  * @return ERROR_OK for success, else a fault code.
 326  */
 327 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
 328                 unsigned reg, uint32_t data)
 329 {
 330         assert(dap->ops != NULL);
 331         return dap->ops->queue_dp_write(dap, reg, data);
 332 }
 333
 334 /**
 335  * Queue an AP register read.
 336  *
 337  * @param ap The AP used for reading.
 338  * @param reg The number of the AP register being read.
 339  * @param data Pointer saying where to store the register's value
 340  * (in host endianness).
 341  *
 342  * @return ERROR_OK for success, else a fault code.
 343  */
 344 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
 345                 unsigned reg, uint32_t *data)
 346 {
 347         assert(ap->dap->ops != NULL);
 348         return ap->dap->ops->queue_ap_read(ap, reg, data);
 349 }
 350
 351 /**
 352  * Queue an AP register write.
 353  *
 354  * @param ap The AP used for writing.
 355  * @param reg The number of the AP register being written.
 356  * @param data Value being written (host endianness)
 357  *
 358  * @return ERROR_OK for success, else a fault code.
 359  */
 360 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
 361                 unsigned reg, uint32_t data)
 362 {
 363         assert(ap->dap->ops != NULL);
 364         return ap->dap->ops->queue_ap_write(ap, reg, data);
 365 }
 366
 367 /**
 368  * Queue an AP abort operation.  The current AP transaction is aborted,
 369  * including any update of the transaction counter.  The AP is left in
 370  * an unknown state (so it must be re-initialized).  For use only after
 371  * the AP has reported WAIT status for an extended period.
 372  *
 373  * @param dap The DAP used for writing.
 374  * @param ack Pointer to where transaction status will be stored.
 375  *
 376  * @return ERROR_OK for success, else a fault code.
 377  */
 378 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 379 {
 380         assert(dap->ops != NULL);
 381         return dap->ops->queue_ap_abort(dap, ack);
 382 }
 383
 384 /**
 385  * Perform all queued DAP operations, and clear any errors posted in the
 386  * CTRL_STAT register when they are done.  Note that if more than one AP
 387  * operation will be queued, one of the first operations in the queue
 388  * should probably enable CORUNDETECT in the CTRL/STAT register.
 389  *
 390  * @param dap The DAP used.
 391  *
 392  * @return ERROR_OK for success, else a fault code.
 393  */
 394 static inline int dap_run(struct adiv5_dap *dap)
 395 {
 396         assert(dap->ops != NULL);
 397         return dap->ops->run(dap);
 398 }
 399
 400 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
 401                                      uint32_t *value)
 402 {
 403         int retval;
 404
 405         retval = dap_queue_dp_read(dap, reg, value);
 406         if (retval != ERROR_OK)
 407                 return retval;
 408
 409         return dap_run(dap);
 410 }
 411
 412 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
 413                                        uint32_t mask, uint32_t value, int timeout)
 414 {
 415         assert(timeout > 0);
 416         assert((value & mask) == value);
 417
 418         int ret;
 419         uint32_t regval;
 420         LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
 421                   reg, mask, value);
 422         do {
 423                 ret = dap_dp_read_atomic(dap, reg, &regval);
 424                 if (ret != ERROR_OK)
 425                         return ret;
 426
 427                 if ((regval & mask) == value)
 428                         break;
 429
 430                 alive_sleep(10);
 431         } while (--timeout);
 432
 433         if (!timeout) {
 434                 LOG_DEBUG("DAP: poll %x timeout", reg);
 435                 return ERROR_WAIT;
 436         } else {
 437                 return ERROR_OK;
 438         }
 439 }
 440
 441 /* Queued MEM-AP memory mapped single word transfers. */
 442 int mem_ap_read_u32(struct adiv5_ap *ap,
 443                 uint32_t address, uint32_t *value);
 444 int mem_ap_write_u32(struct adiv5_ap *ap,
 445                 uint32_t address, uint32_t value);
 446
 447 /* Synchronous MEM-AP memory mapped single word transfers. */
 448 int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
 449                 uint32_t address, uint32_t *value);
 450 int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
 451                 uint32_t address, uint32_t value);
 452
 453 /* Synchronous MEM-AP memory mapped bus block transfers. */
 454 int mem_ap_read_buf(struct adiv5_ap *ap,
 455                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
 456 int mem_ap_write_buf(struct adiv5_ap *ap,
 457                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
 458
 459 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
 460 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
 461                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
 462 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
 463                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
 464
 465 /* Create DAP struct */
 466 struct adiv5_dap *dap_init(void);
 467
 468 /* Initialisation of the debug system, power domains and registers */
 469 int dap_dp_init(struct adiv5_dap *dap);
 470 int mem_ap_init(struct adiv5_ap *ap);
 471
 472 /* Probe the AP for ROM Table location */
 473 int dap_get_debugbase(struct adiv5_ap *ap,
 474                         uint32_t *dbgbase, uint32_t *apid);
 475
 476 /* Probe Access Ports to find a particular type */
 477 int dap_find_ap(struct adiv5_dap *dap,
 478                         enum ap_type type_to_find,
 479                         struct adiv5_ap **ap_out);
 480
 481 static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
 482 {
 483         return &dap->ap[ap_num];
 484 }
 485
 486 /* Lookup CoreSight component */
 487 int dap_lookup_cs_component(struct adiv5_ap *ap,
 488                         uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
 489
 490 struct target;
 491
 492 /* Put debug link into SWD mode */
 493 int dap_to_swd(struct target *target);
 494
 495 /* Put debug link into JTAG mode */
 496 int dap_to_jtag(struct target *target);
 497
 498 extern const struct command_registration dap_command_handlers[];
 499
 500 #endif