arm_adi_v5: Make the DAP API stateless
[openocd.git] / src / target / arm_adi_v5.h
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
23
24 #ifndef ARM_ADI_V5_H
25 #define ARM_ADI_V5_H
26
27 /**
28 * @file
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
32 */
33
34 #include "arm_jtag.h"
35
36 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
37 * is no longer JTAG-specific
38 */
39 #define JTAG_DP_DPACC 0xA
40 #define JTAG_DP_APACC 0xB
41
42 /* three-bit ACK values for SWD access (sent LSB first) */
43 #define SWD_ACK_OK 0x1
44 #define SWD_ACK_WAIT 0x2
45 #define SWD_ACK_FAULT 0x4
46
47 #define DPAP_WRITE 0
48 #define DPAP_READ 1
49
50 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
51
52 /* A[3:0] for DP registers; A[1:0] are always zero.
53 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
54 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
55 * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
56 */
57 #define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */
58 #define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */
59 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */
60 #define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */
61 #define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */
62 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */
63 #define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */
64
65 #define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */
66 #define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */
67
68 /* Fields of the DP's AP ABORT register */
69 #define DAPABORT (1UL << 0)
70 #define STKCMPCLR (1UL << 1) /* SWD-only */
71 #define STKERRCLR (1UL << 2) /* SWD-only */
72 #define WDERRCLR (1UL << 3) /* SWD-only */
73 #define ORUNERRCLR (1UL << 4) /* SWD-only */
74
75 /* Fields of the DP's CTRL/STAT register */
76 #define CORUNDETECT (1UL << 0)
77 #define SSTICKYORUN (1UL << 1)
78 /* 3:2 - transaction mode (e.g. pushed compare) */
79 #define SSTICKYCMP (1UL << 4)
80 #define SSTICKYERR (1UL << 5)
81 #define READOK (1UL << 6) /* SWD-only */
82 #define WDATAERR (1UL << 7) /* SWD-only */
83 /* 11:8 - mask lanes for pushed compare or verify ops */
84 /* 21:12 - transaction counter */
85 #define CDBGRSTREQ (1UL << 26)
86 #define CDBGRSTACK (1UL << 27)
87 #define CDBGPWRUPREQ (1UL << 28)
88 #define CDBGPWRUPACK (1UL << 29)
89 #define CSYSPWRUPREQ (1UL << 30)
90 #define CSYSPWRUPACK (1UL << 31)
91
92 /* MEM-AP register addresses */
93 #define MEM_AP_REG_CSW 0x00
94 #define MEM_AP_REG_TAR 0x04
95 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
96 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
97 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
98 #define MEM_AP_REG_BD1 0x14
99 #define MEM_AP_REG_BD2 0x18
100 #define MEM_AP_REG_BD3 0x1C
101 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
102 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
103 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
104 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
105 /* Generic AP register address */
106 #define AP_REG_IDR 0xFC /* RO: Identification Register */
107
108 /* Fields of the MEM-AP's CSW register */
109 #define CSW_8BIT 0
110 #define CSW_16BIT 1
111 #define CSW_32BIT 2
112 #define CSW_ADDRINC_MASK (3UL << 4)
113 #define CSW_ADDRINC_OFF 0UL
114 #define CSW_ADDRINC_SINGLE (1UL << 4)
115 #define CSW_ADDRINC_PACKED (2UL << 4)
116 #define CSW_DEVICE_EN (1UL << 6)
117 #define CSW_TRIN_PROG (1UL << 7)
118 #define CSW_SPIDEN (1UL << 23)
119 /* 30:24 - implementation-defined! */
120 #define CSW_HPROT (1UL << 25) /* ? */
121 #define CSW_MASTER_DEBUG (1UL << 29) /* ? */
122 #define CSW_SPROT (1UL << 30)
123 #define CSW_DBGSWENABLE (1UL << 31)
124
125 /* Fields of the MEM-AP's IDR register */
126 #define IDR_REV (0xFUL << 28)
127 #define IDR_JEP106 (0x7FFUL << 17)
128 #define IDR_CLASS (0xFUL << 13)
129 #define IDR_VARIANT (0xFUL << 4)
130 #define IDR_TYPE (0xFUL << 0)
131
132 #define IDR_JEP106_ARM 0x04760000
133
134 #define DP_SELECT_APSEL 0xFF000000
135 #define DP_SELECT_APBANK 0x000000F0
136 #define DP_SELECT_DPBANK 0x0000000F
137 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
138
139 /**
140 * This represents an ARM Debug Interface (v5) Access Port (AP).
141 * Most common is a MEM-AP, for memory access.
142 */
143 struct adiv5_ap {
144 /**
145 * DAP this AP belongs to.
146 */
147 struct adiv5_dap *dap;
148
149 /**
150 * Number of this AP.
151 */
152 uint8_t ap_num;
153
154 /**
155 * Default value for (MEM-AP) AP_REG_CSW register.
156 */
157 uint32_t csw_default;
158
159 /**
160 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
161 * configure an access mode, such as autoincrementing AP_REG_TAR during
162 * word access. "-1" indicates no cached value.
163 */
164 uint32_t csw_value;
165
166 /**
167 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
168 * configure the address being read or written
169 * "-1" indicates no cached value.
170 */
171 uint32_t tar_value;
172
173 /**
174 * Configures how many extra tck clocks are added after starting a
175 * MEM-AP access before we try to read its status (and/or result).
176 */
177 uint32_t memaccess_tck;
178
179 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
180 uint32_t tar_autoincr_block;
181
182 /* true if packed transfers are supported by the MEM-AP */
183 bool packed_transfers;
184
185 /* true if unaligned memory access is not supported by the MEM-AP */
186 bool unaligned_access_bad;
187 };
188
189
190 /**
191 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
192 * A DAP has two types of component: one Debug Port (DP), which is a
193 * transport agent; and at least one Access Port (AP), controlling
194 * resource access.
195 *
196 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
197 * Accordingly, this interface is responsible for hiding the transport
198 * differences so upper layer code can largely ignore them.
199 *
200 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
201 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
202 * a choice made at board design time (by only using the SWD pins), or
203 * as part of setting up a debug session (if all the dual-role JTAG/SWD
204 * signals are available).
205 */
206 struct adiv5_dap {
207 const struct dap_ops *ops;
208
209 struct jtag_tap *tap;
210 /* Control config */
211 uint32_t dp_ctrl_stat;
212
213 struct adiv5_ap ap[256];
214
215 /* The current manually selected AP by the "dap apsel" command */
216 uint32_t apsel;
217
218 /**
219 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
220 * indicates no cached value and forces rewrite of the register.
221 */
222 uint32_t select;
223
224 /* information about current pending SWjDP-AHBAP transaction */
225 uint8_t ack;
226
227 /**
228 * Holds the pointer to the destination word for the last queued read,
229 * for use with posted AP read sequence optimization.
230 */
231 uint32_t *last_read;
232
233 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
234 * despite lack of support in the ARMv7 architecture. Memory access through
235 * the AHB-AP has strange byte ordering these processors, and we need to
236 * swizzle appropriately. */
237 bool ti_be_32_quirks;
238
239 /**
240 * Signals that an attempt to reestablish communication afresh
241 * should be performed before the next access.
242 */
243 bool do_reconnect;
244 };
245
246 /**
247 * Transport-neutral representation of queued DAP transactions, supporting
248 * both JTAG and SWD transports. All submitted transactions are logically
249 * queued, until the queue is executed by run(). Some implementations might
250 * execute transactions as soon as they're submitted, but no status is made
251 * available until run().
252 */
253 struct dap_ops {
254 /** DP register read. */
255 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
256 uint32_t *data);
257 /** DP register write. */
258 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
259 uint32_t data);
260
261 /** AP register read. */
262 int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
263 uint32_t *data);
264 /** AP register write. */
265 int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
266 uint32_t data);
267
268 /** AP operation abort. */
269 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
270
271 /** Executes all queued DAP operations. */
272 int (*run)(struct adiv5_dap *dap);
273 };
274
275 /*
276 * Access Port classes
277 */
278 enum ap_class {
279 AP_CLASS_NONE = 0x00000, /* No class defined */
280 AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */
281 };
282
283 /*
284 * Access Port types
285 */
286 enum ap_type {
287 AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
288 AP_TYPE_AHB_AP = 0x1, /* AHB Memory-AP */
289 AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */
290 AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
291 };
292
293 /**
294 * Queue a DP register read.
295 * Note that not all DP registers are readable; also, that JTAG and SWD
296 * have slight differences in DP register support.
297 *
298 * @param dap The DAP used for reading.
299 * @param reg The two-bit number of the DP register being read.
300 * @param data Pointer saying where to store the register's value
301 * (in host endianness).
302 *
303 * @return ERROR_OK for success, else a fault code.
304 */
305 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
306 unsigned reg, uint32_t *data)
307 {
308 assert(dap->ops != NULL);
309 return dap->ops->queue_dp_read(dap, reg, data);
310 }
311
312 /**
313 * Queue a DP register write.
314 * Note that not all DP registers are writable; also, that JTAG and SWD
315 * have slight differences in DP register support.
316 *
317 * @param dap The DAP used for writing.
318 * @param reg The two-bit number of the DP register being written.
319 * @param data Value being written (host endianness)
320 *
321 * @return ERROR_OK for success, else a fault code.
322 */
323 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
324 unsigned reg, uint32_t data)
325 {
326 assert(dap->ops != NULL);
327 return dap->ops->queue_dp_write(dap, reg, data);
328 }
329
330 /**
331 * Queue an AP register read.
332 *
333 * @param ap The AP used for reading.
334 * @param reg The number of the AP register being read.
335 * @param data Pointer saying where to store the register's value
336 * (in host endianness).
337 *
338 * @return ERROR_OK for success, else a fault code.
339 */
340 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
341 unsigned reg, uint32_t *data)
342 {
343 assert(ap->dap->ops != NULL);
344 return ap->dap->ops->queue_ap_read(ap, reg, data);
345 }
346
347 /**
348 * Queue an AP register write.
349 *
350 * @param ap The AP used for writing.
351 * @param reg The number of the AP register being written.
352 * @param data Value being written (host endianness)
353 *
354 * @return ERROR_OK for success, else a fault code.
355 */
356 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
357 unsigned reg, uint32_t data)
358 {
359 assert(ap->dap->ops != NULL);
360 return ap->dap->ops->queue_ap_write(ap, reg, data);
361 }
362
363 /**
364 * Queue an AP abort operation. The current AP transaction is aborted,
365 * including any update of the transaction counter. The AP is left in
366 * an unknown state (so it must be re-initialized). For use only after
367 * the AP has reported WAIT status for an extended period.
368 *
369 * @param dap The DAP used for writing.
370 * @param ack Pointer to where transaction status will be stored.
371 *
372 * @return ERROR_OK for success, else a fault code.
373 */
374 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
375 {
376 assert(dap->ops != NULL);
377 return dap->ops->queue_ap_abort(dap, ack);
378 }
379
380 /**
381 * Perform all queued DAP operations, and clear any errors posted in the
382 * CTRL_STAT register when they are done. Note that if more than one AP
383 * operation will be queued, one of the first operations in the queue
384 * should probably enable CORUNDETECT in the CTRL/STAT register.
385 *
386 * @param dap The DAP used.
387 *
388 * @return ERROR_OK for success, else a fault code.
389 */
390 static inline int dap_run(struct adiv5_dap *dap)
391 {
392 assert(dap->ops != NULL);
393 return dap->ops->run(dap);
394 }
395
396 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
397 uint32_t *value)
398 {
399 int retval;
400
401 retval = dap_queue_dp_read(dap, reg, value);
402 if (retval != ERROR_OK)
403 return retval;
404
405 return dap_run(dap);
406 }
407
408 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
409 uint32_t mask, uint32_t value, int timeout)
410 {
411 assert(timeout > 0);
412 assert((value & mask) == value);
413
414 int ret;
415 uint32_t regval;
416 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
417 reg, mask, value);
418 do {
419 ret = dap_dp_read_atomic(dap, reg, &regval);
420 if (ret != ERROR_OK)
421 return ret;
422
423 if ((regval & mask) == value)
424 break;
425
426 alive_sleep(10);
427 } while (--timeout);
428
429 if (!timeout) {
430 LOG_DEBUG("DAP: poll %x timeout", reg);
431 return ERROR_WAIT;
432 } else {
433 return ERROR_OK;
434 }
435 }
436
437 /* Queued MEM-AP memory mapped single word transfers. */
438 int mem_ap_read_u32(struct adiv5_ap *ap,
439 uint32_t address, uint32_t *value);
440 int mem_ap_write_u32(struct adiv5_ap *ap,
441 uint32_t address, uint32_t value);
442
443 /* Synchronous MEM-AP memory mapped single word transfers. */
444 int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
445 uint32_t address, uint32_t *value);
446 int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
447 uint32_t address, uint32_t value);
448
449 /* Synchronous MEM-AP memory mapped bus block transfers. */
450 int mem_ap_read_buf(struct adiv5_ap *ap,
451 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
452 int mem_ap_write_buf(struct adiv5_ap *ap,
453 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
454
455 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
456 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
457 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
458 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
459 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
460
461 /* Create DAP struct */
462 struct adiv5_dap *dap_init(void);
463
464 /* Initialisation of the debug system, power domains and registers */
465 int dap_dp_init(struct adiv5_dap *dap);
466 int mem_ap_init(struct adiv5_ap *ap);
467
468 /* Probe the AP for ROM Table location */
469 int dap_get_debugbase(struct adiv5_ap *ap,
470 uint32_t *dbgbase, uint32_t *apid);
471
472 /* Probe Access Ports to find a particular type */
473 int dap_find_ap(struct adiv5_dap *dap,
474 enum ap_type type_to_find,
475 struct adiv5_ap **ap_out);
476
477 static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
478 {
479 return &dap->ap[ap_num];
480 }
481
482 /* Lookup CoreSight component */
483 int dap_lookup_cs_component(struct adiv5_ap *ap,
484 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
485
486 struct target;
487
488 /* Put debug link into SWD mode */
489 int dap_to_swd(struct target *target);
490
491 /* Put debug link into JTAG mode */
492 int dap_to_jtag(struct target *target);
493
494 extern const struct command_registration dap_command_handlers[];
495
496 #endif