e2e83e11e9ebfaca27125784843b501f1b42f7fa
[openocd.git] / src / target / arm_adi_v5.h
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
23
24 #ifndef ARM_ADI_V5_H
25 #define ARM_ADI_V5_H
26
27 /**
28 * @file
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
32 */
33
34 #include "arm_jtag.h"
35
36 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
37 * is no longer JTAG-specific
38 */
39 #define JTAG_DP_DPACC 0xA
40 #define JTAG_DP_APACC 0xB
41
42 /* three-bit ACK values for SWD access (sent LSB first) */
43 #define SWD_ACK_OK 0x4
44 #define SWD_ACK_WAIT 0x2
45 #define SWD_ACK_FAULT 0x1
46
47 #define DPAP_WRITE 0
48 #define DPAP_READ 1
49
50 /* A[3:0] for DP registers; A[1:0] are always zero.
51 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
52 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
53 * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
54 */
55 #define DP_IDCODE 0 /* SWD: read */
56 #define DP_ABORT 0 /* SWD: write */
57 #define DP_CTRL_STAT 0x4 /* r/w */
58 #define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */
59 #define DP_RESEND 0x8 /* SWD: read */
60 #define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */
61 #define DP_RDBUFF 0xC /* read-only */
62
63 #define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8)) /* 1..4 clocks */
64 #define WCR_TO_PRESCALE(wcr) (7 & ((wcr))) /* impl defined */
65
66 /* Fields of the DP's AP ABORT register */
67 #define DAPABORT (1 << 0)
68 #define STKCMPCLR (1 << 1) /* SWD-only */
69 #define STKERRCLR (1 << 2) /* SWD-only */
70 #define WDERRCLR (1 << 3) /* SWD-only */
71 #define ORUNERRCLR (1 << 4) /* SWD-only */
72
73 /* Fields of the DP's CTRL/STAT register */
74 #define CORUNDETECT (1 << 0)
75 #define SSTICKYORUN (1 << 1)
76 /* 3:2 - transaction mode (e.g. pushed compare) */
77 #define SSTICKYCMP (1 << 4)
78 #define SSTICKYERR (1 << 5)
79 #define READOK (1 << 6) /* SWD-only */
80 #define WDATAERR (1 << 7) /* SWD-only */
81 /* 11:8 - mask lanes for pushed compare or verify ops */
82 /* 21:12 - transaction counter */
83 #define CDBGRSTREQ (1 << 26)
84 #define CDBGRSTACK (1 << 27)
85 #define CDBGPWRUPREQ (1 << 28)
86 #define CDBGPWRUPACK (1 << 29)
87 #define CSYSPWRUPREQ (1 << 30)
88 #define CSYSPWRUPACK (1 << 31)
89
90 /* MEM-AP register addresses */
91 /* TODO: rename as MEM_AP_REG_* */
92 #define AP_REG_CSW 0x00
93 #define AP_REG_TAR 0x04
94 #define AP_REG_DRW 0x0C
95 #define AP_REG_BD0 0x10
96 #define AP_REG_BD1 0x14
97 #define AP_REG_BD2 0x18
98 #define AP_REG_BD3 0x1C
99 #define AP_REG_CFG 0xF4 /* big endian? */
100 #define AP_REG_BASE 0xF8
101
102 /* Generic AP register address */
103 #define AP_REG_IDR 0xFC
104
105 /* Fields of the MEM-AP's CSW register */
106 #define CSW_8BIT 0
107 #define CSW_16BIT 1
108 #define CSW_32BIT 2
109 #define CSW_ADDRINC_MASK (3 << 4)
110 #define CSW_ADDRINC_OFF 0
111 #define CSW_ADDRINC_SINGLE (1 << 4)
112 #define CSW_ADDRINC_PACKED (2 << 4)
113 #define CSW_DEVICE_EN (1 << 6)
114 #define CSW_TRIN_PROG (1 << 7)
115 #define CSW_SPIDEN (1 << 23)
116 /* 30:24 - implementation-defined! */
117 #define CSW_HPROT (1 << 25) /* ? */
118 #define CSW_MASTER_DEBUG (1 << 29) /* ? */
119 #define CSW_SPROT (1 << 30)
120 #define CSW_DBGSWENABLE (1 << 31)
121
122 /**
123 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
124 * A DAP has two types of component: one Debug Port (DP), which is a
125 * transport agent; and at least one Access Port (AP), controlling
126 * resource access. Most common is a MEM-AP, for memory access.
127 *
128 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
129 * Accordingly, this interface is responsible for hiding the transport
130 * differences so upper layer code can largely ignore them.
131 *
132 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
133 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
134 * a choice made at board design time (by only using the SWD pins), or
135 * as part of setting up a debug session (if all the dual-role JTAG/SWD
136 * signals are available).
137 */
138 struct adiv5_dap {
139 const struct dap_ops *ops;
140
141 struct arm_jtag *jtag_info;
142 /* Control config */
143 uint32_t dp_ctrl_stat;
144
145 uint32_t apcsw[256];
146 uint32_t apsel;
147
148 /**
149 * Cache for DP_SELECT bits identifying the current AP. A DAP may
150 * connect to multiple APs, such as one MEM-AP for general access,
151 * another reserved for accessing debug modules, and a JTAG-DP.
152 * "-1" indicates no cached value.
153 */
154 uint32_t ap_current;
155
156 /**
157 * Cache for DP_SELECT bits identifying the current four-word AP
158 * register bank. This caches AP register addresss bits 7:4; JTAG
159 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
160 * "-1" indicates no cached value.
161 */
162 uint32_t ap_bank_value;
163
164 /**
165 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
166 * configure an access mode, such as autoincrementing AP_REG_TAR during
167 * word access. "-1" indicates no cached value.
168 */
169 uint32_t ap_csw_value;
170
171 /**
172 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
173 * configure the address being read or written
174 * "-1" indicates no cached value.
175 */
176 uint32_t ap_tar_value;
177
178 /* information about current pending SWjDP-AHBAP transaction */
179 uint8_t ack;
180
181 /**
182 * Configures how many extra tck clocks are added after starting a
183 * MEM-AP access before we try to read its status (and/or result).
184 */
185 uint32_t memaccess_tck;
186
187 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
188 uint32_t tar_autoincr_block;
189 };
190
191 /**
192 * Transport-neutral representation of queued DAP transactions, supporting
193 * both JTAG and SWD transports. All submitted transactions are logically
194 * queued, until the queue is executed by run(). Some implementations might
195 * execute transactions as soon as they're submitted, but no status is made
196 * availablue until run().
197 */
198 struct dap_ops {
199 /** If the DAP transport isn't SWD, it must be JTAG. Upper level
200 * code may need to care about the difference in some cases.
201 */
202 bool is_swd;
203
204 /** Reads the DAP's IDCODe register. */
205 int (*queue_idcode_read)(struct adiv5_dap *dap,
206 uint8_t *ack, uint32_t *data);
207
208 /** DP register read. */
209 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
210 uint32_t *data);
211 /** DP register write. */
212 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
213 uint32_t data);
214
215 /** AP register read. */
216 int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
217 uint32_t *data);
218 /** AP register write. */
219 int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
220 uint32_t data);
221 /** AP read block. */
222 int (*queue_ap_read_block)(struct adiv5_dap *dap, unsigned reg,
223 uint32_t blocksize, uint8_t *buffer);
224
225 /** AP operation abort. */
226 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
227
228 /** Executes all queued DAP operations. */
229 int (*run)(struct adiv5_dap *dap);
230 };
231
232 /*
233 * Access Port types
234 */
235 enum ap_type {
236 AP_TYPE_AHB_AP = 0x01, /* AHB Memory-AP */
237 AP_TYPE_APB_AP = 0x02, /* APB Memory-AP */
238 AP_TYPE_JTAG_AP = 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */
239 };
240
241 /**
242 * Queue an IDCODE register read. This is primarily useful for SWD
243 * transports, where it is required as part of link initialization.
244 * (For JTAG, this register is read as part of scan chain setup.)
245 *
246 * @param dap The DAP used for reading.
247 * @param ack Pointer to where transaction status will be stored.
248 * @param data Pointer saying where to store the IDCODE value.
249 *
250 * @return ERROR_OK for success, else a fault code.
251 */
252 static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
253 uint8_t *ack, uint32_t *data)
254 {
255 assert(dap->ops != NULL);
256 return dap->ops->queue_idcode_read(dap, ack, data);
257 }
258
259 /**
260 * Queue a DP register read.
261 * Note that not all DP registers are readable; also, that JTAG and SWD
262 * have slight differences in DP register support.
263 *
264 * @param dap The DAP used for reading.
265 * @param reg The two-bit number of the DP register being read.
266 * @param data Pointer saying where to store the register's value
267 * (in host endianness).
268 *
269 * @return ERROR_OK for success, else a fault code.
270 */
271 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
272 unsigned reg, uint32_t *data)
273 {
274 assert(dap->ops != NULL);
275 return dap->ops->queue_dp_read(dap, reg, data);
276 }
277
278 /**
279 * Queue a DP register write.
280 * Note that not all DP registers are writable; also, that JTAG and SWD
281 * have slight differences in DP register support.
282 *
283 * @param dap The DAP used for writing.
284 * @param reg The two-bit number of the DP register being written.
285 * @param data Value being written (host endianness)
286 *
287 * @return ERROR_OK for success, else a fault code.
288 */
289 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
290 unsigned reg, uint32_t data)
291 {
292 assert(dap->ops != NULL);
293 return dap->ops->queue_dp_write(dap, reg, data);
294 }
295
296 /**
297 * Queue an AP register read.
298 *
299 * @param dap The DAP used for reading.
300 * @param reg The number of the AP register being read.
301 * @param data Pointer saying where to store the register's value
302 * (in host endianness).
303 *
304 * @return ERROR_OK for success, else a fault code.
305 */
306 static inline int dap_queue_ap_read(struct adiv5_dap *dap,
307 unsigned reg, uint32_t *data)
308 {
309 assert(dap->ops != NULL);
310 return dap->ops->queue_ap_read(dap, reg, data);
311 }
312
313 /**
314 * Queue an AP register write.
315 *
316 * @param dap The DAP used for writing.
317 * @param reg The number of the AP register being written.
318 * @param data Value being written (host endianness)
319 *
320 * @return ERROR_OK for success, else a fault code.
321 */
322 static inline int dap_queue_ap_write(struct adiv5_dap *dap,
323 unsigned reg, uint32_t data)
324 {
325 assert(dap->ops != NULL);
326 return dap->ops->queue_ap_write(dap, reg, data);
327 }
328
329 /**
330 * Queue an AP block read.
331 *
332 * @param dap The DAP used for reading.
333 * @param reg The number of the AP register being read.
334 * @param blocksize The number of the AP register being read.
335 * @param buffer Pointer saying where to store the data
336 * (in host endianness).
337 *
338 * @return ERROR_OK for success, else a fault code.
339 */
340 static inline int dap_queue_ap_read_block(struct adiv5_dap *dap,
341 unsigned reg, unsigned blocksize, uint8_t *buffer)
342 {
343 assert(dap->ops != NULL);
344 return dap->ops->queue_ap_read_block(dap, reg, blocksize, buffer);
345 }
346
347 /**
348 * Queue an AP abort operation. The current AP transaction is aborted,
349 * including any update of the transaction counter. The AP is left in
350 * an unknown state (so it must be re-initialized). For use only after
351 * the AP has reported WAIT status for an extended period.
352 *
353 * @param dap The DAP used for writing.
354 * @param ack Pointer to where transaction status will be stored.
355 *
356 * @return ERROR_OK for success, else a fault code.
357 */
358 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
359 {
360 assert(dap->ops != NULL);
361 return dap->ops->queue_ap_abort(dap, ack);
362 }
363
364 /**
365 * Perform all queued DAP operations, and clear any errors posted in the
366 * CTRL_STAT register when they are done. Note that if more than one AP
367 * operation will be queued, one of the first operations in the queue
368 * should probably enable CORUNDETECT in the CTRL/STAT register.
369 *
370 * @param dap The DAP used.
371 *
372 * @return ERROR_OK for success, else a fault code.
373 */
374 static inline int dap_run(struct adiv5_dap *dap)
375 {
376 assert(dap->ops != NULL);
377 return dap->ops->run(dap);
378 }
379
380 /** Accessor for currently selected DAP-AP number (0..255) */
381 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
382 {
383 return (uint8_t)(swjdp->ap_current >> 24);
384 }
385
386 /* AP selection applies to future AP transactions */
387 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
388
389 /* Queued AP transactions */
390 int dap_setup_accessport(struct adiv5_dap *swjdp,
391 uint32_t csw, uint32_t tar);
392
393 /* Queued MEM-AP memory mapped single word transfers */
394 int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
395 int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
396
397 /* Synchronous MEM-AP memory mapped single word transfers */
398 int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
399 uint32_t address, uint32_t *value);
400 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
401 uint32_t address, uint32_t value);
402
403 /* MEM-AP memory mapped bus block transfers */
404 int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
405 uint8_t *buffer, int count, uint32_t address);
406 int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
407 uint8_t *buffer, int count, uint32_t address);
408 int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
409 uint8_t *buffer, int count, uint32_t address, bool addr_incr);
410
411 int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
412 const uint8_t *buffer, int count, uint32_t address);
413 int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
414 const uint8_t *buffer, int count, uint32_t address);
415 int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
416 const uint8_t *buffer, int count, uint32_t address, bool addr_incr);
417
418 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
419 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
420 uint32_t address, uint32_t *value);
421 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
422 uint32_t address, uint32_t value);
423
424 /* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
425 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
426 uint32_t address, uint32_t *value);
427 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
428 uint32_t address, uint32_t value);
429
430 /* Non incrementing buffer functions for accessing fifos */
431 int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
432 uint8_t *buffer, int count, uint32_t address);
433 int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
434 const uint8_t *buffer, int count, uint32_t address);
435
436 /* MEM-AP memory mapped bus block transfers with selection of ap */
437 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
438 uint8_t *buffer, int count, uint32_t address);
439 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
440 uint8_t *buffer, int count, uint32_t address);
441 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
442 uint8_t *buffer, int count, uint32_t address);
443
444 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
445 const uint8_t *buffer, int count, uint32_t address);
446 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
447 const uint8_t *buffer, int count, uint32_t address);
448 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
449 const uint8_t *buffer, int count, uint32_t address);
450
451 /* Initialisation of the debug system, power domains and registers */
452 int ahbap_debugport_init(struct adiv5_dap *swjdp);
453
454 /* Probe the AP for ROM Table location */
455 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
456 uint32_t *dbgbase, uint32_t *apid);
457
458 /* Probe Access Ports to find a particular type */
459 int dap_find_ap(struct adiv5_dap *dap,
460 enum ap_type type_to_find,
461 uint8_t *ap_num_out);
462
463 /* Lookup CoreSight component */
464 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
465 uint32_t dbgbase, uint8_t type, uint32_t *addr);
466
467 struct target;
468
469 /* Put debug link into SWD mode */
470 int dap_to_swd(struct target *target);
471
472 /* Put debug link into JTAG mode */
473 int dap_to_jtag(struct target *target);
474
475 extern const struct command_registration dap_command_handlers[];
476
477 #endif