src/target/arm_adi_v5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARM_ADI_V5_H
  24 #define ARM_ADI_V5_H
  25
  26 #include "target.h"
  27 #include "register.h"
  28 #include "arm_jtag.h"
  29
  30 #define DAP_IR_DPACC    0xA
  31 #define DAP_IR_APACC    0xB
  32
  33 #define DPAP_WRITE              0
  34 #define DPAP_READ               1
  35 #define DP_ZERO                 0
  36 #define DP_CTRL_STAT    0x4
  37 #define DP_SELECT               0x8
  38 #define DP_RDBUFF               0xC
  39
  40 #define CORUNDETECT             (1 << 0)
  41 #define SSTICKYORUN             (1 << 1)
  42 #define SSTICKYERR              (1 << 5)
  43 #define CDBGRSTREQ              (1 << 26)
  44 #define CDBGRSTACK              (1 << 27)
  45 #define CDBGPWRUPREQ    (1 << 28)
  46 #define CDBGPWRUPACK    (1 << 29)
  47 #define CSYSPWRUPREQ    (1 << 30)
  48 #define CSYSPWRUPACK    (1 << 31)
  49
  50 #define AP_REG_CSW              0x00
  51 #define AP_REG_TAR              0x04
  52 #define AP_REG_DRW              0x0C
  53 #define AP_REG_BD0              0x10
  54 #define AP_REG_BD1              0x14
  55 #define AP_REG_BD2              0x18
  56 #define AP_REG_BD3              0x1C
  57 #define AP_REG_DBGROMA  0xF8
  58 #define AP_REG_IDR              0xFC
  59
  60 #define CSW_8BIT                0
  61 #define CSW_16BIT               1
  62 #define CSW_32BIT               2
  63
  64 #define CSW_ADDRINC_MASK        (3 << 4)
  65 #define CSW_ADDRINC_OFF         0
  66 #define CSW_ADDRINC_SINGLE      (1 << 4)
  67 #define CSW_ADDRINC_PACKED      (2 << 4)
  68 #define CSW_HPROT                       (1 << 25)
  69 #define CSW_MASTER_DEBUG        (1 << 29)
  70 #define CSW_DBGSWENABLE         (1 << 31)
  71
  72 /* transaction mode */
  73 #define TRANS_MODE_NONE                 0
  74 /* Transaction waits for previous to complete */
  75 #define TRANS_MODE_ATOMIC               1
  76 /* Freerunning transactions with delays and overrun checking */
  77 #define TRANS_MODE_COMPOSITE    2
  78
  79 typedef struct swjdp_reg_s
  80 {
  81         int addr;
  82         arm_jtag_t *jtag_info;
  83 } swjdp_reg_t;
  84
  85 typedef struct swjdp_common_s
  86 {
  87         arm_jtag_t *jtag_info;
  88         /* Control config */
  89         uint32_t dp_ctrl_stat;
  90         /* Support for several AP's in one DAP */
  91         uint32_t apsel;
  92         /* Register select cache */
  93         uint32_t dp_select_value;
  94         uint32_t ap_csw_value;
  95         uint32_t ap_tar_value;
  96         /* information about current pending SWjDP-AHBAP transaction */
  97         uint8_t  trans_mode;
  98         uint8_t  trans_rw;
  99         uint8_t  ack;
 100         /* extra tck clocks for memory bus access */
 101         uint32_t        memaccess_tck;
 102         /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 103         uint32_t tar_autoincr_block;
 104
 105 } swjdp_common_t;
 106
 107 /* Accessor function for currently selected DAP-AP number */
 108 static inline uint8_t dap_ap_get_select(swjdp_common_t *swjdp)
 109 {
 110         return (uint8_t)(swjdp ->apsel >> 24);
 111 }
 112
 113 /* Internal functions used in the module, partial transactions, use with caution */
 114 int dap_dp_write_reg(swjdp_common_t *swjdp, uint32_t value, uint8_t reg_addr);
 115 /* int swjdp_write_apacc(swjdp_common_t *swjdp, uint32_t value, uint8_t reg_addr); */
 116 int dap_dp_read_reg(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr);
 117 /* int swjdp_read_apacc(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr); */
 118 int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar);
 119 int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel);
 120
 121 int dap_ap_write_reg(swjdp_common_t *swjdp, uint32_t addr, uint8_t* out_buf);
 122 int dap_ap_write_reg_u32(swjdp_common_t *swjdp, uint32_t addr, uint32_t value);
 123 int dap_ap_read_reg(swjdp_common_t *swjdp, uint32_t addr, uint8_t *in_buf);
 124 int dap_ap_read_reg_u32(swjdp_common_t *swjdp, uint32_t addr, uint32_t *value);
 125
 126 /* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
 127 int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
 128
 129 /* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
 130 int mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value);
 131 int mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value);
 132
 133 /* MEM-AP memory mapped bus transfers, single registers, complete transactions */
 134 int mem_ap_read_atomic_u32(swjdp_common_t *swjdp,
 135                 uint32_t address, uint32_t *value);
 136 int mem_ap_write_atomic_u32(swjdp_common_t *swjdp,
 137                 uint32_t address, uint32_t value);
 138
 139 /* MEM-AP memory mapped bus block transfers */
 140 int mem_ap_read_buf_u8(swjdp_common_t *swjdp,
 141                 uint8_t *buffer, int count, uint32_t address);
 142 int mem_ap_read_buf_u16(swjdp_common_t *swjdp,
 143                 uint8_t *buffer, int count, uint32_t address);
 144 int mem_ap_read_buf_u32(swjdp_common_t *swjdp,
 145                 uint8_t *buffer, int count, uint32_t address);
 146
 147 int mem_ap_write_buf_u8(swjdp_common_t *swjdp,
 148                 uint8_t *buffer, int count, uint32_t address);
 149 int mem_ap_write_buf_u16(swjdp_common_t *swjdp,
 150                 uint8_t *buffer, int count, uint32_t address);
 151 int mem_ap_write_buf_u32(swjdp_common_t *swjdp,
 152                 uint8_t *buffer, int count, uint32_t address);
 153
 154 /* Initialisation of the debug system, power domains and registers */
 155 int ahbap_debugport_init(swjdp_common_t *swjdp);
 156
 157
 158 /* Commands for user dap access */
 159 int dap_info_command(struct command_context_s *cmd_ctx,
 160                 swjdp_common_t *swjdp, int apsel);
 161
 162 #define DAP_COMMAND_HANDLER(name) \
 163                 COMMAND_HELPER(name, swjdp_common_t *swjdp)
 164 DAP_COMMAND_HANDLER(dap_baseaddr_command);
 165 DAP_COMMAND_HANDLER(dap_memaccess_command);
 166 DAP_COMMAND_HANDLER(dap_apsel_command);
 167 DAP_COMMAND_HANDLER(dap_apid_command);
 168
 169 #endif