883ac8b5d8df582225eba60d1f67a14a00d09a43
[openocd.git] / src / target / arm_adi_v5.h
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
21
22 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
23 #define OPENOCD_TARGET_ARM_ADI_V5_H
24
25 /**
26 * @file
27 * This defines formats and data structures used to talk to ADIv5 entities.
28 * Those include a DAP, different types of Debug Port (DP), and memory mapped
29 * resources accessed through a MEM-AP.
30 */
31
32 #include <helper/list.h>
33 #include "arm_jtag.h"
34
35 /* three-bit ACK values for SWD access (sent LSB first) */
36 #define SWD_ACK_OK 0x1
37 #define SWD_ACK_WAIT 0x2
38 #define SWD_ACK_FAULT 0x4
39
40 #define DPAP_WRITE 0
41 #define DPAP_READ 1
42
43 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
44
45 /* A[3:0] for DP registers; A[1:0] are always zero.
46 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
47 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
48 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
49 */
50 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
51 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
52 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
53 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
54 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
55 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
56 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
57 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
58 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
59 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
60 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
61
62 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
63
64 /* Fields of the DP's AP ABORT register */
65 #define DAPABORT (1UL << 0)
66 #define STKCMPCLR (1UL << 1) /* SWD-only */
67 #define STKERRCLR (1UL << 2) /* SWD-only */
68 #define WDERRCLR (1UL << 3) /* SWD-only */
69 #define ORUNERRCLR (1UL << 4) /* SWD-only */
70
71 /* Fields of the DP's CTRL/STAT register */
72 #define CORUNDETECT (1UL << 0)
73 #define SSTICKYORUN (1UL << 1)
74 /* 3:2 - transaction mode (e.g. pushed compare) */
75 #define SSTICKYCMP (1UL << 4)
76 #define SSTICKYERR (1UL << 5)
77 #define READOK (1UL << 6) /* SWD-only */
78 #define WDATAERR (1UL << 7) /* SWD-only */
79 /* 11:8 - mask lanes for pushed compare or verify ops */
80 /* 21:12 - transaction counter */
81 #define CDBGRSTREQ (1UL << 26)
82 #define CDBGRSTACK (1UL << 27)
83 #define CDBGPWRUPREQ (1UL << 28)
84 #define CDBGPWRUPACK (1UL << 29)
85 #define CSYSPWRUPREQ (1UL << 30)
86 #define CSYSPWRUPACK (1UL << 31)
87
88 /* MEM-AP register addresses */
89 #define MEM_AP_REG_CSW 0x00
90 #define MEM_AP_REG_TAR 0x04
91 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
92 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
93 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
94 #define MEM_AP_REG_BD1 0x14
95 #define MEM_AP_REG_BD2 0x18
96 #define MEM_AP_REG_BD3 0x1C
97 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
98 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
99 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
100 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
101 /* Generic AP register address */
102 #define AP_REG_IDR 0xFC /* RO: Identification Register */
103
104 /* Fields of the MEM-AP's CSW register */
105 #define CSW_SIZE_MASK 7
106 #define CSW_8BIT 0
107 #define CSW_16BIT 1
108 #define CSW_32BIT 2
109 #define CSW_ADDRINC_MASK (3UL << 4)
110 #define CSW_ADDRINC_OFF 0UL
111 #define CSW_ADDRINC_SINGLE (1UL << 4)
112 #define CSW_ADDRINC_PACKED (2UL << 4)
113 #define CSW_DEVICE_EN (1UL << 6)
114 #define CSW_TRIN_PROG (1UL << 7)
115 /* all fields in bits 12 and above are implementation-defined! */
116 #define CSW_SPIDEN (1UL << 23)
117 #define CSW_HPROT1 (1UL << 25) /* AHB: Privileged */
118 #define CSW_MASTER_DEBUG (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */
119 #define CSW_SPROT (1UL << 30)
120 #define CSW_DBGSWENABLE (1UL << 31)
121
122 /* initial value of csw_default used for MEM-AP transfers */
123 #define CSW_DEFAULT (CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE)
124
125 /* Fields of the MEM-AP's IDR register */
126 #define IDR_REV (0xFUL << 28)
127 #define IDR_JEP106 (0x7FFUL << 17)
128 #define IDR_CLASS (0xFUL << 13)
129 #define IDR_VARIANT (0xFUL << 4)
130 #define IDR_TYPE (0xFUL << 0)
131
132 #define IDR_JEP106_ARM 0x04760000
133
134 #define DP_SELECT_APSEL 0xFF000000
135 #define DP_SELECT_APBANK 0x000000F0
136 #define DP_SELECT_DPBANK 0x0000000F
137 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
138
139 /**
140 * This represents an ARM Debug Interface (v5) Access Port (AP).
141 * Most common is a MEM-AP, for memory access.
142 */
143 struct adiv5_ap {
144 /**
145 * DAP this AP belongs to.
146 */
147 struct adiv5_dap *dap;
148
149 /**
150 * Number of this AP.
151 */
152 uint8_t ap_num;
153
154 /**
155 * Default value for (MEM-AP) AP_REG_CSW register.
156 */
157 uint32_t csw_default;
158
159 /**
160 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
161 * configure an access mode, such as autoincrementing AP_REG_TAR during
162 * word access. "-1" indicates no cached value.
163 */
164 uint32_t csw_value;
165
166 /**
167 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
168 * configure the address being read or written
169 * "-1" indicates no cached value.
170 */
171 uint32_t tar_value;
172
173 /**
174 * Configures how many extra tck clocks are added after starting a
175 * MEM-AP access before we try to read its status (and/or result).
176 */
177 uint32_t memaccess_tck;
178
179 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
180 uint32_t tar_autoincr_block;
181
182 /* true if packed transfers are supported by the MEM-AP */
183 bool packed_transfers;
184
185 /* true if unaligned memory access is not supported by the MEM-AP */
186 bool unaligned_access_bad;
187
188 /* true if tar_value is in sync with TAR register */
189 bool tar_valid;
190 };
191
192
193 /**
194 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
195 * A DAP has two types of component: one Debug Port (DP), which is a
196 * transport agent; and at least one Access Port (AP), controlling
197 * resource access.
198 *
199 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
200 * Accordingly, this interface is responsible for hiding the transport
201 * differences so upper layer code can largely ignore them.
202 *
203 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
204 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
205 * a choice made at board design time (by only using the SWD pins), or
206 * as part of setting up a debug session (if all the dual-role JTAG/SWD
207 * signals are available).
208 */
209 struct adiv5_dap {
210 const struct dap_ops *ops;
211
212 /* dap transaction list for WAIT support */
213 struct list_head cmd_journal;
214
215 struct jtag_tap *tap;
216 /* Control config */
217 uint32_t dp_ctrl_stat;
218
219 struct adiv5_ap ap[256];
220
221 /* The current manually selected AP by the "dap apsel" command */
222 uint32_t apsel;
223
224 /**
225 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
226 * indicates no cached value and forces rewrite of the register.
227 */
228 uint32_t select;
229
230 /* information about current pending SWjDP-AHBAP transaction */
231 uint8_t ack;
232
233 /**
234 * Holds the pointer to the destination word for the last queued read,
235 * for use with posted AP read sequence optimization.
236 */
237 uint32_t *last_read;
238
239 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
240 * despite lack of support in the ARMv7 architecture. Memory access through
241 * the AHB-AP has strange byte ordering these processors, and we need to
242 * swizzle appropriately. */
243 bool ti_be_32_quirks;
244
245 /**
246 * Signals that an attempt to reestablish communication afresh
247 * should be performed before the next access.
248 */
249 bool do_reconnect;
250
251 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
252 * do not set this bit until later in the bringup sequence */
253 bool ignore_syspwrupack;
254 };
255
256 /**
257 * Transport-neutral representation of queued DAP transactions, supporting
258 * both JTAG and SWD transports. All submitted transactions are logically
259 * queued, until the queue is executed by run(). Some implementations might
260 * execute transactions as soon as they're submitted, but no status is made
261 * available until run().
262 */
263 struct dap_ops {
264 /** connect operation for SWD */
265 int (*connect)(struct adiv5_dap *dap);
266 /** DP register read. */
267 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
268 uint32_t *data);
269 /** DP register write. */
270 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
271 uint32_t data);
272
273 /** AP register read. */
274 int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
275 uint32_t *data);
276 /** AP register write. */
277 int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
278 uint32_t data);
279
280 /** AP operation abort. */
281 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
282
283 /** Executes all queued DAP operations. */
284 int (*run)(struct adiv5_dap *dap);
285
286 /** Executes all queued DAP operations but doesn't check
287 * sticky error conditions */
288 int (*sync)(struct adiv5_dap *dap);
289
290 /** Optional; called at OpenOCD exit */
291 void (*quit)(struct adiv5_dap *dap);
292 };
293
294 /*
295 * Access Port classes
296 */
297 enum ap_class {
298 AP_CLASS_NONE = 0x00000, /* No class defined */
299 AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */
300 };
301
302 /*
303 * Access Port types
304 */
305 enum ap_type {
306 AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
307 AP_TYPE_AHB_AP = 0x1, /* AHB Memory-AP */
308 AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */
309 AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
310 };
311
312 /**
313 * Queue a DP register read.
314 * Note that not all DP registers are readable; also, that JTAG and SWD
315 * have slight differences in DP register support.
316 *
317 * @param dap The DAP used for reading.
318 * @param reg The two-bit number of the DP register being read.
319 * @param data Pointer saying where to store the register's value
320 * (in host endianness).
321 *
322 * @return ERROR_OK for success, else a fault code.
323 */
324 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
325 unsigned reg, uint32_t *data)
326 {
327 assert(dap->ops != NULL);
328 return dap->ops->queue_dp_read(dap, reg, data);
329 }
330
331 /**
332 * Queue a DP register write.
333 * Note that not all DP registers are writable; also, that JTAG and SWD
334 * have slight differences in DP register support.
335 *
336 * @param dap The DAP used for writing.
337 * @param reg The two-bit number of the DP register being written.
338 * @param data Value being written (host endianness)
339 *
340 * @return ERROR_OK for success, else a fault code.
341 */
342 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
343 unsigned reg, uint32_t data)
344 {
345 assert(dap->ops != NULL);
346 return dap->ops->queue_dp_write(dap, reg, data);
347 }
348
349 /**
350 * Queue an AP register read.
351 *
352 * @param ap The AP used for reading.
353 * @param reg The number of the AP register being read.
354 * @param data Pointer saying where to store the register's value
355 * (in host endianness).
356 *
357 * @return ERROR_OK for success, else a fault code.
358 */
359 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
360 unsigned reg, uint32_t *data)
361 {
362 assert(ap->dap->ops != NULL);
363 return ap->dap->ops->queue_ap_read(ap, reg, data);
364 }
365
366 /**
367 * Queue an AP register write.
368 *
369 * @param ap The AP used for writing.
370 * @param reg The number of the AP register being written.
371 * @param data Value being written (host endianness)
372 *
373 * @return ERROR_OK for success, else a fault code.
374 */
375 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
376 unsigned reg, uint32_t data)
377 {
378 assert(ap->dap->ops != NULL);
379 return ap->dap->ops->queue_ap_write(ap, reg, data);
380 }
381
382 /**
383 * Queue an AP abort operation. The current AP transaction is aborted,
384 * including any update of the transaction counter. The AP is left in
385 * an unknown state (so it must be re-initialized). For use only after
386 * the AP has reported WAIT status for an extended period.
387 *
388 * @param dap The DAP used for writing.
389 * @param ack Pointer to where transaction status will be stored.
390 *
391 * @return ERROR_OK for success, else a fault code.
392 */
393 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
394 {
395 assert(dap->ops != NULL);
396 return dap->ops->queue_ap_abort(dap, ack);
397 }
398
399 /**
400 * Perform all queued DAP operations, and clear any errors posted in the
401 * CTRL_STAT register when they are done. Note that if more than one AP
402 * operation will be queued, one of the first operations in the queue
403 * should probably enable CORUNDETECT in the CTRL/STAT register.
404 *
405 * @param dap The DAP used.
406 *
407 * @return ERROR_OK for success, else a fault code.
408 */
409 static inline int dap_run(struct adiv5_dap *dap)
410 {
411 assert(dap->ops != NULL);
412 return dap->ops->run(dap);
413 }
414
415 static inline int dap_sync(struct adiv5_dap *dap)
416 {
417 assert(dap->ops != NULL);
418 if (dap->ops->sync)
419 return dap->ops->sync(dap);
420 return ERROR_OK;
421 }
422
423 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
424 uint32_t *value)
425 {
426 int retval;
427
428 retval = dap_queue_dp_read(dap, reg, value);
429 if (retval != ERROR_OK)
430 return retval;
431
432 return dap_run(dap);
433 }
434
435 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
436 uint32_t mask, uint32_t value, int timeout)
437 {
438 assert(timeout > 0);
439 assert((value & mask) == value);
440
441 int ret;
442 uint32_t regval;
443 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
444 reg, mask, value);
445 do {
446 ret = dap_dp_read_atomic(dap, reg, &regval);
447 if (ret != ERROR_OK)
448 return ret;
449
450 if ((regval & mask) == value)
451 break;
452
453 alive_sleep(10);
454 } while (--timeout);
455
456 if (!timeout) {
457 LOG_DEBUG("DAP: poll %x timeout", reg);
458 return ERROR_WAIT;
459 } else {
460 return ERROR_OK;
461 }
462 }
463
464 /* Queued MEM-AP memory mapped single word transfers. */
465 int mem_ap_read_u32(struct adiv5_ap *ap,
466 uint32_t address, uint32_t *value);
467 int mem_ap_write_u32(struct adiv5_ap *ap,
468 uint32_t address, uint32_t value);
469
470 /* Synchronous MEM-AP memory mapped single word transfers. */
471 int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
472 uint32_t address, uint32_t *value);
473 int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
474 uint32_t address, uint32_t value);
475
476 /* Synchronous MEM-AP memory mapped bus block transfers. */
477 int mem_ap_read_buf(struct adiv5_ap *ap,
478 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
479 int mem_ap_write_buf(struct adiv5_ap *ap,
480 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
481
482 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
483 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
484 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
485 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
486 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
487
488 /* Initialisation of the debug system, power domains and registers */
489 int dap_dp_init(struct adiv5_dap *dap);
490 int mem_ap_init(struct adiv5_ap *ap);
491
492 /* Invalidate cached DP select and cached TAR and CSW of all APs */
493 void dap_invalidate_cache(struct adiv5_dap *dap);
494
495 /* Probe the AP for ROM Table location */
496 int dap_get_debugbase(struct adiv5_ap *ap,
497 uint32_t *dbgbase, uint32_t *apid);
498
499 /* Probe Access Ports to find a particular type */
500 int dap_find_ap(struct adiv5_dap *dap,
501 enum ap_type type_to_find,
502 struct adiv5_ap **ap_out);
503
504 static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
505 {
506 return &dap->ap[ap_num];
507 }
508
509 /* Lookup CoreSight component */
510 int dap_lookup_cs_component(struct adiv5_ap *ap,
511 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
512
513 struct target;
514
515 /* Put debug link into SWD mode */
516 int dap_to_swd(struct target *target);
517
518 /* Put debug link into JTAG mode */
519 int dap_to_jtag(struct target *target);
520
521 extern const struct command_registration dap_instance_commands[];
522
523 struct arm_dap_object;
524 extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o);
525 extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj);
526 extern int dap_info_command(struct command_context *cmd_ctx,
527 struct adiv5_ap *ap);
528 extern int dap_register_commands(struct command_context *cmd_ctx);
529 extern const char *adiv5_dap_name(struct adiv5_dap *self);
530 extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self);
531 extern int dap_cleanup_all(void);
532
533 struct adiv5_private_config {
534 int ap_num;
535 struct adiv5_dap *dap;
536 };
537
538 extern int adiv5_verify_config(struct adiv5_private_config *pc);
539 extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi);
540
541 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */