37b7771231b2fa70d65dbbad796d55ec83a4e03b
[openocd.git] / src / target / arm_adi_v5.h
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23
24 #ifndef ARM_ADI_V5_H
25 #define ARM_ADI_V5_H
26
27 /**
28 * @file
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
32 */
33
34 #include "arm_jtag.h"
35
36 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
37 * is no longer JTAG-specific
38 */
39 #define JTAG_DP_DPACC 0xA
40 #define JTAG_DP_APACC 0xB
41
42 /* three-bit ACK values for SWD access (sent LSB first) */
43 #define SWD_ACK_OK 0x4
44 #define SWD_ACK_WAIT 0x2
45 #define SWD_ACK_FAULT 0x1
46
47 #define DPAP_WRITE 0
48 #define DPAP_READ 1
49
50 /* A[3:0] for DP registers; A[1:0] are always zero.
51 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
52 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
53 * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
54 */
55 #define DP_IDCODE 0 /* SWD: read */
56 #define DP_ABORT 0 /* SWD: write */
57 #define DP_CTRL_STAT 0x4 /* r/w */
58 #define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */
59 #define DP_RESEND 0x8 /* SWD: read */
60 #define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */
61 #define DP_RDBUFF 0xC /* read-only */
62
63 #define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8)) /* 1..4 clocks */
64 #define WCR_TO_PRESCALE(wcr) (7 & ((wcr))) /* impl defined */
65
66 /* Fields of the DP's AP ABORT register */
67 #define DAPABORT (1 << 0)
68 #define STKCMPCLR (1 << 1) /* SWD-only */
69 #define STKERRCLR (1 << 2) /* SWD-only */
70 #define WDERRCLR (1 << 3) /* SWD-only */
71 #define ORUNERRCLR (1 << 4) /* SWD-only */
72
73 /* Fields of the DP's CTRL/STAT register */
74 #define CORUNDETECT (1 << 0)
75 #define SSTICKYORUN (1 << 1)
76 /* 3:2 - transaction mode (e.g. pushed compare) */
77 #define SSTICKYCMP (1 << 4)
78 #define SSTICKYERR (1 << 5)
79 #define READOK (1 << 6) /* SWD-only */
80 #define WDATAERR (1 << 7) /* SWD-only */
81 /* 11:8 - mask lanes for pushed compare or verify ops */
82 /* 21:12 - transaction counter */
83 #define CDBGRSTREQ (1 << 26)
84 #define CDBGRSTACK (1 << 27)
85 #define CDBGPWRUPREQ (1 << 28)
86 #define CDBGPWRUPACK (1 << 29)
87 #define CSYSPWRUPREQ (1 << 30)
88 #define CSYSPWRUPACK (1 << 31)
89
90 /* MEM-AP register addresses */
91 /* TODO: rename as MEM_AP_REG_* */
92 #define AP_REG_CSW 0x00
93 #define AP_REG_TAR 0x04
94 #define AP_REG_DRW 0x0C
95 #define AP_REG_BD0 0x10
96 #define AP_REG_BD1 0x14
97 #define AP_REG_BD2 0x18
98 #define AP_REG_BD3 0x1C
99 #define AP_REG_CFG 0xF4 /* big endian? */
100 #define AP_REG_BASE 0xF8
101
102 /* Generic AP register address */
103 #define AP_REG_IDR 0xFC
104
105 /* Fields of the MEM-AP's CSW register */
106 #define CSW_8BIT 0
107 #define CSW_16BIT 1
108 #define CSW_32BIT 2
109 #define CSW_ADDRINC_MASK (3 << 4)
110 #define CSW_ADDRINC_OFF 0
111 #define CSW_ADDRINC_SINGLE (1 << 4)
112 #define CSW_ADDRINC_PACKED (2 << 4)
113 #define CSW_DEVICE_EN (1 << 6)
114 #define CSW_TRIN_PROG (1 << 7)
115 #define CSW_SPIDEN (1 << 23)
116 /* 30:24 - implementation-defined! */
117 #define CSW_HPROT (1 << 25) /* ? */
118 #define CSW_MASTER_DEBUG (1 << 29) /* ? */
119 #define CSW_DBGSWENABLE (1 << 31)
120
121 /**
122 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
123 * A DAP has two types of component: one Debug Port (DP), which is a
124 * transport agent; and at least one Access Port (AP), controlling
125 * resource access. Most common is a MEM-AP, for memory access.
126 *
127 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
128 * Accordingly, this interface is responsible for hiding the transport
129 * differences so upper layer code can largely ignore them.
130 *
131 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
132 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
133 * a choice made at board design time (by only using the SWD pins), or
134 * as part of setting up a debug session (if all the dual-role JTAG/SWD
135 * signals are available).
136 */
137 struct adiv5_dap {
138 const struct dap_ops *ops;
139
140 struct arm_jtag *jtag_info;
141 /* Control config */
142 uint32_t dp_ctrl_stat;
143
144 uint32_t apsel;
145
146 /**
147 * Cache for DP_SELECT bits identifying the current AP. A DAP may
148 * connect to multiple APs, such as one MEM-AP for general access,
149 * another reserved for accessing debug modules, and a JTAG-DP.
150 * "-1" indicates no cached value.
151 */
152 uint32_t ap_current;
153
154 /**
155 * Cache for DP_SELECT bits identifying the current four-word AP
156 * register bank. This caches AP register addresss bits 7:4; JTAG
157 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
158 * "-1" indicates no cached value.
159 */
160 uint32_t ap_bank_value;
161
162 /**
163 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
164 * configure an access mode, such as autoincrementing AP_REG_TAR during
165 * word access. "-1" indicates no cached value.
166 */
167 uint32_t ap_csw_value;
168
169 /**
170 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
171 * configure the address being read or written
172 * "-1" indicates no cached value.
173 */
174 uint32_t ap_tar_value;
175
176 /* information about current pending SWjDP-AHBAP transaction */
177 uint8_t ack;
178
179 /**
180 * Configures how many extra tck clocks are added after starting a
181 * MEM-AP access before we try to read its status (and/or result).
182 */
183 uint32_t memaccess_tck;
184
185 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
186 uint32_t tar_autoincr_block;
187 };
188
189 /**
190 * Transport-neutral representation of queued DAP transactions, supporting
191 * both JTAG and SWD transports. All submitted transactions are logically
192 * queued, until the queue is executed by run(). Some implementations might
193 * execute transactions as soon as they're submitted, but no status is made
194 * availablue until run().
195 */
196 struct dap_ops {
197 /** If the DAP transport isn't SWD, it must be JTAG. Upper level
198 * code may need to care about the difference in some cases.
199 */
200 bool is_swd;
201
202 /** Reads the DAP's IDCODe register. */
203 int (*queue_idcode_read)(struct adiv5_dap *dap,
204 uint8_t *ack, uint32_t *data);
205
206 /** DP register read. */
207 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
208 uint32_t *data);
209 /** DP register write. */
210 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
211 uint32_t data);
212
213 /** AP register read. */
214 int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
215 uint32_t *data);
216 /** AP register write. */
217 int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
218 uint32_t data);
219
220 /** AP operation abort. */
221 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
222
223 /** Executes all queued DAP operations. */
224 int (*run)(struct adiv5_dap *dap);
225 };
226
227 /**
228 * Queue an IDCODE register read. This is primarily useful for SWD
229 * transports, where it is required as part of link initialization.
230 * (For JTAG, this register is read as part of scan chain setup.)
231 *
232 * @param dap The DAP used for reading.
233 * @param ack Pointer to where transaction status will be stored.
234 * @param data Pointer saying where to store the IDCODE value.
235 *
236 * @return ERROR_OK for success, else a fault code.
237 */
238 static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
239 uint8_t *ack, uint32_t *data)
240 {
241 assert(dap->ops != NULL);
242 return dap->ops->queue_idcode_read(dap, ack, data);
243 }
244
245 /**
246 * Queue a DP register read.
247 * Note that not all DP registers are readable; also, that JTAG and SWD
248 * have slight differences in DP register support.
249 *
250 * @param dap The DAP used for reading.
251 * @param reg The two-bit number of the DP register being read.
252 * @param data Pointer saying where to store the register's value
253 * (in host endianness).
254 *
255 * @return ERROR_OK for success, else a fault code.
256 */
257 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
258 unsigned reg, uint32_t *data)
259 {
260 assert(dap->ops != NULL);
261 return dap->ops->queue_dp_read(dap, reg, data);
262 }
263
264 /**
265 * Queue a DP register write.
266 * Note that not all DP registers are writable; also, that JTAG and SWD
267 * have slight differences in DP register support.
268 *
269 * @param dap The DAP used for writing.
270 * @param reg The two-bit number of the DP register being written.
271 * @param data Value being written (host endianness)
272 *
273 * @return ERROR_OK for success, else a fault code.
274 */
275 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
276 unsigned reg, uint32_t data)
277 {
278 assert(dap->ops != NULL);
279 return dap->ops->queue_dp_write(dap, reg, data);
280 }
281
282 /**
283 * Queue an AP register read.
284 *
285 * @param dap The DAP used for reading.
286 * @param reg The number of the AP register being read.
287 * @param data Pointer saying where to store the register's value
288 * (in host endianness).
289 *
290 * @return ERROR_OK for success, else a fault code.
291 */
292 static inline int dap_queue_ap_read(struct adiv5_dap *dap,
293 unsigned reg, uint32_t *data)
294 {
295 assert(dap->ops != NULL);
296 return dap->ops->queue_ap_read(dap, reg, data);
297 }
298
299 /**
300 * Queue an AP register write.
301 *
302 * @param dap The DAP used for writing.
303 * @param reg The number of the AP register being written.
304 * @param data Value being written (host endianness)
305 *
306 * @return ERROR_OK for success, else a fault code.
307 */
308 static inline int dap_queue_ap_write(struct adiv5_dap *dap,
309 unsigned reg, uint32_t data)
310 {
311 assert(dap->ops != NULL);
312 return dap->ops->queue_ap_write(dap, reg, data);
313 }
314
315 /**
316 * Queue an AP abort operation. The current AP transaction is aborted,
317 * including any update of the transaction counter. The AP is left in
318 * an unknown state (so it must be re-initialized). For use only after
319 * the AP has reported WAIT status for an extended period.
320 *
321 * @param dap The DAP used for writing.
322 * @param ack Pointer to where transaction status will be stored.
323 *
324 * @return ERROR_OK for success, else a fault code.
325 */
326 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
327 {
328 assert(dap->ops != NULL);
329 return dap->ops->queue_ap_abort(dap, ack);
330 }
331
332 /**
333 * Perform all queued DAP operations, and clear any errors posted in the
334 * CTRL_STAT register when they are done. Note that if more than one AP
335 * operation will be queued, one of the first operations in the queue
336 * should probably enable CORUNDETECT in the CTRL/STAT register.
337 *
338 * @param dap The DAP used.
339 *
340 * @return ERROR_OK for success, else a fault code.
341 */
342 static inline int dap_run(struct adiv5_dap *dap)
343 {
344 assert(dap->ops != NULL);
345 return dap->ops->run(dap);
346 }
347
348 /** Accessor for currently selected DAP-AP number (0..255) */
349 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
350 {
351 return (uint8_t)(swjdp->ap_current >> 24);
352 }
353
354 /* AP selection applies to future AP transactions */
355 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
356
357 /* Queued AP transactions */
358 int dap_setup_accessport(struct adiv5_dap *swjdp,
359 uint32_t csw, uint32_t tar);
360
361 /* Queued MEM-AP memory mapped single word transfers */
362 int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
363 int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
364
365 /* Synchronous MEM-AP memory mapped single word transfers */
366 int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
367 uint32_t address, uint32_t *value);
368 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
369 uint32_t address, uint32_t value);
370
371 /* MEM-AP memory mapped bus block transfers */
372 int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
373 uint8_t *buffer, int count, uint32_t address);
374 int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
375 uint8_t *buffer, int count, uint32_t address);
376 int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
377 uint8_t *buffer, int count, uint32_t address);
378
379 int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
380 const uint8_t *buffer, int count, uint32_t address);
381 int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
382 const uint8_t *buffer, int count, uint32_t address);
383 int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
384 const uint8_t *buffer, int count, uint32_t address);
385
386 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
387 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
388 uint32_t address, uint32_t *value);
389 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
390 uint32_t address, uint32_t value);
391
392 /* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
393 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
394 uint32_t address, uint32_t *value);
395 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
396 uint32_t address, uint32_t value);
397
398 /* MEM-AP memory mapped bus block transfers with selection of ap */
399 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
400 uint8_t *buffer, int count, uint32_t address);
401 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
402 uint8_t *buffer, int count, uint32_t address);
403 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
404 uint8_t *buffer, int count, uint32_t address);
405
406 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
407 const uint8_t *buffer, int count, uint32_t address);
408 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
409 const uint8_t *buffer, int count, uint32_t address);
410 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
411 const uint8_t *buffer, int count, uint32_t address);
412
413 /* Initialisation of the debug system, power domains and registers */
414 int ahbap_debugport_init(struct adiv5_dap *swjdp);
415
416 /* Probe the AP for ROM Table location */
417 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
418 uint32_t *dbgbase, uint32_t *apid);
419
420 /* Lookup CoreSight component */
421 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
422 uint32_t dbgbase, uint8_t type, uint32_t *addr);
423
424 struct target;
425
426 /* Put debug link into SWD mode */
427 int dap_to_swd(struct target *target);
428
429 /* Put debug link into JTAG mode */
430 int dap_to_jtag(struct target *target);
431
432 extern const struct command_registration dap_command_handlers[];
433
434 #endif