target/arm_adi_v5: change prototype of dap_rom_display()
[openocd.git] / src / target / arm_adi_v5.h
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
21
22 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
23 #define OPENOCD_TARGET_ARM_ADI_V5_H
24
25 /**
26 * @file
27 * This defines formats and data structures used to talk to ADIv5 entities.
28 * Those include a DAP, different types of Debug Port (DP), and memory mapped
29 * resources accessed through a MEM-AP.
30 */
31
32 #include <helper/list.h>
33 #include "arm_jtag.h"
34
35 /* three-bit ACK values for SWD access (sent LSB first) */
36 #define SWD_ACK_OK 0x1
37 #define SWD_ACK_WAIT 0x2
38 #define SWD_ACK_FAULT 0x4
39
40 #define DPAP_WRITE 0
41 #define DPAP_READ 1
42
43 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
44
45 /* A[3:0] for DP registers; A[1:0] are always zero.
46 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
47 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
48 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
49 */
50 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
51 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
52 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
53 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
54 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
55 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
56 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
57 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
58 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
59 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
60 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
61
62 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
63
64 /* Fields of the DP's AP ABORT register */
65 #define DAPABORT (1UL << 0)
66 #define STKCMPCLR (1UL << 1) /* SWD-only */
67 #define STKERRCLR (1UL << 2) /* SWD-only */
68 #define WDERRCLR (1UL << 3) /* SWD-only */
69 #define ORUNERRCLR (1UL << 4) /* SWD-only */
70
71 /* Fields of the DP's CTRL/STAT register */
72 #define CORUNDETECT (1UL << 0)
73 #define SSTICKYORUN (1UL << 1)
74 /* 3:2 - transaction mode (e.g. pushed compare) */
75 #define SSTICKYCMP (1UL << 4)
76 #define SSTICKYERR (1UL << 5)
77 #define READOK (1UL << 6) /* SWD-only */
78 #define WDATAERR (1UL << 7) /* SWD-only */
79 /* 11:8 - mask lanes for pushed compare or verify ops */
80 /* 21:12 - transaction counter */
81 #define CDBGRSTREQ (1UL << 26)
82 #define CDBGRSTACK (1UL << 27)
83 #define CDBGPWRUPREQ (1UL << 28)
84 #define CDBGPWRUPACK (1UL << 29)
85 #define CSYSPWRUPREQ (1UL << 30)
86 #define CSYSPWRUPACK (1UL << 31)
87
88 /* MEM-AP register addresses */
89 #define MEM_AP_REG_CSW 0x00
90 #define MEM_AP_REG_TAR 0x04
91 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
92 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
93 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
94 #define MEM_AP_REG_BD1 0x14
95 #define MEM_AP_REG_BD2 0x18
96 #define MEM_AP_REG_BD3 0x1C
97 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
98 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
99 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
100 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
101 /* Generic AP register address */
102 #define AP_REG_IDR 0xFC /* RO: Identification Register */
103
104 /* Fields of the MEM-AP's CSW register */
105 #define CSW_SIZE_MASK 7
106 #define CSW_8BIT 0
107 #define CSW_16BIT 1
108 #define CSW_32BIT 2
109 #define CSW_ADDRINC_MASK (3UL << 4)
110 #define CSW_ADDRINC_OFF 0UL
111 #define CSW_ADDRINC_SINGLE (1UL << 4)
112 #define CSW_ADDRINC_PACKED (2UL << 4)
113 #define CSW_DEVICE_EN (1UL << 6)
114 #define CSW_TRIN_PROG (1UL << 7)
115 /* all fields in bits 12 and above are implementation-defined! */
116 #define CSW_SPIDEN (1UL << 23)
117 #define CSW_HPROT1 (1UL << 25) /* AHB: Privileged */
118 #define CSW_MASTER_DEBUG (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */
119 #define CSW_SPROT (1UL << 30)
120 #define CSW_DBGSWENABLE (1UL << 31)
121
122 /* initial value of csw_default used for MEM-AP transfers */
123 #define CSW_DEFAULT (CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE)
124
125 /* Fields of the MEM-AP's IDR register */
126 #define IDR_REV (0xFUL << 28)
127 #define IDR_JEP106 (0x7FFUL << 17)
128 #define IDR_CLASS (0xFUL << 13)
129 #define IDR_VARIANT (0xFUL << 4)
130 #define IDR_TYPE (0xFUL << 0)
131
132 #define IDR_JEP106_ARM 0x04760000
133
134 #define DP_SELECT_APSEL 0xFF000000
135 #define DP_SELECT_APBANK 0x000000F0
136 #define DP_SELECT_DPBANK 0x0000000F
137 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
138
139 #define DP_APSEL_MAX (255)
140 #define DP_APSEL_INVALID (-1)
141
142 /**
143 * This represents an ARM Debug Interface (v5) Access Port (AP).
144 * Most common is a MEM-AP, for memory access.
145 */
146 struct adiv5_ap {
147 /**
148 * DAP this AP belongs to.
149 */
150 struct adiv5_dap *dap;
151
152 /**
153 * Number of this AP.
154 */
155 uint8_t ap_num;
156
157 /**
158 * Default value for (MEM-AP) AP_REG_CSW register.
159 */
160 uint32_t csw_default;
161
162 /**
163 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
164 * configure an access mode, such as autoincrementing AP_REG_TAR during
165 * word access. "-1" indicates no cached value.
166 */
167 uint32_t csw_value;
168
169 /**
170 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
171 * configure the address being read or written
172 * "-1" indicates no cached value.
173 */
174 uint32_t tar_value;
175
176 /**
177 * Configures how many extra tck clocks are added after starting a
178 * MEM-AP access before we try to read its status (and/or result).
179 */
180 uint32_t memaccess_tck;
181
182 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
183 uint32_t tar_autoincr_block;
184
185 /* true if packed transfers are supported by the MEM-AP */
186 bool packed_transfers;
187
188 /* true if unaligned memory access is not supported by the MEM-AP */
189 bool unaligned_access_bad;
190
191 /* true if tar_value is in sync with TAR register */
192 bool tar_valid;
193 };
194
195
196 /**
197 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
198 * A DAP has two types of component: one Debug Port (DP), which is a
199 * transport agent; and at least one Access Port (AP), controlling
200 * resource access.
201 *
202 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
203 * Accordingly, this interface is responsible for hiding the transport
204 * differences so upper layer code can largely ignore them.
205 *
206 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
207 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
208 * a choice made at board design time (by only using the SWD pins), or
209 * as part of setting up a debug session (if all the dual-role JTAG/SWD
210 * signals are available).
211 */
212 struct adiv5_dap {
213 const struct dap_ops *ops;
214
215 /* dap transaction list for WAIT support */
216 struct list_head cmd_journal;
217
218 struct jtag_tap *tap;
219 /* Control config */
220 uint32_t dp_ctrl_stat;
221
222 struct adiv5_ap ap[256];
223
224 /* The current manually selected AP by the "dap apsel" command */
225 uint32_t apsel;
226
227 /**
228 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
229 * indicates no cached value and forces rewrite of the register.
230 */
231 uint32_t select;
232
233 /* information about current pending SWjDP-AHBAP transaction */
234 uint8_t ack;
235
236 /**
237 * Holds the pointer to the destination word for the last queued read,
238 * for use with posted AP read sequence optimization.
239 */
240 uint32_t *last_read;
241
242 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
243 * despite lack of support in the ARMv7 architecture. Memory access through
244 * the AHB-AP has strange byte ordering these processors, and we need to
245 * swizzle appropriately. */
246 bool ti_be_32_quirks;
247
248 /**
249 * Signals that an attempt to reestablish communication afresh
250 * should be performed before the next access.
251 */
252 bool do_reconnect;
253
254 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
255 * do not set this bit until later in the bringup sequence */
256 bool ignore_syspwrupack;
257 };
258
259 /**
260 * Transport-neutral representation of queued DAP transactions, supporting
261 * both JTAG and SWD transports. All submitted transactions are logically
262 * queued, until the queue is executed by run(). Some implementations might
263 * execute transactions as soon as they're submitted, but no status is made
264 * available until run().
265 */
266 struct dap_ops {
267 /** connect operation for SWD */
268 int (*connect)(struct adiv5_dap *dap);
269 /** DP register read. */
270 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
271 uint32_t *data);
272 /** DP register write. */
273 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
274 uint32_t data);
275
276 /** AP register read. */
277 int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
278 uint32_t *data);
279 /** AP register write. */
280 int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
281 uint32_t data);
282
283 /** AP operation abort. */
284 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
285
286 /** Executes all queued DAP operations. */
287 int (*run)(struct adiv5_dap *dap);
288
289 /** Executes all queued DAP operations but doesn't check
290 * sticky error conditions */
291 int (*sync)(struct adiv5_dap *dap);
292
293 /** Optional; called at OpenOCD exit */
294 void (*quit)(struct adiv5_dap *dap);
295 };
296
297 /*
298 * Access Port classes
299 */
300 enum ap_class {
301 AP_CLASS_NONE = 0x00000, /* No class defined */
302 AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */
303 };
304
305 /*
306 * Access Port types
307 */
308 enum ap_type {
309 AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
310 AP_TYPE_AHB_AP = 0x1, /* AHB Memory-AP */
311 AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */
312 AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
313 };
314
315 /**
316 * Queue a DP register read.
317 * Note that not all DP registers are readable; also, that JTAG and SWD
318 * have slight differences in DP register support.
319 *
320 * @param dap The DAP used for reading.
321 * @param reg The two-bit number of the DP register being read.
322 * @param data Pointer saying where to store the register's value
323 * (in host endianness).
324 *
325 * @return ERROR_OK for success, else a fault code.
326 */
327 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
328 unsigned reg, uint32_t *data)
329 {
330 assert(dap->ops != NULL);
331 return dap->ops->queue_dp_read(dap, reg, data);
332 }
333
334 /**
335 * Queue a DP register write.
336 * Note that not all DP registers are writable; also, that JTAG and SWD
337 * have slight differences in DP register support.
338 *
339 * @param dap The DAP used for writing.
340 * @param reg The two-bit number of the DP register being written.
341 * @param data Value being written (host endianness)
342 *
343 * @return ERROR_OK for success, else a fault code.
344 */
345 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
346 unsigned reg, uint32_t data)
347 {
348 assert(dap->ops != NULL);
349 return dap->ops->queue_dp_write(dap, reg, data);
350 }
351
352 /**
353 * Queue an AP register read.
354 *
355 * @param ap The AP used for reading.
356 * @param reg The number of the AP register being read.
357 * @param data Pointer saying where to store the register's value
358 * (in host endianness).
359 *
360 * @return ERROR_OK for success, else a fault code.
361 */
362 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
363 unsigned reg, uint32_t *data)
364 {
365 assert(ap->dap->ops != NULL);
366 return ap->dap->ops->queue_ap_read(ap, reg, data);
367 }
368
369 /**
370 * Queue an AP register write.
371 *
372 * @param ap The AP used for writing.
373 * @param reg The number of the AP register being written.
374 * @param data Value being written (host endianness)
375 *
376 * @return ERROR_OK for success, else a fault code.
377 */
378 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
379 unsigned reg, uint32_t data)
380 {
381 assert(ap->dap->ops != NULL);
382 return ap->dap->ops->queue_ap_write(ap, reg, data);
383 }
384
385 /**
386 * Queue an AP abort operation. The current AP transaction is aborted,
387 * including any update of the transaction counter. The AP is left in
388 * an unknown state (so it must be re-initialized). For use only after
389 * the AP has reported WAIT status for an extended period.
390 *
391 * @param dap The DAP used for writing.
392 * @param ack Pointer to where transaction status will be stored.
393 *
394 * @return ERROR_OK for success, else a fault code.
395 */
396 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
397 {
398 assert(dap->ops != NULL);
399 return dap->ops->queue_ap_abort(dap, ack);
400 }
401
402 /**
403 * Perform all queued DAP operations, and clear any errors posted in the
404 * CTRL_STAT register when they are done. Note that if more than one AP
405 * operation will be queued, one of the first operations in the queue
406 * should probably enable CORUNDETECT in the CTRL/STAT register.
407 *
408 * @param dap The DAP used.
409 *
410 * @return ERROR_OK for success, else a fault code.
411 */
412 static inline int dap_run(struct adiv5_dap *dap)
413 {
414 assert(dap->ops != NULL);
415 return dap->ops->run(dap);
416 }
417
418 static inline int dap_sync(struct adiv5_dap *dap)
419 {
420 assert(dap->ops != NULL);
421 if (dap->ops->sync)
422 return dap->ops->sync(dap);
423 return ERROR_OK;
424 }
425
426 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
427 uint32_t *value)
428 {
429 int retval;
430
431 retval = dap_queue_dp_read(dap, reg, value);
432 if (retval != ERROR_OK)
433 return retval;
434
435 return dap_run(dap);
436 }
437
438 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
439 uint32_t mask, uint32_t value, int timeout)
440 {
441 assert(timeout > 0);
442 assert((value & mask) == value);
443
444 int ret;
445 uint32_t regval;
446 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
447 reg, mask, value);
448 do {
449 ret = dap_dp_read_atomic(dap, reg, &regval);
450 if (ret != ERROR_OK)
451 return ret;
452
453 if ((regval & mask) == value)
454 break;
455
456 alive_sleep(10);
457 } while (--timeout);
458
459 if (!timeout) {
460 LOG_DEBUG("DAP: poll %x timeout", reg);
461 return ERROR_WAIT;
462 } else {
463 return ERROR_OK;
464 }
465 }
466
467 /* Queued MEM-AP memory mapped single word transfers. */
468 int mem_ap_read_u32(struct adiv5_ap *ap,
469 uint32_t address, uint32_t *value);
470 int mem_ap_write_u32(struct adiv5_ap *ap,
471 uint32_t address, uint32_t value);
472
473 /* Synchronous MEM-AP memory mapped single word transfers. */
474 int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
475 uint32_t address, uint32_t *value);
476 int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
477 uint32_t address, uint32_t value);
478
479 /* Synchronous MEM-AP memory mapped bus block transfers. */
480 int mem_ap_read_buf(struct adiv5_ap *ap,
481 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
482 int mem_ap_write_buf(struct adiv5_ap *ap,
483 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
484
485 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
486 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
487 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
488 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
489 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
490
491 /* Initialisation of the debug system, power domains and registers */
492 int dap_dp_init(struct adiv5_dap *dap);
493 int mem_ap_init(struct adiv5_ap *ap);
494
495 /* Invalidate cached DP select and cached TAR and CSW of all APs */
496 void dap_invalidate_cache(struct adiv5_dap *dap);
497
498 /* Probe the AP for ROM Table location */
499 int dap_get_debugbase(struct adiv5_ap *ap,
500 uint32_t *dbgbase, uint32_t *apid);
501
502 /* Probe Access Ports to find a particular type */
503 int dap_find_ap(struct adiv5_dap *dap,
504 enum ap_type type_to_find,
505 struct adiv5_ap **ap_out);
506
507 static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
508 {
509 return &dap->ap[ap_num];
510 }
511
512 /* Lookup CoreSight component */
513 int dap_lookup_cs_component(struct adiv5_ap *ap,
514 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
515
516 struct target;
517
518 /* Put debug link into SWD mode */
519 int dap_to_swd(struct adiv5_dap *dap);
520
521 /* Put debug link into JTAG mode */
522 int dap_to_jtag(struct adiv5_dap *dap);
523
524 extern const struct command_registration dap_instance_commands[];
525
526 struct arm_dap_object;
527 extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o);
528 extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj);
529 extern int dap_info_command(struct command_invocation *cmd,
530 struct adiv5_ap *ap);
531 extern int dap_register_commands(struct command_context *cmd_ctx);
532 extern const char *adiv5_dap_name(struct adiv5_dap *self);
533 extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self);
534 extern int dap_cleanup_all(void);
535
536 struct adiv5_private_config {
537 int ap_num;
538 struct adiv5_dap *dap;
539 };
540
541 extern int adiv5_verify_config(struct adiv5_private_config *pc);
542 extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi);
543
544 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */