1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
85 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap
*dap
,uint8_t apsel
)
105 uint32_t select_apsel
= (apsel
<< 24) & 0xFF000000;
107 if (select_apsel
!= dap
->apsel
)
109 dap
->apsel
= select_apsel
;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
113 dap
->ap_bank_value
= -1;
114 dap
->ap_csw_value
= -1;
115 dap
->ap_tar_value
= -1;
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
128 * @todo Rename to reflect it being specifically a MEM-AP function.
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
138 int dap_setup_accessport(struct adiv5_dap
*dap
, uint32_t csw
, uint32_t tar
)
142 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
143 if (csw
!= dap
->ap_csw_value
)
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval
= dap_queue_ap_write(dap
, AP_REG_CSW
, csw
);
147 if (retval
!= ERROR_OK
)
149 dap
->ap_csw_value
= csw
;
151 if (tar
!= dap
->ap_tar_value
)
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval
= dap_queue_ap_write(dap
, AP_REG_TAR
, tar
);
155 if (retval
!= ERROR_OK
)
157 dap
->ap_tar_value
= tar
;
159 /* Disable TAR cache when autoincrementing */
160 if (csw
& CSW_ADDRINC_MASK
)
161 dap
->ap_tar_value
= -1;
166 * Asynchronous (queued) read of a word from memory or a system register.
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
174 * @return ERROR_OK for success. Otherwise a fault code.
176 int mem_ap_read_u32(struct adiv5_dap
*dap
, uint32_t address
,
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
184 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
185 address
& 0xFFFFFFF0);
186 if (retval
!= ERROR_OK
)
189 return dap_queue_ap_read(dap
, AP_REG_BD0
| (address
& 0xC), value
);
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
204 int mem_ap_read_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
209 retval
= mem_ap_read_u32(dap
, address
, value
);
210 if (retval
!= ERROR_OK
)
217 * Asynchronous (queued) write of a word to memory or a system register.
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
225 * @return ERROR_OK for success. Otherwise a fault code.
227 int mem_ap_write_u32(struct adiv5_dap
*dap
, uint32_t address
,
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
235 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
236 address
& 0xFFFFFFF0);
237 if (retval
!= ERROR_OK
)
240 return dap_queue_ap_write(dap
, AP_REG_BD0
| (address
& 0xC),
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
255 int mem_ap_write_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
258 int retval
= mem_ap_write_u32(dap
, address
, value
);
260 if (retval
!= ERROR_OK
)
266 /*****************************************************************************
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
270 * Write a buffer in target order (little endian) *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap
*dap
, uint8_t *buffer
, int count
, uint32_t address
)
275 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
276 uint32_t adr
= address
;
277 uint8_t* pBuffer
= buffer
;
282 /* if we have an unaligned access - reorder data */
285 for (writecount
= 0; writecount
< count
; writecount
++)
289 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
291 for (i
= 0; i
< 4; i
++)
293 *((uint8_t*)pBuffer
+ (adr
& 0x3)) = outvalue
;
297 pBuffer
+= sizeof(uint32_t);
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
305 if (wcount
< blocksize
)
308 /* handle unaligned data at 4k boundary */
312 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
313 if (retval
!= ERROR_OK
)
316 for (writecount
= 0; writecount
< blocksize
; writecount
++)
318 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
,
319 *(uint32_t *) (buffer
+ 4 * writecount
));
320 if (retval
!= ERROR_OK
)
324 if (dap_run(dap
) == ERROR_OK
)
326 wcount
= wcount
- blocksize
;
327 address
= address
+ 4 * blocksize
;
328 buffer
= buffer
+ 4 * blocksize
;
337 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
338 /* REVISIT return the *actual* fault code */
339 return ERROR_JTAG_DEVICE_ERROR
;
346 static int mem_ap_write_buf_packed_u16(struct adiv5_dap
*dap
,
347 uint8_t *buffer
, int count
, uint32_t address
)
349 int retval
= ERROR_OK
;
350 int wcount
, blocksize
, writecount
, i
;
358 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
359 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
361 if (wcount
< blocksize
)
364 /* handle unaligned data at 4k boundary */
368 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
369 if (retval
!= ERROR_OK
)
371 writecount
= blocksize
;
375 nbytes
= MIN((writecount
<< 1), 4);
379 if (mem_ap_write_buf_u16(dap
, buffer
,
380 nbytes
, address
) != ERROR_OK
)
382 LOG_WARNING("Block write error address "
383 "0x%" PRIx32
", count 0x%x",
385 return ERROR_JTAG_DEVICE_ERROR
;
388 address
+= nbytes
>> 1;
393 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
395 for (i
= 0; i
< nbytes
; i
++)
397 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
402 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
403 retval
= dap_queue_ap_write(dap
,
404 AP_REG_DRW
, outvalue
);
405 if (retval
!= ERROR_OK
)
408 if (dap_run(dap
) != ERROR_OK
)
410 LOG_WARNING("Block write error address "
411 "0x%" PRIx32
", count 0x%x",
413 /* REVISIT return *actual* fault code */
414 return ERROR_JTAG_DEVICE_ERROR
;
418 buffer
+= nbytes
>> 1;
419 writecount
-= nbytes
>> 1;
421 } while (writecount
);
428 int mem_ap_write_buf_u16(struct adiv5_dap
*dap
, uint8_t *buffer
, int count
, uint32_t address
)
430 int retval
= ERROR_OK
;
433 return mem_ap_write_buf_packed_u16(dap
, buffer
, count
, address
);
437 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
438 if (retval
!= ERROR_OK
)
441 memcpy(&svalue
, buffer
, sizeof(uint16_t));
442 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
443 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
444 if (retval
!= ERROR_OK
)
447 retval
= dap_run(dap
);
448 if (retval
!= ERROR_OK
)
459 static int mem_ap_write_buf_packed_u8(struct adiv5_dap
*dap
,
460 uint8_t *buffer
, int count
, uint32_t address
)
462 int retval
= ERROR_OK
;
463 int wcount
, blocksize
, writecount
, i
;
471 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
472 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
474 if (wcount
< blocksize
)
477 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
478 if (retval
!= ERROR_OK
)
480 writecount
= blocksize
;
484 nbytes
= MIN(writecount
, 4);
488 if (mem_ap_write_buf_u8(dap
, buffer
, nbytes
, address
) != ERROR_OK
)
490 LOG_WARNING("Block write error address "
491 "0x%" PRIx32
", count 0x%x",
493 return ERROR_JTAG_DEVICE_ERROR
;
501 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
503 for (i
= 0; i
< nbytes
; i
++)
505 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
510 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
511 retval
= dap_queue_ap_write(dap
,
512 AP_REG_DRW
, outvalue
);
513 if (retval
!= ERROR_OK
)
516 if (dap_run(dap
) != ERROR_OK
)
518 LOG_WARNING("Block write error address "
519 "0x%" PRIx32
", count 0x%x",
521 /* REVISIT return *actual* fault code */
522 return ERROR_JTAG_DEVICE_ERROR
;
527 writecount
-= nbytes
;
529 } while (writecount
);
536 int mem_ap_write_buf_u8(struct adiv5_dap
*dap
, uint8_t *buffer
, int count
, uint32_t address
)
538 int retval
= ERROR_OK
;
541 return mem_ap_write_buf_packed_u8(dap
, buffer
, count
, address
);
545 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
546 if (retval
!= ERROR_OK
)
548 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
549 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
550 if (retval
!= ERROR_OK
)
553 retval
= dap_run(dap
);
554 if (retval
!= ERROR_OK
)
565 /* FIXME don't import ... this is a temporary workaround for the
566 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
568 extern int adi_jtag_dp_scan(struct adiv5_dap
*dap
,
569 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
570 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
);
573 * Synchronously read a block of 32-bit words into a buffer
574 * @param dap The DAP connected to the MEM-AP.
575 * @param buffer where the words will be stored (in host byte order).
576 * @param count How many words to read.
577 * @param address Memory address from which to read words; all the
578 * words must be readable by the currently selected MEM-AP.
580 int mem_ap_read_buf_u32(struct adiv5_dap
*dap
, uint8_t *buffer
,
581 int count
, uint32_t address
)
583 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
584 uint32_t adr
= address
;
585 uint8_t* pBuffer
= buffer
;
592 /* Adjust to read blocks within boundaries aligned to the
593 * TAR autoincrement size (at least 2^10). Autoincrement
594 * mode avoids an extra per-word roundtrip to update TAR.
596 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
,
598 if (wcount
< blocksize
)
601 /* handle unaligned data at 4k boundary */
605 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_SINGLE
,
607 if (retval
!= ERROR_OK
)
610 /* FIXME remove these three calls to adi_jtag_dp_scan(),
611 * so this routine becomes transport-neutral. Be careful
612 * not to cause performance problems with JTAG; would it
613 * suffice to loop over dap_queue_ap_read(), or would that
614 * be slower when JTAG is the chosen transport?
617 /* Scan out first read */
618 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, AP_REG_DRW
,
619 DPAP_READ
, 0, NULL
, NULL
);
620 if (retval
!= ERROR_OK
)
622 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
624 /* Scan out next read; scan in posted value for the
625 * previous one. Assumes read is acked "OK/FAULT",
626 * and CTRL_STAT says that meant "OK".
628 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, AP_REG_DRW
,
629 DPAP_READ
, 0, buffer
+ 4 * readcount
,
631 if (retval
!= ERROR_OK
)
635 /* Scan in last posted value; RDBUFF has no other effect,
636 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
638 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_DPACC
, DP_RDBUFF
,
639 DPAP_READ
, 0, buffer
+ 4 * readcount
,
641 if (retval
!= ERROR_OK
)
644 retval
= dap_run(dap
);
645 if (retval
!= ERROR_OK
)
653 LOG_WARNING("Block read error address 0x%" PRIx32
, address
);
656 wcount
= wcount
- blocksize
;
657 address
+= 4 * blocksize
;
658 buffer
+= 4 * blocksize
;
661 /* if we have an unaligned access - reorder data */
664 for (readcount
= 0; readcount
< count
; readcount
++)
668 memcpy(&data
, pBuffer
, sizeof(uint32_t));
670 for (i
= 0; i
< 4; i
++)
672 *((uint8_t*)pBuffer
) =
673 (data
>> 8 * (adr
& 0x3));
683 static int mem_ap_read_buf_packed_u16(struct adiv5_dap
*dap
,
684 uint8_t *buffer
, int count
, uint32_t address
)
687 int retval
= ERROR_OK
;
688 int wcount
, blocksize
, readcount
, i
;
696 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
697 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
698 if (wcount
< blocksize
)
701 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
702 if (retval
!= ERROR_OK
)
705 /* handle unaligned data at 4k boundary */
708 readcount
= blocksize
;
712 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
713 if (dap_run(dap
) != ERROR_OK
)
715 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
716 /* REVISIT return the *actual* fault code */
717 return ERROR_JTAG_DEVICE_ERROR
;
720 nbytes
= MIN((readcount
<< 1), 4);
722 for (i
= 0; i
< nbytes
; i
++)
724 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
729 readcount
-= (nbytes
>> 1);
738 * Synchronously read a block of 16-bit halfwords into a buffer
739 * @param dap The DAP connected to the MEM-AP.
740 * @param buffer where the halfwords will be stored (in host byte order).
741 * @param count How many halfwords to read.
742 * @param address Memory address from which to read words; all the
743 * words must be readable by the currently selected MEM-AP.
745 int mem_ap_read_buf_u16(struct adiv5_dap
*dap
, uint8_t *buffer
,
746 int count
, uint32_t address
)
749 int retval
= ERROR_OK
;
752 return mem_ap_read_buf_packed_u16(dap
, buffer
, count
, address
);
756 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
757 if (retval
!= ERROR_OK
)
759 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
760 if (retval
!= ERROR_OK
)
763 retval
= dap_run(dap
);
764 if (retval
!= ERROR_OK
)
769 for (i
= 0; i
< 2; i
++)
771 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
778 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
779 memcpy(buffer
, &svalue
, sizeof(uint16_t));
789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
790 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
792 * The solution is to arrange for a large out/in scan in this loop and
793 * and convert data afterwards.
795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap
*dap
,
796 uint8_t *buffer
, int count
, uint32_t address
)
799 int retval
= ERROR_OK
;
800 int wcount
, blocksize
, readcount
, i
;
808 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
809 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
811 if (wcount
< blocksize
)
814 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
815 if (retval
!= ERROR_OK
)
817 readcount
= blocksize
;
821 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
822 if (dap_run(dap
) != ERROR_OK
)
824 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
825 /* REVISIT return the *actual* fault code */
826 return ERROR_JTAG_DEVICE_ERROR
;
829 nbytes
= MIN(readcount
, 4);
831 for (i
= 0; i
< nbytes
; i
++)
833 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
847 * Synchronously read a block of bytes into a buffer
848 * @param dap The DAP connected to the MEM-AP.
849 * @param buffer where the bytes will be stored.
850 * @param count How many bytes to read.
851 * @param address Memory address from which to read data; all the
852 * data must be readable by the currently selected MEM-AP.
854 int mem_ap_read_buf_u8(struct adiv5_dap
*dap
, uint8_t *buffer
,
855 int count
, uint32_t address
)
858 int retval
= ERROR_OK
;
861 return mem_ap_read_buf_packed_u8(dap
, buffer
, count
, address
);
865 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
866 if (retval
!= ERROR_OK
)
868 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
869 if (retval
!= ERROR_OK
)
871 retval
= dap_run(dap
);
872 if (retval
!= ERROR_OK
)
875 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
884 /*--------------------------------------------------------------------------*/
887 /* FIXME don't import ... just initialize as
888 * part of DAP transport setup
890 extern const struct dap_ops jtag_dp_ops
;
892 /*--------------------------------------------------------------------------*/
895 * Initialize a DAP. This sets up the power domains, prepares the DP
896 * for further use, and arranges to use AP #0 for all AP operations
897 * until dap_ap-select() changes that policy.
899 * @param dap The DAP being initialized.
901 * @todo Rename this. We also need an initialization scheme which account
902 * for SWD transports not just JTAG; that will need to address differences
903 * in layering. (JTAG is useful without any debug target; but not SWD.)
904 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
906 int ahbap_debugport_init(struct adiv5_dap
*dap
)
908 uint32_t idreg
, romaddr
, dummy
;
915 /* JTAG-DP or SWJ-DP, in JTAG mode */
916 dap
->ops
= &jtag_dp_ops
;
918 /* Default MEM-AP setup.
920 * REVISIT AP #0 may be an inappropriate default for this.
921 * Should we probe, or take a hint from the caller?
922 * Presumably we can ignore the possibility of multiple APs.
925 dap_ap_select(dap
, 0);
927 /* DP initialization */
929 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &dummy
);
930 if (retval
!= ERROR_OK
)
933 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, SSTICKYERR
);
934 if (retval
!= ERROR_OK
)
937 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &dummy
);
938 if (retval
!= ERROR_OK
)
941 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
942 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
943 if (retval
!= ERROR_OK
)
946 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
947 if (retval
!= ERROR_OK
)
949 if ((retval
= dap_run(dap
)) != ERROR_OK
)
952 /* Check that we have debug power domains activated */
953 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
955 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
956 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
957 if (retval
!= ERROR_OK
)
959 if ((retval
= dap_run(dap
)) != ERROR_OK
)
964 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
966 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
967 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
968 if (retval
!= ERROR_OK
)
970 if ((retval
= dap_run(dap
)) != ERROR_OK
)
975 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &dummy
);
976 if (retval
!= ERROR_OK
)
978 /* With debug power on we can activate OVERRUN checking */
979 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
980 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
981 if (retval
!= ERROR_OK
)
983 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &dummy
);
984 if (retval
!= ERROR_OK
)
988 * REVISIT this isn't actually *initializing* anything in an AP,
989 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
990 * Should it? If the ROM address is valid, is this the right
991 * place to scan the table and do any topology detection?
993 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &idreg
);
994 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &romaddr
);
996 if ((retval
= dap_run(dap
)) != ERROR_OK
)
999 LOG_DEBUG("MEM-AP #%" PRId32
" ID Register 0x%" PRIx32
1000 ", Debug ROM Address 0x%" PRIx32
,
1001 dap
->apsel
, idreg
, romaddr
);
1006 /* CID interpretation -- see ARM IHI 0029B section 3
1007 * and ARM IHI 0031A table 13-3.
1009 static const char *class_description
[16] ={
1010 "Reserved", "ROM table", "Reserved", "Reserved",
1011 "Reserved", "Reserved", "Reserved", "Reserved",
1012 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1013 "Reserved", "OptimoDE DESS",
1014 "Generic IP component", "PrimeCell or System component"
1018 is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1020 return cid3
== 0xb1 && cid2
== 0x05
1021 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1024 static int dap_info_command(struct command_context
*cmd_ctx
,
1025 struct adiv5_dap
*dap
, int apsel
)
1028 uint32_t dbgbase
, apid
;
1029 int romtable_present
= 0;
1033 /* AP address is in bits 31:24 of DP_SELECT */
1035 return ERROR_INVALID_ARGUMENTS
;
1037 apselold
= dap
->apsel
;
1038 dap_ap_select(dap
, apsel
);
1039 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &dbgbase
);
1040 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1041 retval
= dap_run(dap
);
1042 if (retval
!= ERROR_OK
)
1045 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1046 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1047 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1053 command_print(cmd_ctx
, "\tType is JTAG-AP");
1056 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1059 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1062 command_print(cmd_ctx
, "\tUnknown AP type");
1066 /* NOTE: a MEM-AP may have a single CoreSight component that's
1067 * not a ROM table ... or have no such components at all.
1070 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
,
1075 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1078 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1079 if (romtable_present
)
1081 uint32_t cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1082 uint16_t entry_offset
;
1084 /* bit 16 of apid indicates a memory access port */
1086 command_print(cmd_ctx
, "\tValid ROM table present");
1088 command_print(cmd_ctx
, "\tROM table in legacy format");
1090 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1091 mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1092 mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1093 mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1094 mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1095 mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1096 retval
= dap_run(dap
);
1097 if (retval
!= ERROR_OK
)
1100 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1101 command_print(cmd_ctx
, "\tCID3 0x%2.2x"
1105 (unsigned) cid3
, (unsigned)cid2
,
1106 (unsigned) cid1
, (unsigned) cid0
);
1108 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1110 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1111 "Dedicated debug bus.");
1113 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1117 mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1118 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"",entry_offset
,romentry
);
1121 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1122 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1123 uint32_t component_base
;
1127 component_base
= (dbgbase
& 0xFFFFF000)
1128 + (romentry
& 0xFFFFF000);
1130 /* IDs are in last 4K section */
1133 mem_ap_read_atomic_u32(dap
,
1134 component_base
+ 0xFE0, &c_pid0
);
1136 mem_ap_read_atomic_u32(dap
,
1137 component_base
+ 0xFE4, &c_pid1
);
1139 mem_ap_read_atomic_u32(dap
,
1140 component_base
+ 0xFE8, &c_pid2
);
1142 mem_ap_read_atomic_u32(dap
,
1143 component_base
+ 0xFEC, &c_pid3
);
1145 mem_ap_read_atomic_u32(dap
,
1146 component_base
+ 0xFD0, &c_pid4
);
1149 mem_ap_read_atomic_u32(dap
,
1150 component_base
+ 0xFF0, &c_cid0
);
1152 mem_ap_read_atomic_u32(dap
,
1153 component_base
+ 0xFF4, &c_cid1
);
1155 mem_ap_read_atomic_u32(dap
,
1156 component_base
+ 0xFF8, &c_cid2
);
1158 mem_ap_read_atomic_u32(dap
,
1159 component_base
+ 0xFFC, &c_cid3
);
1163 command_print(cmd_ctx
,
1164 "\t\tComponent base address 0x%" PRIx32
1165 ", start address 0x%" PRIx32
,
1167 /* component may take multiple 4K pages */
1168 component_base
- 0x1000*(c_pid4
>> 4));
1169 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1170 (int) (c_cid1
>> 4) & 0xf,
1171 /* See ARM IHI 0029B Table 3-3 */
1172 class_description
[(c_cid1
>> 4) & 0xf]);
1174 /* CoreSight component? */
1175 if (((c_cid1
>> 4) & 0x0f) == 9) {
1178 char *major
= "Reserved", *subtype
= "Reserved";
1180 mem_ap_read_atomic_u32(dap
,
1181 (component_base
& 0xfffff000) | 0xfcc,
1183 minor
= (devtype
>> 4) & 0x0f;
1184 switch (devtype
& 0x0f) {
1186 major
= "Miscellaneous";
1192 subtype
= "Validation component";
1197 major
= "Trace Sink";
1211 major
= "Trace Link";
1217 subtype
= "Funnel, router";
1223 subtype
= "FIFO, buffer";
1228 major
= "Trace Source";
1234 subtype
= "Processor";
1240 subtype
= "Engine/Coprocessor";
1248 major
= "Debug Control";
1254 subtype
= "Trigger Matrix";
1257 subtype
= "Debug Auth";
1262 major
= "Debug Logic";
1268 subtype
= "Processor";
1274 subtype
= "Engine/Coprocessor";
1279 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1280 (unsigned) (devtype
& 0xff),
1282 /* REVISIT also show 0xfc8 DevId */
1285 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1286 command_print(cmd_ctx
,
1295 command_print(cmd_ctx
,
1296 "\t\tPeripheral ID[4..0] = hex "
1297 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1298 (int) c_pid4
, (int) c_pid3
, (int) c_pid2
,
1299 (int) c_pid1
, (int) c_pid0
);
1301 /* Part number interpretations are from Cortex
1302 * core specs, the CoreSight components TRM
1303 * (ARM DDI 0314H), and ETM specs; also from
1304 * chip observation (e.g. TI SDTI).
1306 part_num
= (c_pid0
& 0xff);
1307 part_num
|= (c_pid1
& 0x0f) << 8;
1310 type
= "Cortex-M3 NVIC";
1311 full
= "(Interrupt Controller)";
1314 type
= "Cortex-M3 ITM";
1315 full
= "(Instrumentation Trace Module)";
1318 type
= "Cortex-M3 DWT";
1319 full
= "(Data Watchpoint and Trace)";
1322 type
= "Cortex-M3 FBP";
1323 full
= "(Flash Patch and Breakpoint)";
1326 type
= "CoreSight ETM11";
1327 full
= "(Embedded Trace)";
1329 // case 0x113: what?
1330 case 0x120: /* from OMAP3 memmap */
1332 full
= "(System Debug Trace Interface)";
1334 case 0x343: /* from OMAP3 memmap */
1339 type
= "Coresight CTI";
1340 full
= "(Cross Trigger)";
1343 type
= "Coresight ETB";
1344 full
= "(Trace Buffer)";
1347 type
= "Coresight CSTF";
1348 full
= "(Trace Funnel)";
1351 type
= "CoreSight ETM9";
1352 full
= "(Embedded Trace)";
1355 type
= "Coresight TPIU";
1356 full
= "(Trace Port Interface Unit)";
1359 type
= "Cortex-A8 ETM";
1360 full
= "(Embedded Trace)";
1363 type
= "Cortex-A8 CTI";
1364 full
= "(Cross Trigger)";
1367 type
= "Cortex-M3 TPIU";
1368 full
= "(Trace Port Interface Unit)";
1371 type
= "Cortex-M3 ETM";
1372 full
= "(Embedded Trace)";
1375 type
= "Cortex-A8 Debug";
1376 full
= "(Debug Unit)";
1379 type
= "-*- unrecognized -*-";
1383 command_print(cmd_ctx
, "\t\tPart is %s %s",
1389 command_print(cmd_ctx
, "\t\tComponent not present");
1391 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1394 } while (romentry
> 0);
1398 command_print(cmd_ctx
, "\tNo ROM table present");
1400 dap_ap_select(dap
, apselold
);
1405 COMMAND_HANDLER(handle_dap_info_command
)
1407 struct target
*target
= get_current_target(CMD_CTX
);
1408 struct arm
*arm
= target_to_arm(target
);
1409 struct adiv5_dap
*dap
= arm
->dap
;
1417 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1420 return ERROR_COMMAND_SYNTAX_ERROR
;
1423 return dap_info_command(CMD_CTX
, dap
, apsel
);
1426 COMMAND_HANDLER(dap_baseaddr_command
)
1428 struct target
*target
= get_current_target(CMD_CTX
);
1429 struct arm
*arm
= target_to_arm(target
);
1430 struct adiv5_dap
*dap
= arm
->dap
;
1432 uint32_t apsel
, apselsave
, baseaddr
;
1435 apselsave
= dap
->apsel
;
1441 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1442 /* AP address is in bits 31:24 of DP_SELECT */
1444 return ERROR_INVALID_ARGUMENTS
;
1447 return ERROR_COMMAND_SYNTAX_ERROR
;
1450 if (apselsave
!= apsel
)
1451 dap_ap_select(dap
, apsel
);
1453 /* NOTE: assumes we're talking to a MEM-AP, which
1454 * has a base address. There are other kinds of AP,
1455 * though they're not common for now. This should
1456 * use the ID register to verify it's a MEM-AP.
1458 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &baseaddr
);
1459 retval
= dap_run(dap
);
1460 if (retval
!= ERROR_OK
)
1463 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1465 if (apselsave
!= apsel
)
1466 dap_ap_select(dap
, apselsave
);
1471 COMMAND_HANDLER(dap_memaccess_command
)
1473 struct target
*target
= get_current_target(CMD_CTX
);
1474 struct arm
*arm
= target_to_arm(target
);
1475 struct adiv5_dap
*dap
= arm
->dap
;
1477 uint32_t memaccess_tck
;
1481 memaccess_tck
= dap
->memaccess_tck
;
1484 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1487 return ERROR_COMMAND_SYNTAX_ERROR
;
1489 dap
->memaccess_tck
= memaccess_tck
;
1491 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1492 dap
->memaccess_tck
);
1497 COMMAND_HANDLER(dap_apsel_command
)
1499 struct target
*target
= get_current_target(CMD_CTX
);
1500 struct arm
*arm
= target_to_arm(target
);
1501 struct adiv5_dap
*dap
= arm
->dap
;
1503 uint32_t apsel
, apid
;
1511 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1512 /* AP address is in bits 31:24 of DP_SELECT */
1514 return ERROR_INVALID_ARGUMENTS
;
1517 return ERROR_COMMAND_SYNTAX_ERROR
;
1520 dap_ap_select(dap
, apsel
);
1521 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1522 retval
= dap_run(dap
);
1523 if (retval
!= ERROR_OK
)
1526 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1532 COMMAND_HANDLER(dap_apid_command
)
1534 struct target
*target
= get_current_target(CMD_CTX
);
1535 struct arm
*arm
= target_to_arm(target
);
1536 struct adiv5_dap
*dap
= arm
->dap
;
1538 uint32_t apsel
, apselsave
, apid
;
1541 apselsave
= dap
->apsel
;
1547 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1548 /* AP address is in bits 31:24 of DP_SELECT */
1550 return ERROR_INVALID_ARGUMENTS
;
1553 return ERROR_COMMAND_SYNTAX_ERROR
;
1556 if (apselsave
!= apsel
)
1557 dap_ap_select(dap
, apsel
);
1559 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1560 retval
= dap_run(dap
);
1561 if (retval
!= ERROR_OK
)
1564 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1565 if (apselsave
!= apsel
)
1566 dap_ap_select(dap
, apselsave
);
1571 static const struct command_registration dap_commands
[] = {
1574 .handler
= handle_dap_info_command
,
1575 .mode
= COMMAND_EXEC
,
1576 .help
= "display ROM table for MEM-AP "
1577 "(default currently selected AP)",
1578 .usage
= "[ap_num]",
1582 .handler
= dap_apsel_command
,
1583 .mode
= COMMAND_EXEC
,
1584 .help
= "Set the currently selected AP (default 0) "
1585 "and display the result",
1586 .usage
= "[ap_num]",
1590 .handler
= dap_apid_command
,
1591 .mode
= COMMAND_EXEC
,
1592 .help
= "return ID register from AP "
1593 "(default currently selected AP)",
1594 .usage
= "[ap_num]",
1598 .handler
= dap_baseaddr_command
,
1599 .mode
= COMMAND_EXEC
,
1600 .help
= "return debug base address from MEM-AP "
1601 "(default currently selected AP)",
1602 .usage
= "[ap_num]",
1605 .name
= "memaccess",
1606 .handler
= dap_memaccess_command
,
1607 .mode
= COMMAND_EXEC
,
1608 .help
= "set/get number of extra tck for MEM-AP memory "
1609 "bus access [0-255]",
1610 .usage
= "[cycles]",
1612 COMMAND_REGISTRATION_DONE
1615 const struct command_registration dap_command_handlers
[] = {
1618 .mode
= COMMAND_EXEC
,
1619 .help
= "DAP command group",
1620 .chain
= dap_commands
,
1622 COMMAND_REGISTRATION_DONE
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)