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arm_adi_v5: Rewrite MEM-AP transfer implementation
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "jtag/interface.h"
76 #include "arm.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
79
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
81
82 /*
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
85 */
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
87 {
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
89 }
90
91 /***************************************************************************
92 * *
93 * DP and MEM-AP register access through APACC and DPACC *
94 * *
95 ***************************************************************************/
96
97 /**
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
101 *
102 * @param dap The DAP
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
105 */
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
107 {
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
109
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
114 */
115 dap->ap_bank_value = -1;
116 dap->ap_csw_value = -1;
117 dap->ap_tar_value = -1;
118 }
119 }
120
121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
122 {
123 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
124 dap->apcsw[dap->ap_current >> 24];
125
126 if (csw != dap->ap_csw_value) {
127 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
128 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
129 if (retval != ERROR_OK)
130 return retval;
131 dap->ap_csw_value = csw;
132 }
133 return ERROR_OK;
134 }
135
136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
137 {
138 if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
139 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
140 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
141 if (retval != ERROR_OK)
142 return retval;
143 dap->ap_tar_value = tar;
144 }
145 return ERROR_OK;
146 }
147
148 /**
149 * Queue transactions setting up transfer parameters for the
150 * currently selected MEM-AP.
151 *
152 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
153 * initiate data reads or writes using memory or peripheral addresses.
154 * If the CSW is configured for it, the TAR may be automatically
155 * incremented after each transfer.
156 *
157 * @todo Rename to reflect it being specifically a MEM-AP function.
158 *
159 * @param dap The DAP connected to the MEM-AP.
160 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
161 * matches the cached value, the register is not changed.
162 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
163 * matches the cached address, the register is not changed.
164 *
165 * @return ERROR_OK if the transaction was properly queued, else a fault code.
166 */
167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
168 {
169 int retval;
170 retval = dap_setup_accessport_csw(dap, csw);
171 if (retval != ERROR_OK)
172 return retval;
173 retval = dap_setup_accessport_tar(dap, tar);
174 if (retval != ERROR_OK)
175 return retval;
176 return ERROR_OK;
177 }
178
179 /**
180 * Asynchronous (queued) read of a word from memory or a system register.
181 *
182 * @param dap The DAP connected to the MEM-AP performing the read.
183 * @param address Address of the 32-bit word to read; it must be
184 * readable by the currently selected MEM-AP.
185 * @param value points to where the word will be stored when the
186 * transaction queue is flushed (assuming no errors).
187 *
188 * @return ERROR_OK for success. Otherwise a fault code.
189 */
190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
191 uint32_t *value)
192 {
193 int retval;
194
195 /* Use banked addressing (REG_BDx) to avoid some link traffic
196 * (updating TAR) when reading several consecutive addresses.
197 */
198 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
199 address & 0xFFFFFFF0);
200 if (retval != ERROR_OK)
201 return retval;
202
203 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
204 }
205
206 /**
207 * Synchronous read of a word from memory or a system register.
208 * As a side effect, this flushes any queued transactions.
209 *
210 * @param dap The DAP connected to the MEM-AP performing the read.
211 * @param address Address of the 32-bit word to read; it must be
212 * readable by the currently selected MEM-AP.
213 * @param value points to where the result will be stored.
214 *
215 * @return ERROR_OK for success; *value holds the result.
216 * Otherwise a fault code.
217 */
218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
219 uint32_t *value)
220 {
221 int retval;
222
223 retval = mem_ap_read_u32(dap, address, value);
224 if (retval != ERROR_OK)
225 return retval;
226
227 return dap_run(dap);
228 }
229
230 /**
231 * Asynchronous (queued) write of a word to memory or a system register.
232 *
233 * @param dap The DAP connected to the MEM-AP.
234 * @param address Address to be written; it must be writable by
235 * the currently selected MEM-AP.
236 * @param value Word that will be written to the address when transaction
237 * queue is flushed (assuming no errors).
238 *
239 * @return ERROR_OK for success. Otherwise a fault code.
240 */
241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
242 uint32_t value)
243 {
244 int retval;
245
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when writing several consecutive addresses.
248 */
249 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
250 address & 0xFFFFFFF0);
251 if (retval != ERROR_OK)
252 return retval;
253
254 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
255 value);
256 }
257
258 /**
259 * Synchronous write of a word to memory or a system register.
260 * As a side effect, this flushes any queued transactions.
261 *
262 * @param dap The DAP connected to the MEM-AP.
263 * @param address Address to be written; it must be writable by
264 * the currently selected MEM-AP.
265 * @param value Word that will be written.
266 *
267 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
268 */
269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
270 uint32_t value)
271 {
272 int retval = mem_ap_write_u32(dap, address, value);
273
274 if (retval != ERROR_OK)
275 return retval;
276
277 return dap_run(dap);
278 }
279
280 /**
281 * Synchronous write of a block of memory, using a specific access size.
282 *
283 * @param dap The DAP connected to the MEM-AP.
284 * @param buffer The data buffer to write. No particular alignment is assumed.
285 * @param size Which access size to use, in bytes. 1, 2 or 4.
286 * @param count The number of writes to do (in size units, not bytes).
287 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
288 * @param addrinc Whether the target address should be increased for each write or not. This
289 * should normally be true, except when writing to e.g. a FIFO.
290 * @return ERROR_OK on success, otherwise an error code.
291 */
292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
293 uint32_t address, bool addrinc)
294 {
295 size_t nbytes = size * count;
296 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
297 uint32_t csw_size;
298 int retval;
299
300 if (size == 4)
301 csw_size = CSW_32BIT;
302 else if (size == 2)
303 csw_size = CSW_16BIT;
304 else if (size == 1)
305 csw_size = CSW_8BIT;
306 else
307 return ERROR_TARGET_UNALIGNED_ACCESS;
308
309 retval = dap_setup_accessport_tar(dap, address);
310 if (retval != ERROR_OK)
311 return retval;
312
313 while (nbytes > 0) {
314 uint32_t this_size = size;
315
316 /* Select packed transfer if possible */
317 if (addrinc && dap->packed_transfers && nbytes >= 4
318 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
319 this_size = 4;
320 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
321 } else {
322 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
323 }
324
325 if (retval != ERROR_OK)
326 break;
327
328 /* How many source bytes each transfer will consume, and their location in the DRW,
329 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
330 uint32_t outvalue = 0;
331 switch (this_size) {
332 case 4:
333 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
334 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
335 case 2:
336 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
337 case 1:
338 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
339 }
340
341 nbytes -= this_size;
342
343 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
344 if (retval != ERROR_OK)
345 break;
346
347 /* Rewrite TAR if it wrapped */
348 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
349 retval = dap_setup_accessport_tar(dap, address);
350 if (retval != ERROR_OK)
351 break;
352 }
353 }
354
355 /* REVISIT: Might want to have a queued version of this function that does not run. */
356 if (retval == ERROR_OK)
357 retval = dap_run(dap);
358
359 if (retval != ERROR_OK) {
360 uint32_t tar;
361 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
362 && dap_run(dap) == ERROR_OK)
363 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
364 else
365 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
366 }
367
368 return retval;
369 }
370
371 /* Compatibility wrappers around mem_ap_write(). Note that the count is in bytes for these. */
372 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address, bool addr_incr)
373 {
374 return mem_ap_write(dap, buffer, 4, count / 4, address, true);
375 }
376
377 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
378 {
379 return mem_ap_write(dap, buffer, 2, count / 2, address, true);
380 }
381
382 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
383 {
384 return mem_ap_write(dap, buffer, 1, count, address, true);
385 }
386
387 /**
388 * Synchronous read of a block of memory, using a specific access size.
389 *
390 * @param dap The DAP connected to the MEM-AP.
391 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
392 * @param size Which access size to use, in bytes. 1, 2 or 4.
393 * @param count The number of reads to do (in size units, not bytes).
394 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
395 * @param addrinc Whether the target address should be increased after each read or not. This
396 * should normally be true, except when reading from e.g. a FIFO.
397 * @return ERROR_OK on success, otherwise an error code.
398 */
399 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
400 uint32_t adr, bool addrinc)
401 {
402 size_t nbytes = size * count;
403 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
404 uint32_t csw_size;
405 uint32_t address = adr;
406 int retval;
407
408 if (size == 4)
409 csw_size = CSW_32BIT;
410 else if (size == 2)
411 csw_size = CSW_16BIT;
412 else if (size == 1)
413 csw_size = CSW_8BIT;
414 else
415 return ERROR_TARGET_UNALIGNED_ACCESS;
416
417 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
418 * over-allocation if packed transfers are going to be used, but determining the real need at
419 * this point would be messy. */
420 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
421 uint32_t *read_ptr = read_buf;
422 if (read_buf == NULL) {
423 LOG_ERROR("Failed to allocate read buffer");
424 return ERROR_FAIL;
425 }
426
427 retval = dap_setup_accessport_tar(dap, address);
428 if (retval != ERROR_OK)
429 return retval;
430
431 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
432 * useful bytes it contains, and their location in the word, depends on the type of transfer
433 * and alignment. */
434 while (nbytes > 0) {
435 uint32_t this_size = size;
436
437 /* Select packed transfer if possible */
438 if (addrinc && dap->packed_transfers && nbytes >= 4
439 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
440 this_size = 4;
441 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
442 } else {
443 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
444 }
445 if (retval != ERROR_OK)
446 break;
447
448 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
449 if (retval != ERROR_OK)
450 break;
451
452 nbytes -= this_size;
453 address += this_size;
454
455 /* Rewrite TAR if it wrapped */
456 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
457 retval = dap_setup_accessport_tar(dap, address);
458 if (retval != ERROR_OK)
459 break;
460 }
461 }
462
463 if (retval == ERROR_OK)
464 retval = dap_run(dap);
465
466 /* Restore state */
467 address = adr;
468 nbytes = size * count;
469 read_ptr = read_buf;
470
471 /* If something failed, read TAR to find out how much data was successfully read, so we can
472 * at least give the caller what we have. */
473 if (retval != ERROR_OK) {
474 uint32_t tar;
475 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
476 && dap_run(dap) == ERROR_OK) {
477 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
478 if (nbytes > tar - address)
479 nbytes = tar - address;
480 } else {
481 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
482 nbytes = 0;
483 }
484 }
485
486 /* Replay loop to populate caller's buffer from the correct word and byte lane */
487 while (nbytes > 0) {
488 uint32_t this_size = size;
489
490 if (addrinc && dap->packed_transfers && nbytes >= 4
491 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
492 this_size = 4;
493 }
494
495 switch (this_size) {
496 case 4:
497 *buffer++ = *read_ptr >> 8 * (address++ & 3);
498 *buffer++ = *read_ptr >> 8 * (address++ & 3);
499 case 2:
500 *buffer++ = *read_ptr >> 8 * (address++ & 3);
501 case 1:
502 *buffer++ = *read_ptr >> 8 * (address++ & 3);
503 }
504
505 read_ptr++;
506 nbytes -= this_size;
507 }
508
509 free(read_buf);
510 return retval;
511 }
512
513 /* Compatibility wrappers around mem_ap_read(). Note that the count is in bytes for these (despite
514 * what their doxygen documentation said). */
515 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
516 int count, uint32_t address, bool addr_incr)
517 {
518 return mem_ap_read(dap, buffer, 4, count / 4, address, addr_incr);
519 }
520
521 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
522 int count, uint32_t address)
523 {
524 return mem_ap_read(dap, buffer, 2, count / 2, address, true);
525 }
526
527 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
528 int count, uint32_t address)
529 {
530 return mem_ap_read(dap, buffer, 1, count, address, true);
531 }
532
533 /*--------------------------------------------------------------------*/
534 /* Wrapping function with selection of AP */
535 /*--------------------------------------------------------------------*/
536 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
537 uint32_t address, uint32_t *value)
538 {
539 dap_ap_select(swjdp, ap);
540 return mem_ap_read_u32(swjdp, address, value);
541 }
542
543 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
544 uint32_t address, uint32_t value)
545 {
546 dap_ap_select(swjdp, ap);
547 return mem_ap_write_u32(swjdp, address, value);
548 }
549
550 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
551 uint32_t address, uint32_t *value)
552 {
553 dap_ap_select(swjdp, ap);
554 return mem_ap_read_atomic_u32(swjdp, address, value);
555 }
556
557 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
558 uint32_t address, uint32_t value)
559 {
560 dap_ap_select(swjdp, ap);
561 return mem_ap_write_atomic_u32(swjdp, address, value);
562 }
563
564 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
565 uint8_t *buffer, int count, uint32_t address)
566 {
567 dap_ap_select(swjdp, ap);
568 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
569 }
570
571 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
572 uint8_t *buffer, int count, uint32_t address)
573 {
574 dap_ap_select(swjdp, ap);
575 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
576 }
577
578 int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
579 uint8_t *buffer, int count, uint32_t address)
580 {
581 dap_ap_select(swjdp, ap);
582 return mem_ap_read_buf_u32(swjdp, buffer, count, address, false);
583 }
584
585 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
586 uint8_t *buffer, int count, uint32_t address)
587 {
588 dap_ap_select(swjdp, ap);
589 return mem_ap_read_buf_u32(swjdp, buffer, count, address, true);
590 }
591
592 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
593 const uint8_t *buffer, int count, uint32_t address)
594 {
595 dap_ap_select(swjdp, ap);
596 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
597 }
598
599 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
600 const uint8_t *buffer, int count, uint32_t address)
601 {
602 dap_ap_select(swjdp, ap);
603 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
604 }
605
606 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
607 const uint8_t *buffer, int count, uint32_t address)
608 {
609 dap_ap_select(swjdp, ap);
610 return mem_ap_write_buf_u32(swjdp, buffer, count, address, true);
611 }
612
613 int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
614 const uint8_t *buffer, int count, uint32_t address)
615 {
616 dap_ap_select(swjdp, ap);
617 return mem_ap_write_buf_u32(swjdp, buffer, count, address, false);
618 }
619
620 #define MDM_REG_STAT 0x00
621 #define MDM_REG_CTRL 0x04
622 #define MDM_REG_ID 0xfc
623
624 #define MDM_STAT_FMEACK (1<<0)
625 #define MDM_STAT_FREADY (1<<1)
626 #define MDM_STAT_SYSSEC (1<<2)
627 #define MDM_STAT_SYSRES (1<<3)
628 #define MDM_STAT_FMEEN (1<<5)
629 #define MDM_STAT_BACKDOOREN (1<<6)
630 #define MDM_STAT_LPEN (1<<7)
631 #define MDM_STAT_VLPEN (1<<8)
632 #define MDM_STAT_LLSMODEXIT (1<<9)
633 #define MDM_STAT_VLLSXMODEXIT (1<<10)
634 #define MDM_STAT_CORE_HALTED (1<<16)
635 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
636 #define MDM_STAT_CORESLEEPING (1<<18)
637
638 #define MEM_CTRL_FMEIP (1<<0)
639 #define MEM_CTRL_DBG_DIS (1<<1)
640 #define MEM_CTRL_DBG_REQ (1<<2)
641 #define MEM_CTRL_SYS_RES_REQ (1<<3)
642 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
643 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
644 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
645 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
646
647 /**
648 *
649 */
650 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
651 {
652 uint32_t val;
653 int retval;
654 enum reset_types jtag_reset_config = jtag_get_reset_config();
655
656 dap_ap_select(dap, 1);
657
658 /* first check mdm-ap id register */
659 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
660 if (retval != ERROR_OK)
661 return retval;
662 dap_run(dap);
663
664 if (val != 0x001C0000) {
665 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val);
666 dap_ap_select(dap, 0);
667 return ERROR_FAIL;
668 }
669
670 /* read and parse status register
671 * it's important that the device is out of
672 * reset here
673 */
674 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
675 if (retval != ERROR_OK)
676 return retval;
677 dap_run(dap);
678
679 LOG_DEBUG("MDM_REG_STAT %08X", val);
680
681 if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) {
682 LOG_DEBUG("MDMAP: system is secured, masserase needed");
683
684 if (!(val & MDM_STAT_FMEEN))
685 LOG_DEBUG("MDMAP: masserase is disabled");
686 else {
687 /* we need to assert reset */
688 if (jtag_reset_config & RESET_HAS_SRST) {
689 /* default to asserting srst */
690 adapter_assert_reset();
691 } else {
692 LOG_DEBUG("SRST not configured");
693 dap_ap_select(dap, 0);
694 return ERROR_FAIL;
695 }
696
697 while (1) {
698 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
699 if (retval != ERROR_OK)
700 return retval;
701 dap_run(dap);
702 /* read status register and wait for ready */
703 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
704 if (retval != ERROR_OK)
705 return retval;
706 dap_run(dap);
707 LOG_DEBUG("MDM_REG_STAT %08X", val);
708
709 if ((val & 1))
710 break;
711 }
712
713 while (1) {
714 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
715 if (retval != ERROR_OK)
716 return retval;
717 dap_run(dap);
718 /* read status register */
719 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
720 if (retval != ERROR_OK)
721 return retval;
722 dap_run(dap);
723 LOG_DEBUG("MDM_REG_STAT %08X", val);
724 /* read control register and wait for ready */
725 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
726 if (retval != ERROR_OK)
727 return retval;
728 dap_run(dap);
729 LOG_DEBUG("MDM_REG_CTRL %08X", val);
730
731 if (val == 0x00)
732 break;
733 }
734 }
735 }
736
737 dap_ap_select(dap, 0);
738
739 return ERROR_OK;
740 }
741
742 /** */
743 struct dap_syssec_filter {
744 /** */
745 uint32_t idcode;
746 /** */
747 int (*dap_init)(struct adiv5_dap *dap);
748 };
749
750 /** */
751 static struct dap_syssec_filter dap_syssec_filter_data[] = {
752 { 0x4BA00477, dap_syssec_kinetis_mdmap }
753 };
754
755 /**
756 *
757 */
758 int dap_syssec(struct adiv5_dap *dap)
759 {
760 unsigned int i;
761 struct jtag_tap *tap;
762
763 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
764 tap = dap->jtag_info->tap;
765
766 while (tap != NULL) {
767 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
768 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode);
769 dap_syssec_filter_data[i].dap_init(dap);
770 }
771 tap = tap->next_tap;
772 }
773 }
774
775 return ERROR_OK;
776 }
777
778 /*--------------------------------------------------------------------------*/
779
780
781 /* FIXME don't import ... just initialize as
782 * part of DAP transport setup
783 */
784 extern const struct dap_ops jtag_dp_ops;
785
786 /*--------------------------------------------------------------------------*/
787
788 /**
789 * Initialize a DAP. This sets up the power domains, prepares the DP
790 * for further use, and arranges to use AP #0 for all AP operations
791 * until dap_ap-select() changes that policy.
792 *
793 * @param dap The DAP being initialized.
794 *
795 * @todo Rename this. We also need an initialization scheme which account
796 * for SWD transports not just JTAG; that will need to address differences
797 * in layering. (JTAG is useful without any debug target; but not SWD.)
798 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
799 */
800 int ahbap_debugport_init(struct adiv5_dap *dap)
801 {
802 uint32_t ctrlstat;
803 int cnt = 0;
804 int retval;
805
806 LOG_DEBUG(" ");
807
808 /* JTAG-DP or SWJ-DP, in JTAG mode
809 * ... for SWD mode this is patched as part
810 * of link switchover
811 */
812 if (!dap->ops)
813 dap->ops = &jtag_dp_ops;
814
815 /* Default MEM-AP setup.
816 *
817 * REVISIT AP #0 may be an inappropriate default for this.
818 * Should we probe, or take a hint from the caller?
819 * Presumably we can ignore the possibility of multiple APs.
820 */
821 dap->ap_current = !0;
822 dap_ap_select(dap, 0);
823
824 /* DP initialization */
825
826 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
827 if (retval != ERROR_OK)
828 return retval;
829
830 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
831 if (retval != ERROR_OK)
832 return retval;
833
834 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
835 if (retval != ERROR_OK)
836 return retval;
837
838 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
839 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
840 if (retval != ERROR_OK)
841 return retval;
842
843 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
844 if (retval != ERROR_OK)
845 return retval;
846 retval = dap_run(dap);
847 if (retval != ERROR_OK)
848 return retval;
849
850 /* Check that we have debug power domains activated */
851 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
852 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
853 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
854 if (retval != ERROR_OK)
855 return retval;
856 retval = dap_run(dap);
857 if (retval != ERROR_OK)
858 return retval;
859 alive_sleep(10);
860 }
861
862 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
863 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
864 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
865 if (retval != ERROR_OK)
866 return retval;
867 retval = dap_run(dap);
868 if (retval != ERROR_OK)
869 return retval;
870 alive_sleep(10);
871 }
872
873 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
874 if (retval != ERROR_OK)
875 return retval;
876 /* With debug power on we can activate OVERRUN checking */
877 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
878 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
879 if (retval != ERROR_OK)
880 return retval;
881 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
882 if (retval != ERROR_OK)
883 return retval;
884
885 dap_syssec(dap);
886
887 /* check that we support packed transfers */
888 uint32_t csw;
889
890 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
891 if (retval != ERROR_OK)
892 return retval;
893
894 retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
895 if (retval != ERROR_OK)
896 return retval;
897
898 retval = dap_run(dap);
899 if (retval != ERROR_OK)
900 return retval;
901
902 if (csw & CSW_ADDRINC_PACKED)
903 dap->packed_transfers = true;
904 else
905 dap->packed_transfers = false;
906
907 LOG_DEBUG("MEM_AP Packed Transfers: %s",
908 dap->packed_transfers ? "enabled" : "disabled");
909
910 return ERROR_OK;
911 }
912
913 /* CID interpretation -- see ARM IHI 0029B section 3
914 * and ARM IHI 0031A table 13-3.
915 */
916 static const char *class_description[16] = {
917 "Reserved", "ROM table", "Reserved", "Reserved",
918 "Reserved", "Reserved", "Reserved", "Reserved",
919 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
920 "Reserved", "OptimoDE DESS",
921 "Generic IP component", "PrimeCell or System component"
922 };
923
924 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
925 {
926 return cid3 == 0xb1 && cid2 == 0x05
927 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
928 }
929
930 /*
931 * This function checks the ID for each access port to find the requested Access Port type
932 */
933 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
934 {
935 int ap;
936
937 /* Maximum AP number is 255 since the SELECT register is 8 bits */
938 for (ap = 0; ap <= 255; ap++) {
939
940 /* read the IDR register of the Access Port */
941 uint32_t id_val = 0;
942 dap_ap_select(dap, ap);
943
944 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
945 if (retval != ERROR_OK)
946 return retval;
947
948 retval = dap_run(dap);
949
950 /* IDR bits:
951 * 31-28 : Revision
952 * 27-24 : JEDEC bank (0x4 for ARM)
953 * 23-17 : JEDEC code (0x3B for ARM)
954 * 16 : Mem-AP
955 * 15-8 : Reserved
956 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
957 */
958
959 /* Reading register for a non-existant AP should not cause an error,
960 * but just to be sure, try to continue searching if an error does happen.
961 */
962 if ((retval == ERROR_OK) && /* Register read success */
963 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
964 ((id_val & 0xFF) == type_to_find)) { /* type matches*/
965
966 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08X)",
967 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
968 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
969 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
970 ap, id_val);
971
972 *ap_num_out = ap;
973 return ERROR_OK;
974 }
975 }
976
977 LOG_DEBUG("No %s found",
978 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
979 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
980 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
981 return ERROR_FAIL;
982 }
983
984 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
985 uint32_t *out_dbgbase, uint32_t *out_apid)
986 {
987 uint32_t ap_old;
988 int retval;
989 uint32_t dbgbase, apid;
990
991 /* AP address is in bits 31:24 of DP_SELECT */
992 if (ap >= 256)
993 return ERROR_COMMAND_SYNTAX_ERROR;
994
995 ap_old = dap->ap_current;
996 dap_ap_select(dap, ap);
997
998 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
999 if (retval != ERROR_OK)
1000 return retval;
1001 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1002 if (retval != ERROR_OK)
1003 return retval;
1004 retval = dap_run(dap);
1005 if (retval != ERROR_OK)
1006 return retval;
1007
1008 /* Excavate the device ID code */
1009 struct jtag_tap *tap = dap->jtag_info->tap;
1010 while (tap != NULL) {
1011 if (tap->hasidcode)
1012 break;
1013 tap = tap->next_tap;
1014 }
1015 if (tap == NULL || !tap->hasidcode)
1016 return ERROR_OK;
1017
1018 dap_ap_select(dap, ap_old);
1019
1020 /* The asignment happens only here to prevent modification of these
1021 * values before they are certain. */
1022 *out_dbgbase = dbgbase;
1023 *out_apid = apid;
1024
1025 return ERROR_OK;
1026 }
1027
1028 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1029 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1030 {
1031 uint32_t ap_old;
1032 uint32_t romentry, entry_offset = 0, component_base, devtype;
1033 int retval = ERROR_FAIL;
1034
1035 if (ap >= 256)
1036 return ERROR_COMMAND_SYNTAX_ERROR;
1037
1038 ap_old = dap->ap_current;
1039 dap_ap_select(dap, ap);
1040
1041 do {
1042 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1043 entry_offset, &romentry);
1044 if (retval != ERROR_OK)
1045 return retval;
1046
1047 component_base = (dbgbase & 0xFFFFF000)
1048 + (romentry & 0xFFFFF000);
1049
1050 if (romentry & 0x1) {
1051 retval = mem_ap_read_atomic_u32(dap,
1052 (component_base & 0xfffff000) | 0xfcc,
1053 &devtype);
1054 if (retval != ERROR_OK)
1055 return retval;
1056 if ((devtype & 0xff) == type) {
1057 *addr = component_base;
1058 retval = ERROR_OK;
1059 break;
1060 }
1061 }
1062 entry_offset += 4;
1063 } while (romentry > 0);
1064
1065 dap_ap_select(dap, ap_old);
1066
1067 return retval;
1068 }
1069
1070 static int dap_info_command(struct command_context *cmd_ctx,
1071 struct adiv5_dap *dap, int ap)
1072 {
1073 int retval;
1074 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1075 int romtable_present = 0;
1076 uint8_t mem_ap;
1077 uint32_t ap_old;
1078
1079 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1080 if (retval != ERROR_OK)
1081 return retval;
1082
1083 ap_old = dap->ap_current;
1084 dap_ap_select(dap, ap);
1085
1086 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1087 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1088 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1089 if (apid) {
1090 switch (apid&0x0F) {
1091 case 0:
1092 command_print(cmd_ctx, "\tType is JTAG-AP");
1093 break;
1094 case 1:
1095 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1096 break;
1097 case 2:
1098 command_print(cmd_ctx, "\tType is MEM-AP APB");
1099 break;
1100 default:
1101 command_print(cmd_ctx, "\tUnknown AP type");
1102 break;
1103 }
1104
1105 /* NOTE: a MEM-AP may have a single CoreSight component that's
1106 * not a ROM table ... or have no such components at all.
1107 */
1108 if (mem_ap)
1109 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1110 } else
1111 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1112
1113 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1114 if (romtable_present) {
1115 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1116 uint16_t entry_offset;
1117
1118 /* bit 16 of apid indicates a memory access port */
1119 if (dbgbase & 0x02)
1120 command_print(cmd_ctx, "\tValid ROM table present");
1121 else
1122 command_print(cmd_ctx, "\tROM table in legacy format");
1123
1124 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1125 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1126 if (retval != ERROR_OK)
1127 return retval;
1128 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1129 if (retval != ERROR_OK)
1130 return retval;
1131 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1132 if (retval != ERROR_OK)
1133 return retval;
1134 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1135 if (retval != ERROR_OK)
1136 return retval;
1137 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1138 if (retval != ERROR_OK)
1139 return retval;
1140 retval = dap_run(dap);
1141 if (retval != ERROR_OK)
1142 return retval;
1143
1144 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1145 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1146 ", CID2 0x%2.2x"
1147 ", CID1 0x%2.2x"
1148 ", CID0 0x%2.2x",
1149 (unsigned) cid3, (unsigned)cid2,
1150 (unsigned) cid1, (unsigned) cid0);
1151 if (memtype & 0x01)
1152 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1153 else
1154 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1155 "Dedicated debug bus.");
1156
1157 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1158 entry_offset = 0;
1159 do {
1160 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1161 if (retval != ERROR_OK)
1162 return retval;
1163 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1164 if (romentry & 0x01) {
1165 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1166 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1167 uint32_t component_base;
1168 unsigned part_num;
1169 char *type, *full;
1170
1171 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1172
1173 /* IDs are in last 4K section */
1174 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1175 if (retval != ERROR_OK)
1176 return retval;
1177 c_pid0 &= 0xff;
1178 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1179 if (retval != ERROR_OK)
1180 return retval;
1181 c_pid1 &= 0xff;
1182 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1183 if (retval != ERROR_OK)
1184 return retval;
1185 c_pid2 &= 0xff;
1186 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1187 if (retval != ERROR_OK)
1188 return retval;
1189 c_pid3 &= 0xff;
1190 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1191 if (retval != ERROR_OK)
1192 return retval;
1193 c_pid4 &= 0xff;
1194
1195 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1196 if (retval != ERROR_OK)
1197 return retval;
1198 c_cid0 &= 0xff;
1199 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1200 if (retval != ERROR_OK)
1201 return retval;
1202 c_cid1 &= 0xff;
1203 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1204 if (retval != ERROR_OK)
1205 return retval;
1206 c_cid2 &= 0xff;
1207 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1208 if (retval != ERROR_OK)
1209 return retval;
1210 c_cid3 &= 0xff;
1211
1212 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1213 "start address 0x%" PRIx32, component_base,
1214 /* component may take multiple 4K pages */
1215 component_base - 0x1000*(c_pid4 >> 4));
1216 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1217 (int) (c_cid1 >> 4) & 0xf,
1218 /* See ARM IHI 0029B Table 3-3 */
1219 class_description[(c_cid1 >> 4) & 0xf]);
1220
1221 /* CoreSight component? */
1222 if (((c_cid1 >> 4) & 0x0f) == 9) {
1223 uint32_t devtype;
1224 unsigned minor;
1225 char *major = "Reserved", *subtype = "Reserved";
1226
1227 retval = mem_ap_read_atomic_u32(dap,
1228 (component_base & 0xfffff000) | 0xfcc,
1229 &devtype);
1230 if (retval != ERROR_OK)
1231 return retval;
1232 minor = (devtype >> 4) & 0x0f;
1233 switch (devtype & 0x0f) {
1234 case 0:
1235 major = "Miscellaneous";
1236 switch (minor) {
1237 case 0:
1238 subtype = "other";
1239 break;
1240 case 4:
1241 subtype = "Validation component";
1242 break;
1243 }
1244 break;
1245 case 1:
1246 major = "Trace Sink";
1247 switch (minor) {
1248 case 0:
1249 subtype = "other";
1250 break;
1251 case 1:
1252 subtype = "Port";
1253 break;
1254 case 2:
1255 subtype = "Buffer";
1256 break;
1257 }
1258 break;
1259 case 2:
1260 major = "Trace Link";
1261 switch (minor) {
1262 case 0:
1263 subtype = "other";
1264 break;
1265 case 1:
1266 subtype = "Funnel, router";
1267 break;
1268 case 2:
1269 subtype = "Filter";
1270 break;
1271 case 3:
1272 subtype = "FIFO, buffer";
1273 break;
1274 }
1275 break;
1276 case 3:
1277 major = "Trace Source";
1278 switch (minor) {
1279 case 0:
1280 subtype = "other";
1281 break;
1282 case 1:
1283 subtype = "Processor";
1284 break;
1285 case 2:
1286 subtype = "DSP";
1287 break;
1288 case 3:
1289 subtype = "Engine/Coprocessor";
1290 break;
1291 case 4:
1292 subtype = "Bus";
1293 break;
1294 }
1295 break;
1296 case 4:
1297 major = "Debug Control";
1298 switch (minor) {
1299 case 0:
1300 subtype = "other";
1301 break;
1302 case 1:
1303 subtype = "Trigger Matrix";
1304 break;
1305 case 2:
1306 subtype = "Debug Auth";
1307 break;
1308 }
1309 break;
1310 case 5:
1311 major = "Debug Logic";
1312 switch (minor) {
1313 case 0:
1314 subtype = "other";
1315 break;
1316 case 1:
1317 subtype = "Processor";
1318 break;
1319 case 2:
1320 subtype = "DSP";
1321 break;
1322 case 3:
1323 subtype = "Engine/Coprocessor";
1324 break;
1325 }
1326 break;
1327 }
1328 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1329 (unsigned) (devtype & 0xff),
1330 major, subtype);
1331 /* REVISIT also show 0xfc8 DevId */
1332 }
1333
1334 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1335 command_print(cmd_ctx,
1336 "\t\tCID3 0%2.2x"
1337 ", CID2 0%2.2x"
1338 ", CID1 0%2.2x"
1339 ", CID0 0%2.2x",
1340 (int) c_cid3,
1341 (int) c_cid2,
1342 (int)c_cid1,
1343 (int)c_cid0);
1344 command_print(cmd_ctx,
1345 "\t\tPeripheral ID[4..0] = hex "
1346 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1347 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1348 (int) c_pid1, (int) c_pid0);
1349
1350 /* Part number interpretations are from Cortex
1351 * core specs, the CoreSight components TRM
1352 * (ARM DDI 0314H), CoreSight System Design
1353 * Guide (ARM DGI 0012D) and ETM specs; also
1354 * from chip observation (e.g. TI SDTI).
1355 */
1356 part_num = (c_pid0 & 0xff);
1357 part_num |= (c_pid1 & 0x0f) << 8;
1358 switch (part_num) {
1359 case 0x000:
1360 type = "Cortex-M3 NVIC";
1361 full = "(Interrupt Controller)";
1362 break;
1363 case 0x001:
1364 type = "Cortex-M3 ITM";
1365 full = "(Instrumentation Trace Module)";
1366 break;
1367 case 0x002:
1368 type = "Cortex-M3 DWT";
1369 full = "(Data Watchpoint and Trace)";
1370 break;
1371 case 0x003:
1372 type = "Cortex-M3 FBP";
1373 full = "(Flash Patch and Breakpoint)";
1374 break;
1375 case 0x00c:
1376 type = "Cortex-M4 SCS";
1377 full = "(System Control Space)";
1378 break;
1379 case 0x00d:
1380 type = "CoreSight ETM11";
1381 full = "(Embedded Trace)";
1382 break;
1383 /* case 0x113: what? */
1384 case 0x120: /* from OMAP3 memmap */
1385 type = "TI SDTI";
1386 full = "(System Debug Trace Interface)";
1387 break;
1388 case 0x343: /* from OMAP3 memmap */
1389 type = "TI DAPCTL";
1390 full = "";
1391 break;
1392 case 0x906:
1393 type = "Coresight CTI";
1394 full = "(Cross Trigger)";
1395 break;
1396 case 0x907:
1397 type = "Coresight ETB";
1398 full = "(Trace Buffer)";
1399 break;
1400 case 0x908:
1401 type = "Coresight CSTF";
1402 full = "(Trace Funnel)";
1403 break;
1404 case 0x910:
1405 type = "CoreSight ETM9";
1406 full = "(Embedded Trace)";
1407 break;
1408 case 0x912:
1409 type = "Coresight TPIU";
1410 full = "(Trace Port Interface Unit)";
1411 break;
1412 case 0x921:
1413 type = "Cortex-A8 ETM";
1414 full = "(Embedded Trace)";
1415 break;
1416 case 0x922:
1417 type = "Cortex-A8 CTI";
1418 full = "(Cross Trigger)";
1419 break;
1420 case 0x923:
1421 type = "Cortex-M3 TPIU";
1422 full = "(Trace Port Interface Unit)";
1423 break;
1424 case 0x924:
1425 type = "Cortex-M3 ETM";
1426 full = "(Embedded Trace)";
1427 break;
1428 case 0x925:
1429 type = "Cortex-M4 ETM";
1430 full = "(Embedded Trace)";
1431 break;
1432 case 0x930:
1433 type = "Cortex-R4 ETM";
1434 full = "(Embedded Trace)";
1435 break;
1436 case 0x9a1:
1437 type = "Cortex-M4 TPUI";
1438 full = "(Trace Port Interface Unit)";
1439 break;
1440 case 0xc08:
1441 type = "Cortex-A8 Debug";
1442 full = "(Debug Unit)";
1443 break;
1444 default:
1445 type = "-*- unrecognized -*-";
1446 full = "";
1447 break;
1448 }
1449 command_print(cmd_ctx, "\t\tPart is %s %s",
1450 type, full);
1451 } else {
1452 if (romentry)
1453 command_print(cmd_ctx, "\t\tComponent not present");
1454 else
1455 command_print(cmd_ctx, "\t\tEnd of ROM table");
1456 }
1457 entry_offset += 4;
1458 } while (romentry > 0);
1459 } else
1460 command_print(cmd_ctx, "\tNo ROM table present");
1461 dap_ap_select(dap, ap_old);
1462
1463 return ERROR_OK;
1464 }
1465
1466 COMMAND_HANDLER(handle_dap_info_command)
1467 {
1468 struct target *target = get_current_target(CMD_CTX);
1469 struct arm *arm = target_to_arm(target);
1470 struct adiv5_dap *dap = arm->dap;
1471 uint32_t apsel;
1472
1473 switch (CMD_ARGC) {
1474 case 0:
1475 apsel = dap->apsel;
1476 break;
1477 case 1:
1478 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1479 break;
1480 default:
1481 return ERROR_COMMAND_SYNTAX_ERROR;
1482 }
1483
1484 return dap_info_command(CMD_CTX, dap, apsel);
1485 }
1486
1487 COMMAND_HANDLER(dap_baseaddr_command)
1488 {
1489 struct target *target = get_current_target(CMD_CTX);
1490 struct arm *arm = target_to_arm(target);
1491 struct adiv5_dap *dap = arm->dap;
1492
1493 uint32_t apsel, baseaddr;
1494 int retval;
1495
1496 switch (CMD_ARGC) {
1497 case 0:
1498 apsel = dap->apsel;
1499 break;
1500 case 1:
1501 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1502 /* AP address is in bits 31:24 of DP_SELECT */
1503 if (apsel >= 256)
1504 return ERROR_COMMAND_SYNTAX_ERROR;
1505 break;
1506 default:
1507 return ERROR_COMMAND_SYNTAX_ERROR;
1508 }
1509
1510 dap_ap_select(dap, apsel);
1511
1512 /* NOTE: assumes we're talking to a MEM-AP, which
1513 * has a base address. There are other kinds of AP,
1514 * though they're not common for now. This should
1515 * use the ID register to verify it's a MEM-AP.
1516 */
1517 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1518 if (retval != ERROR_OK)
1519 return retval;
1520 retval = dap_run(dap);
1521 if (retval != ERROR_OK)
1522 return retval;
1523
1524 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1525
1526 return retval;
1527 }
1528
1529 COMMAND_HANDLER(dap_memaccess_command)
1530 {
1531 struct target *target = get_current_target(CMD_CTX);
1532 struct arm *arm = target_to_arm(target);
1533 struct adiv5_dap *dap = arm->dap;
1534
1535 uint32_t memaccess_tck;
1536
1537 switch (CMD_ARGC) {
1538 case 0:
1539 memaccess_tck = dap->memaccess_tck;
1540 break;
1541 case 1:
1542 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1543 break;
1544 default:
1545 return ERROR_COMMAND_SYNTAX_ERROR;
1546 }
1547 dap->memaccess_tck = memaccess_tck;
1548
1549 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1550 dap->memaccess_tck);
1551
1552 return ERROR_OK;
1553 }
1554
1555 COMMAND_HANDLER(dap_apsel_command)
1556 {
1557 struct target *target = get_current_target(CMD_CTX);
1558 struct arm *arm = target_to_arm(target);
1559 struct adiv5_dap *dap = arm->dap;
1560
1561 uint32_t apsel, apid;
1562 int retval;
1563
1564 switch (CMD_ARGC) {
1565 case 0:
1566 apsel = 0;
1567 break;
1568 case 1:
1569 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1570 /* AP address is in bits 31:24 of DP_SELECT */
1571 if (apsel >= 256)
1572 return ERROR_COMMAND_SYNTAX_ERROR;
1573 break;
1574 default:
1575 return ERROR_COMMAND_SYNTAX_ERROR;
1576 }
1577
1578 dap->apsel = apsel;
1579 dap_ap_select(dap, apsel);
1580
1581 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1582 if (retval != ERROR_OK)
1583 return retval;
1584 retval = dap_run(dap);
1585 if (retval != ERROR_OK)
1586 return retval;
1587
1588 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1589 apsel, apid);
1590
1591 return retval;
1592 }
1593
1594 COMMAND_HANDLER(dap_apcsw_command)
1595 {
1596 struct target *target = get_current_target(CMD_CTX);
1597 struct arm *arm = target_to_arm(target);
1598 struct adiv5_dap *dap = arm->dap;
1599
1600 uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1601
1602 switch (CMD_ARGC) {
1603 case 0:
1604 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1605 (dap->apsel), apcsw);
1606 break;
1607 case 1:
1608 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1609 /* AP address is in bits 31:24 of DP_SELECT */
1610 if (sprot > 1)
1611 return ERROR_COMMAND_SYNTAX_ERROR;
1612 if (sprot)
1613 apcsw |= CSW_SPROT;
1614 else
1615 apcsw &= ~CSW_SPROT;
1616 break;
1617 default:
1618 return ERROR_COMMAND_SYNTAX_ERROR;
1619 }
1620 dap->apcsw[dap->apsel] = apcsw;
1621
1622 return 0;
1623 }
1624
1625
1626
1627 COMMAND_HANDLER(dap_apid_command)
1628 {
1629 struct target *target = get_current_target(CMD_CTX);
1630 struct arm *arm = target_to_arm(target);
1631 struct adiv5_dap *dap = arm->dap;
1632
1633 uint32_t apsel, apid;
1634 int retval;
1635
1636 switch (CMD_ARGC) {
1637 case 0:
1638 apsel = dap->apsel;
1639 break;
1640 case 1:
1641 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1642 /* AP address is in bits 31:24 of DP_SELECT */
1643 if (apsel >= 256)
1644 return ERROR_COMMAND_SYNTAX_ERROR;
1645 break;
1646 default:
1647 return ERROR_COMMAND_SYNTAX_ERROR;
1648 }
1649
1650 dap_ap_select(dap, apsel);
1651
1652 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1653 if (retval != ERROR_OK)
1654 return retval;
1655 retval = dap_run(dap);
1656 if (retval != ERROR_OK)
1657 return retval;
1658
1659 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1660
1661 return retval;
1662 }
1663
1664 static const struct command_registration dap_commands[] = {
1665 {
1666 .name = "info",
1667 .handler = handle_dap_info_command,
1668 .mode = COMMAND_EXEC,
1669 .help = "display ROM table for MEM-AP "
1670 "(default currently selected AP)",
1671 .usage = "[ap_num]",
1672 },
1673 {
1674 .name = "apsel",
1675 .handler = dap_apsel_command,
1676 .mode = COMMAND_EXEC,
1677 .help = "Set the currently selected AP (default 0) "
1678 "and display the result",
1679 .usage = "[ap_num]",
1680 },
1681 {
1682 .name = "apcsw",
1683 .handler = dap_apcsw_command,
1684 .mode = COMMAND_EXEC,
1685 .help = "Set csw access bit ",
1686 .usage = "[sprot]",
1687 },
1688
1689 {
1690 .name = "apid",
1691 .handler = dap_apid_command,
1692 .mode = COMMAND_EXEC,
1693 .help = "return ID register from AP "
1694 "(default currently selected AP)",
1695 .usage = "[ap_num]",
1696 },
1697 {
1698 .name = "baseaddr",
1699 .handler = dap_baseaddr_command,
1700 .mode = COMMAND_EXEC,
1701 .help = "return debug base address from MEM-AP "
1702 "(default currently selected AP)",
1703 .usage = "[ap_num]",
1704 },
1705 {
1706 .name = "memaccess",
1707 .handler = dap_memaccess_command,
1708 .mode = COMMAND_EXEC,
1709 .help = "set/get number of extra tck for MEM-AP memory "
1710 "bus access [0-255]",
1711 .usage = "[cycles]",
1712 },
1713 COMMAND_REGISTRATION_DONE
1714 };
1715
1716 const struct command_registration dap_command_handlers[] = {
1717 {
1718 .name = "dap",
1719 .mode = COMMAND_EXEC,
1720 .help = "DAP command group",
1721 .usage = "",
1722 .chain = dap_commands,
1723 },
1724 COMMAND_REGISTRATION_DONE
1725 };
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