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arm_adi_v5: Add part number for TI MSP432P401R
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "jtag/interface.h"
76 #include "arm.h"
77 #include "arm_adi_v5.h"
78 #include <helper/jep106.h>
79 #include <helper/time_support.h>
80 #include <helper/list.h>
81
82 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83
84 /*
85 uint32_t tar_block_size(uint32_t address)
86 Return the largest block starting at address that does not cross a tar block size alignment boundary
87 */
88 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
89 {
90 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 }
92
93 /***************************************************************************
94 * *
95 * DP and MEM-AP register access through APACC and DPACC *
96 * *
97 ***************************************************************************/
98
99 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
100 {
101 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
102 ap->csw_default;
103
104 if (csw != ap->csw_value) {
105 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
106 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
107 if (retval != ERROR_OK)
108 return retval;
109 ap->csw_value = csw;
110 }
111 return ERROR_OK;
112 }
113
114 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
115 {
116 if (tar != ap->tar_value ||
117 (ap->csw_value & CSW_ADDRINC_MASK)) {
118 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
119 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
120 if (retval != ERROR_OK)
121 return retval;
122 ap->tar_value = tar;
123 }
124 return ERROR_OK;
125 }
126
127 /**
128 * Queue transactions setting up transfer parameters for the
129 * currently selected MEM-AP.
130 *
131 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
132 * initiate data reads or writes using memory or peripheral addresses.
133 * If the CSW is configured for it, the TAR may be automatically
134 * incremented after each transfer.
135 *
136 * @param ap The MEM-AP.
137 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
138 * matches the cached value, the register is not changed.
139 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
140 * matches the cached address, the register is not changed.
141 *
142 * @return ERROR_OK if the transaction was properly queued, else a fault code.
143 */
144 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
145 {
146 int retval;
147 retval = mem_ap_setup_csw(ap, csw);
148 if (retval != ERROR_OK)
149 return retval;
150 retval = mem_ap_setup_tar(ap, tar);
151 if (retval != ERROR_OK)
152 return retval;
153 return ERROR_OK;
154 }
155
156 /**
157 * Asynchronous (queued) read of a word from memory or a system register.
158 *
159 * @param ap The MEM-AP to access.
160 * @param address Address of the 32-bit word to read; it must be
161 * readable by the currently selected MEM-AP.
162 * @param value points to where the word will be stored when the
163 * transaction queue is flushed (assuming no errors).
164 *
165 * @return ERROR_OK for success. Otherwise a fault code.
166 */
167 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
168 uint32_t *value)
169 {
170 int retval;
171
172 /* Use banked addressing (REG_BDx) to avoid some link traffic
173 * (updating TAR) when reading several consecutive addresses.
174 */
175 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
176 address & 0xFFFFFFF0);
177 if (retval != ERROR_OK)
178 return retval;
179
180 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
181 }
182
183 /**
184 * Synchronous read of a word from memory or a system register.
185 * As a side effect, this flushes any queued transactions.
186 *
187 * @param ap The MEM-AP to access.
188 * @param address Address of the 32-bit word to read; it must be
189 * readable by the currently selected MEM-AP.
190 * @param value points to where the result will be stored.
191 *
192 * @return ERROR_OK for success; *value holds the result.
193 * Otherwise a fault code.
194 */
195 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
196 uint32_t *value)
197 {
198 int retval;
199
200 retval = mem_ap_read_u32(ap, address, value);
201 if (retval != ERROR_OK)
202 return retval;
203
204 return dap_run(ap->dap);
205 }
206
207 /**
208 * Asynchronous (queued) write of a word to memory or a system register.
209 *
210 * @param ap The MEM-AP to access.
211 * @param address Address to be written; it must be writable by
212 * the currently selected MEM-AP.
213 * @param value Word that will be written to the address when transaction
214 * queue is flushed (assuming no errors).
215 *
216 * @return ERROR_OK for success. Otherwise a fault code.
217 */
218 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
219 uint32_t value)
220 {
221 int retval;
222
223 /* Use banked addressing (REG_BDx) to avoid some link traffic
224 * (updating TAR) when writing several consecutive addresses.
225 */
226 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
227 address & 0xFFFFFFF0);
228 if (retval != ERROR_OK)
229 return retval;
230
231 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
232 value);
233 }
234
235 /**
236 * Synchronous write of a word to memory or a system register.
237 * As a side effect, this flushes any queued transactions.
238 *
239 * @param ap The MEM-AP to access.
240 * @param address Address to be written; it must be writable by
241 * the currently selected MEM-AP.
242 * @param value Word that will be written.
243 *
244 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
245 */
246 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
247 uint32_t value)
248 {
249 int retval = mem_ap_write_u32(ap, address, value);
250
251 if (retval != ERROR_OK)
252 return retval;
253
254 return dap_run(ap->dap);
255 }
256
257 /**
258 * Synchronous write of a block of memory, using a specific access size.
259 *
260 * @param ap The MEM-AP to access.
261 * @param buffer The data buffer to write. No particular alignment is assumed.
262 * @param size Which access size to use, in bytes. 1, 2 or 4.
263 * @param count The number of writes to do (in size units, not bytes).
264 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
265 * @param addrinc Whether the target address should be increased for each write or not. This
266 * should normally be true, except when writing to e.g. a FIFO.
267 * @return ERROR_OK on success, otherwise an error code.
268 */
269 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
270 uint32_t address, bool addrinc)
271 {
272 struct adiv5_dap *dap = ap->dap;
273 size_t nbytes = size * count;
274 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
275 uint32_t csw_size;
276 uint32_t addr_xor;
277 int retval;
278
279 /* TI BE-32 Quirks mode:
280 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
281 * size write address bytes written in order
282 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
283 * 2 TAR ^ 2 (val >> 8), (val)
284 * 1 TAR ^ 3 (val)
285 * For example, if you attempt to write a single byte to address 0, the processor
286 * will actually write a byte to address 3.
287 *
288 * To make writes of size < 4 work as expected, we xor a value with the address before
289 * setting the TAP, and we set the TAP after every transfer rather then relying on
290 * address increment. */
291
292 if (size == 4) {
293 csw_size = CSW_32BIT;
294 addr_xor = 0;
295 } else if (size == 2) {
296 csw_size = CSW_16BIT;
297 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
298 } else if (size == 1) {
299 csw_size = CSW_8BIT;
300 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
301 } else {
302 return ERROR_TARGET_UNALIGNED_ACCESS;
303 }
304
305 if (ap->unaligned_access_bad && (address % size != 0))
306 return ERROR_TARGET_UNALIGNED_ACCESS;
307
308 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
309 if (retval != ERROR_OK)
310 return retval;
311
312 while (nbytes > 0) {
313 uint32_t this_size = size;
314
315 /* Select packed transfer if possible */
316 if (addrinc && ap->packed_transfers && nbytes >= 4
317 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
318 this_size = 4;
319 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
320 } else {
321 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
322 }
323
324 if (retval != ERROR_OK)
325 break;
326
327 /* How many source bytes each transfer will consume, and their location in the DRW,
328 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
329 uint32_t outvalue = 0;
330 if (dap->ti_be_32_quirks) {
331 switch (this_size) {
332 case 4:
333 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
334 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
335 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
336 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
337 break;
338 case 2:
339 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
340 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
341 break;
342 case 1:
343 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
344 break;
345 }
346 } else {
347 switch (this_size) {
348 case 4:
349 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
350 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
351 case 2:
352 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
353 case 1:
354 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
355 }
356 }
357
358 nbytes -= this_size;
359
360 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
361 if (retval != ERROR_OK)
362 break;
363
364 /* Rewrite TAR if it wrapped or we're xoring addresses */
365 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
366 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
367 if (retval != ERROR_OK)
368 break;
369 }
370 }
371
372 /* REVISIT: Might want to have a queued version of this function that does not run. */
373 if (retval == ERROR_OK)
374 retval = dap_run(dap);
375
376 if (retval != ERROR_OK) {
377 uint32_t tar;
378 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
379 && dap_run(dap) == ERROR_OK)
380 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
381 else
382 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
383 }
384
385 return retval;
386 }
387
388 /**
389 * Synchronous read of a block of memory, using a specific access size.
390 *
391 * @param ap The MEM-AP to access.
392 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
393 * @param size Which access size to use, in bytes. 1, 2 or 4.
394 * @param count The number of reads to do (in size units, not bytes).
395 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
396 * @param addrinc Whether the target address should be increased after each read or not. This
397 * should normally be true, except when reading from e.g. a FIFO.
398 * @return ERROR_OK on success, otherwise an error code.
399 */
400 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
401 uint32_t adr, bool addrinc)
402 {
403 struct adiv5_dap *dap = ap->dap;
404 size_t nbytes = size * count;
405 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
406 uint32_t csw_size;
407 uint32_t address = adr;
408 int retval;
409
410 /* TI BE-32 Quirks mode:
411 * Reads on big-endian TMS570 behave strangely differently than writes.
412 * They read from the physical address requested, but with DRW byte-reversed.
413 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
414 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
415 * so avoid them. */
416
417 if (size == 4)
418 csw_size = CSW_32BIT;
419 else if (size == 2)
420 csw_size = CSW_16BIT;
421 else if (size == 1)
422 csw_size = CSW_8BIT;
423 else
424 return ERROR_TARGET_UNALIGNED_ACCESS;
425
426 if (ap->unaligned_access_bad && (adr % size != 0))
427 return ERROR_TARGET_UNALIGNED_ACCESS;
428
429 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
430 * over-allocation if packed transfers are going to be used, but determining the real need at
431 * this point would be messy. */
432 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
433 uint32_t *read_ptr = read_buf;
434 if (read_buf == NULL) {
435 LOG_ERROR("Failed to allocate read buffer");
436 return ERROR_FAIL;
437 }
438
439 retval = mem_ap_setup_tar(ap, address);
440 if (retval != ERROR_OK) {
441 free(read_buf);
442 return retval;
443 }
444
445 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
446 * useful bytes it contains, and their location in the word, depends on the type of transfer
447 * and alignment. */
448 while (nbytes > 0) {
449 uint32_t this_size = size;
450
451 /* Select packed transfer if possible */
452 if (addrinc && ap->packed_transfers && nbytes >= 4
453 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
454 this_size = 4;
455 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
456 } else {
457 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
458 }
459 if (retval != ERROR_OK)
460 break;
461
462 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
463 if (retval != ERROR_OK)
464 break;
465
466 nbytes -= this_size;
467 address += this_size;
468
469 /* Rewrite TAR if it wrapped */
470 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
471 retval = mem_ap_setup_tar(ap, address);
472 if (retval != ERROR_OK)
473 break;
474 }
475 }
476
477 if (retval == ERROR_OK)
478 retval = dap_run(dap);
479
480 /* Restore state */
481 address = adr;
482 nbytes = size * count;
483 read_ptr = read_buf;
484
485 /* If something failed, read TAR to find out how much data was successfully read, so we can
486 * at least give the caller what we have. */
487 if (retval != ERROR_OK) {
488 uint32_t tar;
489 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
490 && dap_run(dap) == ERROR_OK) {
491 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
492 if (nbytes > tar - address)
493 nbytes = tar - address;
494 } else {
495 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
496 nbytes = 0;
497 }
498 }
499
500 /* Replay loop to populate caller's buffer from the correct word and byte lane */
501 while (nbytes > 0) {
502 uint32_t this_size = size;
503
504 if (addrinc && ap->packed_transfers && nbytes >= 4
505 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
506 this_size = 4;
507 }
508
509 if (dap->ti_be_32_quirks) {
510 switch (this_size) {
511 case 4:
512 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
513 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
514 case 2:
515 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
516 case 1:
517 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
518 }
519 } else {
520 switch (this_size) {
521 case 4:
522 *buffer++ = *read_ptr >> 8 * (address++ & 3);
523 *buffer++ = *read_ptr >> 8 * (address++ & 3);
524 case 2:
525 *buffer++ = *read_ptr >> 8 * (address++ & 3);
526 case 1:
527 *buffer++ = *read_ptr >> 8 * (address++ & 3);
528 }
529 }
530
531 read_ptr++;
532 nbytes -= this_size;
533 }
534
535 free(read_buf);
536 return retval;
537 }
538
539 int mem_ap_read_buf(struct adiv5_ap *ap,
540 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
541 {
542 return mem_ap_read(ap, buffer, size, count, address, true);
543 }
544
545 int mem_ap_write_buf(struct adiv5_ap *ap,
546 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
547 {
548 return mem_ap_write(ap, buffer, size, count, address, true);
549 }
550
551 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
552 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
553 {
554 return mem_ap_read(ap, buffer, size, count, address, false);
555 }
556
557 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
558 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
559 {
560 return mem_ap_write(ap, buffer, size, count, address, false);
561 }
562
563 /*--------------------------------------------------------------------------*/
564
565
566 #define DAP_POWER_DOMAIN_TIMEOUT (10)
567
568 /* FIXME don't import ... just initialize as
569 * part of DAP transport setup
570 */
571 extern const struct dap_ops jtag_dp_ops;
572
573 /*--------------------------------------------------------------------------*/
574
575 /**
576 * Create a new DAP
577 */
578 struct adiv5_dap *dap_init(void)
579 {
580 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
581 int i;
582 /* Set up with safe defaults */
583 for (i = 0; i <= 255; i++) {
584 dap->ap[i].dap = dap;
585 dap->ap[i].ap_num = i;
586 /* memaccess_tck max is 255 */
587 dap->ap[i].memaccess_tck = 255;
588 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
589 dap->ap[i].tar_autoincr_block = (1<<10);
590 }
591 INIT_LIST_HEAD(&dap->cmd_journal);
592 return dap;
593 }
594
595 /**
596 * Initialize a DAP. This sets up the power domains, prepares the DP
597 * for further use and activates overrun checking.
598 *
599 * @param dap The DAP being initialized.
600 */
601 int dap_dp_init(struct adiv5_dap *dap)
602 {
603 int retval;
604
605 LOG_DEBUG(" ");
606 /* JTAG-DP or SWJ-DP, in JTAG mode
607 * ... for SWD mode this is patched as part
608 * of link switchover
609 * FIXME: This should already be setup by the respective transport specific DAP creation.
610 */
611 if (!dap->ops)
612 dap->ops = &jtag_dp_ops;
613
614 dap->select = DP_SELECT_INVALID;
615 dap->last_read = NULL;
616
617 for (size_t i = 0; i < 10; i++) {
618 /* DP initialization */
619
620 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
621 if (retval != ERROR_OK)
622 continue;
623
624 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
625 if (retval != ERROR_OK)
626 continue;
627
628 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
629 if (retval != ERROR_OK)
630 continue;
631
632 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
633 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
634 if (retval != ERROR_OK)
635 continue;
636
637 /* Check that we have debug power domains activated */
638 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
639 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
640 CDBGPWRUPACK, CDBGPWRUPACK,
641 DAP_POWER_DOMAIN_TIMEOUT);
642 if (retval != ERROR_OK)
643 continue;
644
645 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
646 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
647 CSYSPWRUPACK, CSYSPWRUPACK,
648 DAP_POWER_DOMAIN_TIMEOUT);
649 if (retval != ERROR_OK)
650 continue;
651
652 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
653 if (retval != ERROR_OK)
654 continue;
655
656 /* With debug power on we can activate OVERRUN checking */
657 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
658 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
659 if (retval != ERROR_OK)
660 continue;
661 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
662 if (retval != ERROR_OK)
663 continue;
664
665 retval = dap_run(dap);
666 if (retval != ERROR_OK)
667 continue;
668
669 break;
670 }
671
672 return retval;
673 }
674
675 /**
676 * Initialize a DAP. This sets up the power domains, prepares the DP
677 * for further use, and arranges to use AP #0 for all AP operations
678 * until dap_ap-select() changes that policy.
679 *
680 * @param ap The MEM-AP being initialized.
681 */
682 int mem_ap_init(struct adiv5_ap *ap)
683 {
684 /* check that we support packed transfers */
685 uint32_t csw, cfg;
686 int retval;
687 struct adiv5_dap *dap = ap->dap;
688
689 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
690 if (retval != ERROR_OK)
691 return retval;
692
693 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
694 if (retval != ERROR_OK)
695 return retval;
696
697 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
698 if (retval != ERROR_OK)
699 return retval;
700
701 retval = dap_run(dap);
702 if (retval != ERROR_OK)
703 return retval;
704
705 if (csw & CSW_ADDRINC_PACKED)
706 ap->packed_transfers = true;
707 else
708 ap->packed_transfers = false;
709
710 /* Packed transfers on TI BE-32 processors do not work correctly in
711 * many cases. */
712 if (dap->ti_be_32_quirks)
713 ap->packed_transfers = false;
714
715 LOG_DEBUG("MEM_AP Packed Transfers: %s",
716 ap->packed_transfers ? "enabled" : "disabled");
717
718 /* The ARM ADI spec leaves implementation-defined whether unaligned
719 * memory accesses work, only work partially, or cause a sticky error.
720 * On TI BE-32 processors, reads seem to return garbage in some bytes
721 * and unaligned writes seem to cause a sticky error.
722 * TODO: it would be nice to have a way to detect whether unaligned
723 * operations are supported on other processors. */
724 ap->unaligned_access_bad = dap->ti_be_32_quirks;
725
726 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
727 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
728
729 return ERROR_OK;
730 }
731
732 /* CID interpretation -- see ARM IHI 0029B section 3
733 * and ARM IHI 0031A table 13-3.
734 */
735 static const char *class_description[16] = {
736 "Reserved", "ROM table", "Reserved", "Reserved",
737 "Reserved", "Reserved", "Reserved", "Reserved",
738 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
739 "Reserved", "OptimoDE DESS",
740 "Generic IP component", "PrimeCell or System component"
741 };
742
743 static bool is_dap_cid_ok(uint32_t cid)
744 {
745 return (cid & 0xffff0fff) == 0xb105000d;
746 }
747
748 /*
749 * This function checks the ID for each access port to find the requested Access Port type
750 */
751 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
752 {
753 int ap_num;
754
755 /* Maximum AP number is 255 since the SELECT register is 8 bits */
756 for (ap_num = 0; ap_num <= 255; ap_num++) {
757
758 /* read the IDR register of the Access Port */
759 uint32_t id_val = 0;
760
761 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
762 if (retval != ERROR_OK)
763 return retval;
764
765 retval = dap_run(dap);
766
767 /* IDR bits:
768 * 31-28 : Revision
769 * 27-24 : JEDEC bank (0x4 for ARM)
770 * 23-17 : JEDEC code (0x3B for ARM)
771 * 16-13 : Class (0b1000=Mem-AP)
772 * 12-8 : Reserved
773 * 7-4 : AP Variant (non-zero for JTAG-AP)
774 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
775 */
776
777 /* Reading register for a non-existant AP should not cause an error,
778 * but just to be sure, try to continue searching if an error does happen.
779 */
780 if ((retval == ERROR_OK) && /* Register read success */
781 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
782 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
783
784 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
785 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
786 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
787 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
788 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
789 ap_num, id_val);
790
791 *ap_out = &dap->ap[ap_num];
792 return ERROR_OK;
793 }
794 }
795
796 LOG_DEBUG("No %s found",
797 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
798 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
799 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
800 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
801 return ERROR_FAIL;
802 }
803
804 int dap_get_debugbase(struct adiv5_ap *ap,
805 uint32_t *dbgbase, uint32_t *apid)
806 {
807 struct adiv5_dap *dap = ap->dap;
808 int retval;
809
810 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
811 if (retval != ERROR_OK)
812 return retval;
813 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
814 if (retval != ERROR_OK)
815 return retval;
816 retval = dap_run(dap);
817 if (retval != ERROR_OK)
818 return retval;
819
820 return ERROR_OK;
821 }
822
823 int dap_lookup_cs_component(struct adiv5_ap *ap,
824 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
825 {
826 uint32_t romentry, entry_offset = 0, component_base, devtype;
827 int retval;
828
829 *addr = 0;
830
831 do {
832 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
833 entry_offset, &romentry);
834 if (retval != ERROR_OK)
835 return retval;
836
837 component_base = (dbgbase & 0xFFFFF000)
838 + (romentry & 0xFFFFF000);
839
840 if (romentry & 0x1) {
841 uint32_t c_cid1;
842 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
843 if (retval != ERROR_OK) {
844 LOG_ERROR("Can't read component with base address 0x%" PRIx32
845 ", the corresponding core might be turned off", component_base);
846 return retval;
847 }
848 if (((c_cid1 >> 4) & 0x0f) == 1) {
849 retval = dap_lookup_cs_component(ap, component_base,
850 type, addr, idx);
851 if (retval == ERROR_OK)
852 break;
853 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
854 return retval;
855 }
856
857 retval = mem_ap_read_atomic_u32(ap,
858 (component_base & 0xfffff000) | 0xfcc,
859 &devtype);
860 if (retval != ERROR_OK)
861 return retval;
862 if ((devtype & 0xff) == type) {
863 if (!*idx) {
864 *addr = component_base;
865 break;
866 } else
867 (*idx)--;
868 }
869 }
870 entry_offset += 4;
871 } while (romentry > 0);
872
873 if (!*addr)
874 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
875
876 return ERROR_OK;
877 }
878
879 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
880 {
881 assert((component_base & 0xFFF) == 0);
882 assert(ap != NULL && cid != NULL && pid != NULL);
883
884 uint32_t cid0, cid1, cid2, cid3;
885 uint32_t pid0, pid1, pid2, pid3, pid4;
886 int retval;
887
888 /* IDs are in last 4K section */
889 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
890 if (retval != ERROR_OK)
891 return retval;
892 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
893 if (retval != ERROR_OK)
894 return retval;
895 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
896 if (retval != ERROR_OK)
897 return retval;
898 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
899 if (retval != ERROR_OK)
900 return retval;
901 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
902 if (retval != ERROR_OK)
903 return retval;
904 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
905 if (retval != ERROR_OK)
906 return retval;
907 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
908 if (retval != ERROR_OK)
909 return retval;
910 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
911 if (retval != ERROR_OK)
912 return retval;
913 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
914 if (retval != ERROR_OK)
915 return retval;
916
917 retval = dap_run(ap->dap);
918 if (retval != ERROR_OK)
919 return retval;
920
921 *cid = (cid3 & 0xff) << 24
922 | (cid2 & 0xff) << 16
923 | (cid1 & 0xff) << 8
924 | (cid0 & 0xff);
925 *pid = (uint64_t)(pid4 & 0xff) << 32
926 | (pid3 & 0xff) << 24
927 | (pid2 & 0xff) << 16
928 | (pid1 & 0xff) << 8
929 | (pid0 & 0xff);
930
931 return ERROR_OK;
932 }
933
934 /* The designer identity code is encoded as:
935 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
936 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
937 * a legacy ASCII Identity Code.
938 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
939 * JEP106 is a standard available from jedec.org
940 */
941
942 /* Part number interpretations are from Cortex
943 * core specs, the CoreSight components TRM
944 * (ARM DDI 0314H), CoreSight System Design
945 * Guide (ARM DGI 0012D) and ETM specs; also
946 * from chip observation (e.g. TI SDTI).
947 */
948
949 /* The legacy code only used the part number field to identify CoreSight peripherals.
950 * This meant that the same part number from two different manufacturers looked the same.
951 * It is desirable for all future additions to identify with both part number and JEP106.
952 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
953 */
954
955 #define ANY_ID 0x1000
956
957 #define ARM_ID 0x4BB
958
959 static const struct {
960 uint16_t designer_id;
961 uint16_t part_num;
962 const char *type;
963 const char *full;
964 } dap_partnums[] = {
965 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
966 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
967 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
968 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
969 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
970 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
971 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
972 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
973 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
974 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
975 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
976 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
977 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
978 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
979 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
980 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
981 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
982 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
983 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
984 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
985 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
986 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
987 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
988 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
989 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
990 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
991 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
992 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
993 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
994 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
995 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
996 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
997 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
998 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
999 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1000 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1001 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1002 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1003 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1004 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1005 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1006 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1007 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1008 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1009 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1010 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1011 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1012 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1013 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1014 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1015 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1016 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1017 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1018 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1019 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1020 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1021 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1022 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1023 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1024 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1025 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1026 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
1027 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1028 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1029 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1030 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1031 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1032 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1033 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1034 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1035 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1036 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1037 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1038 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1039 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1040 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1041 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1042 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1043 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1044 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1045 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1046 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1047 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1048 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1049 /* legacy comment: 0x113: what? */
1050 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1051 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1052 };
1053
1054 static int dap_rom_display(struct command_context *cmd_ctx,
1055 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1056 {
1057 int retval;
1058 uint64_t pid;
1059 uint32_t cid;
1060 char tabs[7] = "";
1061
1062 if (depth > 16) {
1063 command_print(cmd_ctx, "\tTables too deep");
1064 return ERROR_FAIL;
1065 }
1066
1067 if (depth)
1068 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1069
1070 uint32_t base_addr = dbgbase & 0xFFFFF000;
1071 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1072
1073 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1074 if (retval != ERROR_OK) {
1075 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1076 return ERROR_OK; /* Don't abort recursion */
1077 }
1078
1079 if (!is_dap_cid_ok(cid)) {
1080 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1081 return ERROR_OK; /* Don't abort recursion */
1082 }
1083
1084 /* component may take multiple 4K pages */
1085 uint32_t size = (pid >> 36) & 0xf;
1086 if (size > 0)
1087 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1088
1089 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1090
1091 uint8_t class = (cid >> 12) & 0xf;
1092 uint16_t part_num = pid & 0xfff;
1093 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1094
1095 if (designer_id & 0x80) {
1096 /* JEP106 code */
1097 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1098 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1099 } else {
1100 /* Legacy ASCII ID, clear invalid bits */
1101 designer_id &= 0x7f;
1102 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1103 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1104 }
1105
1106 /* default values to be overwritten upon finding a match */
1107 const char *type = "Unrecognized";
1108 const char *full = "";
1109
1110 /* search dap_partnums[] array for a match */
1111 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1112
1113 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1114 continue;
1115
1116 if (dap_partnums[entry].part_num != part_num)
1117 continue;
1118
1119 type = dap_partnums[entry].type;
1120 full = dap_partnums[entry].full;
1121 break;
1122 }
1123
1124 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1125 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1126
1127 if (class == 1) { /* ROM Table */
1128 uint32_t memtype;
1129 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1130 if (retval != ERROR_OK)
1131 return retval;
1132
1133 if (memtype & 0x01)
1134 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1135 else
1136 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1137
1138 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1139 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1140 uint32_t romentry;
1141 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1142 if (retval != ERROR_OK)
1143 return retval;
1144 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1145 tabs, entry_offset, romentry);
1146 if (romentry & 0x01) {
1147 /* Recurse */
1148 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1149 if (retval != ERROR_OK)
1150 return retval;
1151 } else if (romentry != 0) {
1152 command_print(cmd_ctx, "\t\tComponent not present");
1153 } else {
1154 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1155 break;
1156 }
1157 }
1158 } else if (class == 9) { /* CoreSight component */
1159 const char *major = "Reserved", *subtype = "Reserved";
1160
1161 uint32_t devtype;
1162 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1163 if (retval != ERROR_OK)
1164 return retval;
1165 unsigned minor = (devtype >> 4) & 0x0f;
1166 switch (devtype & 0x0f) {
1167 case 0:
1168 major = "Miscellaneous";
1169 switch (minor) {
1170 case 0:
1171 subtype = "other";
1172 break;
1173 case 4:
1174 subtype = "Validation component";
1175 break;
1176 }
1177 break;
1178 case 1:
1179 major = "Trace Sink";
1180 switch (minor) {
1181 case 0:
1182 subtype = "other";
1183 break;
1184 case 1:
1185 subtype = "Port";
1186 break;
1187 case 2:
1188 subtype = "Buffer";
1189 break;
1190 case 3:
1191 subtype = "Router";
1192 break;
1193 }
1194 break;
1195 case 2:
1196 major = "Trace Link";
1197 switch (minor) {
1198 case 0:
1199 subtype = "other";
1200 break;
1201 case 1:
1202 subtype = "Funnel, router";
1203 break;
1204 case 2:
1205 subtype = "Filter";
1206 break;
1207 case 3:
1208 subtype = "FIFO, buffer";
1209 break;
1210 }
1211 break;
1212 case 3:
1213 major = "Trace Source";
1214 switch (minor) {
1215 case 0:
1216 subtype = "other";
1217 break;
1218 case 1:
1219 subtype = "Processor";
1220 break;
1221 case 2:
1222 subtype = "DSP";
1223 break;
1224 case 3:
1225 subtype = "Engine/Coprocessor";
1226 break;
1227 case 4:
1228 subtype = "Bus";
1229 break;
1230 case 6:
1231 subtype = "Software";
1232 break;
1233 }
1234 break;
1235 case 4:
1236 major = "Debug Control";
1237 switch (minor) {
1238 case 0:
1239 subtype = "other";
1240 break;
1241 case 1:
1242 subtype = "Trigger Matrix";
1243 break;
1244 case 2:
1245 subtype = "Debug Auth";
1246 break;
1247 case 3:
1248 subtype = "Power Requestor";
1249 break;
1250 }
1251 break;
1252 case 5:
1253 major = "Debug Logic";
1254 switch (minor) {
1255 case 0:
1256 subtype = "other";
1257 break;
1258 case 1:
1259 subtype = "Processor";
1260 break;
1261 case 2:
1262 subtype = "DSP";
1263 break;
1264 case 3:
1265 subtype = "Engine/Coprocessor";
1266 break;
1267 case 4:
1268 subtype = "Bus";
1269 break;
1270 case 5:
1271 subtype = "Memory";
1272 break;
1273 }
1274 break;
1275 case 6:
1276 major = "Perfomance Monitor";
1277 switch (minor) {
1278 case 0:
1279 subtype = "other";
1280 break;
1281 case 1:
1282 subtype = "Processor";
1283 break;
1284 case 2:
1285 subtype = "DSP";
1286 break;
1287 case 3:
1288 subtype = "Engine/Coprocessor";
1289 break;
1290 case 4:
1291 subtype = "Bus";
1292 break;
1293 case 5:
1294 subtype = "Memory";
1295 break;
1296 }
1297 break;
1298 }
1299 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1300 (uint8_t)(devtype & 0xff),
1301 major, subtype);
1302 /* REVISIT also show 0xfc8 DevId */
1303 }
1304
1305 return ERROR_OK;
1306 }
1307
1308 static int dap_info_command(struct command_context *cmd_ctx,
1309 struct adiv5_ap *ap)
1310 {
1311 int retval;
1312 uint32_t dbgbase, apid;
1313 uint8_t mem_ap;
1314
1315 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1316 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1317 if (retval != ERROR_OK)
1318 return retval;
1319
1320 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1321 if (apid == 0) {
1322 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1323 return ERROR_FAIL;
1324 }
1325
1326 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1327 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1328 command_print(cmd_ctx, "\tType is JTAG-AP");
1329 break;
1330 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1331 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1332 break;
1333 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1334 command_print(cmd_ctx, "\tType is MEM-AP APB");
1335 break;
1336 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1337 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1338 break;
1339 default:
1340 command_print(cmd_ctx, "\tUnknown AP type");
1341 break;
1342 }
1343
1344 /* NOTE: a MEM-AP may have a single CoreSight component that's
1345 * not a ROM table ... or have no such components at all.
1346 */
1347 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1348 if (mem_ap) {
1349 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1350
1351 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1352 command_print(cmd_ctx, "\tNo ROM table present");
1353 } else {
1354 if (dbgbase & 0x01)
1355 command_print(cmd_ctx, "\tValid ROM table present");
1356 else
1357 command_print(cmd_ctx, "\tROM table in legacy format");
1358
1359 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1360 }
1361 }
1362
1363 return ERROR_OK;
1364 }
1365
1366 COMMAND_HANDLER(handle_dap_info_command)
1367 {
1368 struct target *target = get_current_target(CMD_CTX);
1369 struct arm *arm = target_to_arm(target);
1370 struct adiv5_dap *dap = arm->dap;
1371 uint32_t apsel;
1372
1373 switch (CMD_ARGC) {
1374 case 0:
1375 apsel = dap->apsel;
1376 break;
1377 case 1:
1378 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1379 if (apsel >= 256)
1380 return ERROR_COMMAND_SYNTAX_ERROR;
1381 break;
1382 default:
1383 return ERROR_COMMAND_SYNTAX_ERROR;
1384 }
1385
1386 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1387 }
1388
1389 COMMAND_HANDLER(dap_baseaddr_command)
1390 {
1391 struct target *target = get_current_target(CMD_CTX);
1392 struct arm *arm = target_to_arm(target);
1393 struct adiv5_dap *dap = arm->dap;
1394
1395 uint32_t apsel, baseaddr;
1396 int retval;
1397
1398 switch (CMD_ARGC) {
1399 case 0:
1400 apsel = dap->apsel;
1401 break;
1402 case 1:
1403 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1404 /* AP address is in bits 31:24 of DP_SELECT */
1405 if (apsel >= 256)
1406 return ERROR_COMMAND_SYNTAX_ERROR;
1407 break;
1408 default:
1409 return ERROR_COMMAND_SYNTAX_ERROR;
1410 }
1411
1412 /* NOTE: assumes we're talking to a MEM-AP, which
1413 * has a base address. There are other kinds of AP,
1414 * though they're not common for now. This should
1415 * use the ID register to verify it's a MEM-AP.
1416 */
1417 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1418 if (retval != ERROR_OK)
1419 return retval;
1420 retval = dap_run(dap);
1421 if (retval != ERROR_OK)
1422 return retval;
1423
1424 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1425
1426 return retval;
1427 }
1428
1429 COMMAND_HANDLER(dap_memaccess_command)
1430 {
1431 struct target *target = get_current_target(CMD_CTX);
1432 struct arm *arm = target_to_arm(target);
1433 struct adiv5_dap *dap = arm->dap;
1434
1435 uint32_t memaccess_tck;
1436
1437 switch (CMD_ARGC) {
1438 case 0:
1439 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1440 break;
1441 case 1:
1442 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1443 break;
1444 default:
1445 return ERROR_COMMAND_SYNTAX_ERROR;
1446 }
1447 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1448
1449 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1450 dap->ap[dap->apsel].memaccess_tck);
1451
1452 return ERROR_OK;
1453 }
1454
1455 COMMAND_HANDLER(dap_apsel_command)
1456 {
1457 struct target *target = get_current_target(CMD_CTX);
1458 struct arm *arm = target_to_arm(target);
1459 struct adiv5_dap *dap = arm->dap;
1460
1461 uint32_t apsel, apid;
1462 int retval;
1463
1464 switch (CMD_ARGC) {
1465 case 0:
1466 apsel = dap->apsel;
1467 break;
1468 case 1:
1469 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1470 /* AP address is in bits 31:24 of DP_SELECT */
1471 if (apsel >= 256)
1472 return ERROR_COMMAND_SYNTAX_ERROR;
1473 break;
1474 default:
1475 return ERROR_COMMAND_SYNTAX_ERROR;
1476 }
1477
1478 dap->apsel = apsel;
1479
1480 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1481 if (retval != ERROR_OK)
1482 return retval;
1483 retval = dap_run(dap);
1484 if (retval != ERROR_OK)
1485 return retval;
1486
1487 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1488 apsel, apid);
1489
1490 return retval;
1491 }
1492
1493 COMMAND_HANDLER(dap_apcsw_command)
1494 {
1495 struct target *target = get_current_target(CMD_CTX);
1496 struct arm *arm = target_to_arm(target);
1497 struct adiv5_dap *dap = arm->dap;
1498
1499 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1500
1501 switch (CMD_ARGC) {
1502 case 0:
1503 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1504 (dap->apsel), apcsw);
1505 break;
1506 case 1:
1507 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1508 /* AP address is in bits 31:24 of DP_SELECT */
1509 if (sprot > 1)
1510 return ERROR_COMMAND_SYNTAX_ERROR;
1511 if (sprot)
1512 apcsw |= CSW_SPROT;
1513 else
1514 apcsw &= ~CSW_SPROT;
1515 break;
1516 default:
1517 return ERROR_COMMAND_SYNTAX_ERROR;
1518 }
1519 dap->ap[dap->apsel].csw_default = apcsw;
1520
1521 return 0;
1522 }
1523
1524
1525
1526 COMMAND_HANDLER(dap_apid_command)
1527 {
1528 struct target *target = get_current_target(CMD_CTX);
1529 struct arm *arm = target_to_arm(target);
1530 struct adiv5_dap *dap = arm->dap;
1531
1532 uint32_t apsel, apid;
1533 int retval;
1534
1535 switch (CMD_ARGC) {
1536 case 0:
1537 apsel = dap->apsel;
1538 break;
1539 case 1:
1540 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1541 /* AP address is in bits 31:24 of DP_SELECT */
1542 if (apsel >= 256)
1543 return ERROR_COMMAND_SYNTAX_ERROR;
1544 break;
1545 default:
1546 return ERROR_COMMAND_SYNTAX_ERROR;
1547 }
1548
1549 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1550 if (retval != ERROR_OK)
1551 return retval;
1552 retval = dap_run(dap);
1553 if (retval != ERROR_OK)
1554 return retval;
1555
1556 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1557
1558 return retval;
1559 }
1560
1561 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1562 {
1563 struct target *target = get_current_target(CMD_CTX);
1564 struct arm *arm = target_to_arm(target);
1565 struct adiv5_dap *dap = arm->dap;
1566
1567 uint32_t enable = dap->ti_be_32_quirks;
1568
1569 switch (CMD_ARGC) {
1570 case 0:
1571 break;
1572 case 1:
1573 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1574 if (enable > 1)
1575 return ERROR_COMMAND_SYNTAX_ERROR;
1576 break;
1577 default:
1578 return ERROR_COMMAND_SYNTAX_ERROR;
1579 }
1580 dap->ti_be_32_quirks = enable;
1581 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1582 enable ? "enabled" : "disabled");
1583
1584 return 0;
1585 }
1586
1587 static const struct command_registration dap_commands[] = {
1588 {
1589 .name = "info",
1590 .handler = handle_dap_info_command,
1591 .mode = COMMAND_EXEC,
1592 .help = "display ROM table for MEM-AP "
1593 "(default currently selected AP)",
1594 .usage = "[ap_num]",
1595 },
1596 {
1597 .name = "apsel",
1598 .handler = dap_apsel_command,
1599 .mode = COMMAND_EXEC,
1600 .help = "Set the currently selected AP (default 0) "
1601 "and display the result",
1602 .usage = "[ap_num]",
1603 },
1604 {
1605 .name = "apcsw",
1606 .handler = dap_apcsw_command,
1607 .mode = COMMAND_EXEC,
1608 .help = "Set csw access bit ",
1609 .usage = "[sprot]",
1610 },
1611
1612 {
1613 .name = "apid",
1614 .handler = dap_apid_command,
1615 .mode = COMMAND_EXEC,
1616 .help = "return ID register from AP "
1617 "(default currently selected AP)",
1618 .usage = "[ap_num]",
1619 },
1620 {
1621 .name = "baseaddr",
1622 .handler = dap_baseaddr_command,
1623 .mode = COMMAND_EXEC,
1624 .help = "return debug base address from MEM-AP "
1625 "(default currently selected AP)",
1626 .usage = "[ap_num]",
1627 },
1628 {
1629 .name = "memaccess",
1630 .handler = dap_memaccess_command,
1631 .mode = COMMAND_EXEC,
1632 .help = "set/get number of extra tck for MEM-AP memory "
1633 "bus access [0-255]",
1634 .usage = "[cycles]",
1635 },
1636 {
1637 .name = "ti_be_32_quirks",
1638 .handler = dap_ti_be_32_quirks_command,
1639 .mode = COMMAND_CONFIG,
1640 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1641 .usage = "[enable]",
1642 },
1643 COMMAND_REGISTRATION_DONE
1644 };
1645
1646 const struct command_registration dap_command_handlers[] = {
1647 {
1648 .name = "dap",
1649 .mode = COMMAND_EXEC,
1650 .help = "DAP command group",
1651 .usage = "",
1652 .chain = dap_commands,
1653 },
1654 COMMAND_REGISTRATION_DONE
1655 };
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