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arm: Mis-aligned data issue fix.
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 *
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
56 */
57
58 /*
59 * Relevant specifications from ARM include:
60 *
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
63 *
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
66 */
67
68 #ifdef HAVE_CONFIG_H
69 #include "config.h"
70 #endif
71
72 #include "jtag/interface.h"
73 #include "arm.h"
74 #include "arm_adi_v5.h"
75 #include <helper/time_support.h>
76
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
78
79 /*
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 */
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
84 {
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
86 }
87
88 /***************************************************************************
89 * *
90 * DP and MEM-AP register access through APACC and DPACC *
91 * *
92 ***************************************************************************/
93
94 /**
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
98 *
99 * @param dap The DAP
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
102 */
103 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
104 {
105 uint32_t new_ap = (ap << 24) & 0xFF000000;
106
107 if (new_ap != dap->ap_current) {
108 dap->ap_current = new_ap;
109 /* Switching AP invalidates cached values.
110 * Values MUST BE UPDATED BEFORE AP ACCESS.
111 */
112 dap->ap_bank_value = -1;
113 dap->ap_csw_value = -1;
114 dap->ap_tar_value = -1;
115 }
116 }
117
118 /**
119 * Queue transactions setting up transfer parameters for the
120 * currently selected MEM-AP.
121 *
122 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
123 * initiate data reads or writes using memory or peripheral addresses.
124 * If the CSW is configured for it, the TAR may be automatically
125 * incremented after each transfer.
126 *
127 * @todo Rename to reflect it being specifically a MEM-AP function.
128 *
129 * @param dap The DAP connected to the MEM-AP.
130 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
131 * matches the cached value, the register is not changed.
132 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
133 * matches the cached address, the register is not changed.
134 *
135 * @return ERROR_OK if the transaction was properly queued, else a fault code.
136 */
137 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
138 {
139 int retval;
140
141 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
142 if (csw != dap->ap_csw_value) {
143 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
144 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
145 if (retval != ERROR_OK)
146 return retval;
147 dap->ap_csw_value = csw;
148 }
149 if (tar != dap->ap_tar_value) {
150 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
151 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
152 if (retval != ERROR_OK)
153 return retval;
154 dap->ap_tar_value = tar;
155 }
156 /* Disable TAR cache when autoincrementing */
157 if (csw & CSW_ADDRINC_MASK)
158 dap->ap_tar_value = -1;
159 return ERROR_OK;
160 }
161
162 /**
163 * Asynchronous (queued) read of a word from memory or a system register.
164 *
165 * @param dap The DAP connected to the MEM-AP performing the read.
166 * @param address Address of the 32-bit word to read; it must be
167 * readable by the currently selected MEM-AP.
168 * @param value points to where the word will be stored when the
169 * transaction queue is flushed (assuming no errors).
170 *
171 * @return ERROR_OK for success. Otherwise a fault code.
172 */
173 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
174 uint32_t *value)
175 {
176 int retval;
177
178 /* Use banked addressing (REG_BDx) to avoid some link traffic
179 * (updating TAR) when reading several consecutive addresses.
180 */
181 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
182 address & 0xFFFFFFF0);
183 if (retval != ERROR_OK)
184 return retval;
185
186 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
187 }
188
189 /**
190 * Synchronous read of a word from memory or a system register.
191 * As a side effect, this flushes any queued transactions.
192 *
193 * @param dap The DAP connected to the MEM-AP performing the read.
194 * @param address Address of the 32-bit word to read; it must be
195 * readable by the currently selected MEM-AP.
196 * @param value points to where the result will be stored.
197 *
198 * @return ERROR_OK for success; *value holds the result.
199 * Otherwise a fault code.
200 */
201 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
202 uint32_t *value)
203 {
204 int retval;
205
206 retval = mem_ap_read_u32(dap, address, value);
207 if (retval != ERROR_OK)
208 return retval;
209
210 return dap_run(dap);
211 }
212
213 /**
214 * Asynchronous (queued) write of a word to memory or a system register.
215 *
216 * @param dap The DAP connected to the MEM-AP.
217 * @param address Address to be written; it must be writable by
218 * the currently selected MEM-AP.
219 * @param value Word that will be written to the address when transaction
220 * queue is flushed (assuming no errors).
221 *
222 * @return ERROR_OK for success. Otherwise a fault code.
223 */
224 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
225 uint32_t value)
226 {
227 int retval;
228
229 /* Use banked addressing (REG_BDx) to avoid some link traffic
230 * (updating TAR) when writing several consecutive addresses.
231 */
232 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
233 address & 0xFFFFFFF0);
234 if (retval != ERROR_OK)
235 return retval;
236
237 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
238 value);
239 }
240
241 /**
242 * Synchronous write of a word to memory or a system register.
243 * As a side effect, this flushes any queued transactions.
244 *
245 * @param dap The DAP connected to the MEM-AP.
246 * @param address Address to be written; it must be writable by
247 * the currently selected MEM-AP.
248 * @param value Word that will be written.
249 *
250 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
251 */
252 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
253 uint32_t value)
254 {
255 int retval = mem_ap_write_u32(dap, address, value);
256
257 if (retval != ERROR_OK)
258 return retval;
259
260 return dap_run(dap);
261 }
262
263 /*****************************************************************************
264 * *
265 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
266 * *
267 * Write a buffer in target order (little endian) *
268 * *
269 *****************************************************************************/
270 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
271 {
272 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
273 uint32_t adr = address;
274 const uint8_t *pBuffer = buffer;
275
276 count >>= 2;
277 wcount = count;
278
279 /* if we have an unaligned access - reorder data */
280 if (adr & 0x3u) {
281 for (writecount = 0; writecount < count; writecount++) {
282 int i;
283 uint32_t outvalue;
284 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
285
286 for (i = 0; i < 4; i++) {
287 *((uint8_t *)pBuffer + (adr & 0x3)) = outvalue;
288 outvalue >>= 8;
289 adr++;
290 }
291 pBuffer += sizeof(uint32_t);
292 }
293 }
294
295 while (wcount > 0) {
296 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
297 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
298 if (wcount < blocksize)
299 blocksize = wcount;
300
301 /* handle unaligned data at 4k boundary */
302 if (blocksize == 0)
303 blocksize = 1;
304
305 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
306 if (retval != ERROR_OK)
307 return retval;
308
309 for (writecount = 0; writecount < blocksize; writecount++) {
310 uint32_t tmp;
311 tmp = buf_get_u32(buffer + 4 * writecount, 0, 32);
312 retval = dap_queue_ap_write(dap, AP_REG_DRW, tmp);
313 if (retval != ERROR_OK)
314 break;
315 }
316
317 retval = dap_run(dap);
318 if (retval == ERROR_OK) {
319 wcount = wcount - blocksize;
320 address = address + 4 * blocksize;
321 buffer = buffer + 4 * blocksize;
322 } else
323 errorcount++;
324
325 if (errorcount > 1) {
326 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
327 return retval;
328 }
329 }
330
331 return retval;
332 }
333
334 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
335 const uint8_t *buffer, int count, uint32_t address)
336 {
337 int retval = ERROR_OK;
338 int wcount, blocksize, writecount, i;
339
340 wcount = count >> 1;
341
342 while (wcount > 0) {
343 int nbytes;
344
345 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
346 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
347
348 if (wcount < blocksize)
349 blocksize = wcount;
350
351 /* handle unaligned data at 4k boundary */
352 if (blocksize == 0)
353 blocksize = 1;
354
355 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
356 if (retval != ERROR_OK)
357 return retval;
358 writecount = blocksize;
359
360 do {
361 nbytes = MIN((writecount << 1), 4);
362
363 if (nbytes < 4) {
364 retval = mem_ap_write_buf_u16(dap, buffer,
365 nbytes, address);
366 if (retval != ERROR_OK) {
367 LOG_WARNING("Block write error address "
368 "0x%" PRIx32 ", count 0x%x",
369 address, count);
370 return retval;
371 }
372
373 address += nbytes >> 1;
374 } else {
375 uint32_t outvalue;
376 memcpy(&outvalue, buffer, sizeof(uint32_t));
377
378 for (i = 0; i < nbytes; i++) {
379 *((uint8_t *)buffer + (address & 0x3)) = outvalue;
380 outvalue >>= 8;
381 address++;
382 }
383
384 memcpy(&outvalue, buffer, sizeof(uint32_t));
385 retval = dap_queue_ap_write(dap,
386 AP_REG_DRW, outvalue);
387 if (retval != ERROR_OK)
388 break;
389
390 retval = dap_run(dap);
391 if (retval != ERROR_OK) {
392 LOG_WARNING("Block write error address "
393 "0x%" PRIx32 ", count 0x%x",
394 address, count);
395 return retval;
396 }
397 }
398
399 buffer += nbytes >> 1;
400 writecount -= nbytes >> 1;
401
402 } while (writecount);
403 wcount -= blocksize;
404 }
405
406 return retval;
407 }
408
409 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
410 {
411 int retval = ERROR_OK;
412
413 if (count >= 4)
414 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
415
416 while (count > 0) {
417 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
418 if (retval != ERROR_OK)
419 return retval;
420 uint16_t svalue;
421 memcpy(&svalue, buffer, sizeof(uint16_t));
422 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
423 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
424 if (retval != ERROR_OK)
425 break;
426
427 retval = dap_run(dap);
428 if (retval != ERROR_OK)
429 break;
430
431 count -= 2;
432 address += 2;
433 buffer += 2;
434 }
435
436 return retval;
437 }
438
439 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
440 const uint8_t *buffer, int count, uint32_t address)
441 {
442 int retval = ERROR_OK;
443 int wcount, blocksize, writecount, i;
444
445 wcount = count;
446
447 while (wcount > 0) {
448 int nbytes;
449
450 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
451 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
452
453 if (wcount < blocksize)
454 blocksize = wcount;
455
456 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
457 if (retval != ERROR_OK)
458 return retval;
459 writecount = blocksize;
460
461 do {
462 nbytes = MIN(writecount, 4);
463
464 if (nbytes < 4) {
465 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
466 if (retval != ERROR_OK) {
467 LOG_WARNING("Block write error address "
468 "0x%" PRIx32 ", count 0x%x",
469 address, count);
470 return retval;
471 }
472
473 address += nbytes;
474 } else {
475 uint32_t outvalue;
476 memcpy(&outvalue, buffer, sizeof(uint32_t));
477
478 for (i = 0; i < nbytes; i++) {
479 *((uint8_t *)buffer + (address & 0x3)) = outvalue;
480 outvalue >>= 8;
481 address++;
482 }
483
484 memcpy(&outvalue, buffer, sizeof(uint32_t));
485 retval = dap_queue_ap_write(dap,
486 AP_REG_DRW, outvalue);
487 if (retval != ERROR_OK)
488 break;
489
490 retval = dap_run(dap);
491 if (retval != ERROR_OK) {
492 LOG_WARNING("Block write error address "
493 "0x%" PRIx32 ", count 0x%x",
494 address, count);
495 return retval;
496 }
497 }
498
499 buffer += nbytes;
500 writecount -= nbytes;
501
502 } while (writecount);
503 wcount -= blocksize;
504 }
505
506 return retval;
507 }
508
509 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
510 {
511 int retval = ERROR_OK;
512
513 if (count >= 4)
514 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
515
516 while (count > 0) {
517 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
518 if (retval != ERROR_OK)
519 return retval;
520 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
521 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
522 if (retval != ERROR_OK)
523 break;
524
525 retval = dap_run(dap);
526 if (retval != ERROR_OK)
527 break;
528
529 count--;
530 address++;
531 buffer++;
532 }
533
534 return retval;
535 }
536
537 /* FIXME don't import ... this is a temporary workaround for the
538 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
539 */
540 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
541 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
542 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
543
544 /**
545 * Synchronously read a block of 32-bit words into a buffer
546 * @param dap The DAP connected to the MEM-AP.
547 * @param buffer where the words will be stored (in host byte order).
548 * @param count How many words to read.
549 * @param address Memory address from which to read words; all the
550 * words must be readable by the currently selected MEM-AP.
551 */
552 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
553 int count, uint32_t address)
554 {
555 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
556 uint32_t adr = address;
557 uint8_t *pBuffer = buffer;
558
559 count >>= 2;
560 wcount = count;
561
562 while (wcount > 0) {
563 /* Adjust to read blocks within boundaries aligned to the
564 * TAR autoincrement size (at least 2^10). Autoincrement
565 * mode avoids an extra per-word roundtrip to update TAR.
566 */
567 blocksize = max_tar_block_size(dap->tar_autoincr_block,
568 address);
569 if (wcount < blocksize)
570 blocksize = wcount;
571
572 /* handle unaligned data at 4k boundary */
573 if (blocksize == 0)
574 blocksize = 1;
575
576 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
577 address);
578 if (retval != ERROR_OK)
579 return retval;
580
581 /* FIXME remove these three calls to adi_jtag_dp_scan(),
582 * so this routine becomes transport-neutral. Be careful
583 * not to cause performance problems with JTAG; would it
584 * suffice to loop over dap_queue_ap_read(), or would that
585 * be slower when JTAG is the chosen transport?
586 */
587
588 /* Scan out first read */
589 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
590 DPAP_READ, 0, NULL, NULL);
591 if (retval != ERROR_OK)
592 return retval;
593 for (readcount = 0; readcount < blocksize - 1; readcount++) {
594 /* Scan out next read; scan in posted value for the
595 * previous one. Assumes read is acked "OK/FAULT",
596 * and CTRL_STAT says that meant "OK".
597 */
598 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
599 DPAP_READ, 0, buffer + 4 * readcount,
600 &dap->ack);
601 if (retval != ERROR_OK)
602 return retval;
603 }
604
605 /* Scan in last posted value; RDBUFF has no other effect,
606 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
607 */
608 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
609 DPAP_READ, 0, buffer + 4 * readcount,
610 &dap->ack);
611 if (retval != ERROR_OK)
612 return retval;
613
614 retval = dap_run(dap);
615 if (retval != ERROR_OK) {
616 errorcount++;
617 if (errorcount <= 1) {
618 /* try again */
619 continue;
620 }
621 LOG_WARNING("Block read error address 0x%" PRIx32, address);
622 return retval;
623 }
624 wcount = wcount - blocksize;
625 address += 4 * blocksize;
626 buffer += 4 * blocksize;
627 }
628
629 /* if we have an unaligned access - reorder data */
630 if (adr & 0x3u) {
631 for (readcount = 0; readcount < count; readcount++) {
632 int i;
633 uint32_t data;
634 memcpy(&data, pBuffer, sizeof(uint32_t));
635
636 for (i = 0; i < 4; i++) {
637 *((uint8_t *)pBuffer) =
638 (data >> 8 * (adr & 0x3));
639 pBuffer++;
640 adr++;
641 }
642 }
643 }
644
645 return retval;
646 }
647
648 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
649 uint8_t *buffer, int count, uint32_t address)
650 {
651 uint32_t invalue;
652 int retval = ERROR_OK;
653 int wcount, blocksize, readcount, i;
654
655 wcount = count >> 1;
656
657 while (wcount > 0) {
658 int nbytes;
659
660 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
661 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
662 if (wcount < blocksize)
663 blocksize = wcount;
664
665 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
666 if (retval != ERROR_OK)
667 return retval;
668
669 /* handle unaligned data at 4k boundary */
670 if (blocksize == 0)
671 blocksize = 1;
672 readcount = blocksize;
673
674 do {
675 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
676 if (retval != ERROR_OK)
677 return retval;
678 retval = dap_run(dap);
679 if (retval != ERROR_OK) {
680 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
681 return retval;
682 }
683
684 nbytes = MIN((readcount << 1), 4);
685
686 for (i = 0; i < nbytes; i++) {
687 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
688 buffer++;
689 address++;
690 }
691
692 readcount -= (nbytes >> 1);
693 } while (readcount);
694 wcount -= blocksize;
695 }
696
697 return retval;
698 }
699
700 /**
701 * Synchronously read a block of 16-bit halfwords into a buffer
702 * @param dap The DAP connected to the MEM-AP.
703 * @param buffer where the halfwords will be stored (in host byte order).
704 * @param count How many halfwords to read.
705 * @param address Memory address from which to read words; all the
706 * words must be readable by the currently selected MEM-AP.
707 */
708 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
709 int count, uint32_t address)
710 {
711 uint32_t invalue, i;
712 int retval = ERROR_OK;
713
714 if (count >= 4)
715 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
716
717 while (count > 0) {
718 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
719 if (retval != ERROR_OK)
720 return retval;
721 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
722 if (retval != ERROR_OK)
723 break;
724
725 retval = dap_run(dap);
726 if (retval != ERROR_OK)
727 break;
728
729 if (address & 0x1) {
730 for (i = 0; i < 2; i++) {
731 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
732 buffer++;
733 address++;
734 }
735 } else {
736 uint16_t svalue = (invalue >> 8 * (address & 0x3));
737 memcpy(buffer, &svalue, sizeof(uint16_t));
738 address += 2;
739 buffer += 2;
740 }
741 count -= 2;
742 }
743
744 return retval;
745 }
746
747 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
748 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
749 *
750 * The solution is to arrange for a large out/in scan in this loop and
751 * and convert data afterwards.
752 */
753 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
754 uint8_t *buffer, int count, uint32_t address)
755 {
756 uint32_t invalue;
757 int retval = ERROR_OK;
758 int wcount, blocksize, readcount, i;
759
760 wcount = count;
761
762 while (wcount > 0) {
763 int nbytes;
764
765 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
766 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
767
768 if (wcount < blocksize)
769 blocksize = wcount;
770
771 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
772 if (retval != ERROR_OK)
773 return retval;
774 readcount = blocksize;
775
776 do {
777 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
778 if (retval != ERROR_OK)
779 return retval;
780 retval = dap_run(dap);
781 if (retval != ERROR_OK) {
782 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
783 return retval;
784 }
785
786 nbytes = MIN(readcount, 4);
787
788 for (i = 0; i < nbytes; i++) {
789 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
790 buffer++;
791 address++;
792 }
793
794 readcount -= nbytes;
795 } while (readcount);
796 wcount -= blocksize;
797 }
798
799 return retval;
800 }
801
802 /**
803 * Synchronously read a block of bytes into a buffer
804 * @param dap The DAP connected to the MEM-AP.
805 * @param buffer where the bytes will be stored.
806 * @param count How many bytes to read.
807 * @param address Memory address from which to read data; all the
808 * data must be readable by the currently selected MEM-AP.
809 */
810 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
811 int count, uint32_t address)
812 {
813 uint32_t invalue;
814 int retval = ERROR_OK;
815
816 if (count >= 4)
817 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
818
819 while (count > 0) {
820 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
821 if (retval != ERROR_OK)
822 return retval;
823 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
824 if (retval != ERROR_OK)
825 return retval;
826 retval = dap_run(dap);
827 if (retval != ERROR_OK)
828 break;
829
830 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
831 count--;
832 address++;
833 buffer++;
834 }
835
836 return retval;
837 }
838
839 /*--------------------------------------------------------------------*/
840 /* Wrapping function with selection of AP */
841 /*--------------------------------------------------------------------*/
842 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
843 uint32_t address, uint32_t *value)
844 {
845 dap_ap_select(swjdp, ap);
846 return mem_ap_read_u32(swjdp, address, value);
847 }
848
849 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
850 uint32_t address, uint32_t value)
851 {
852 dap_ap_select(swjdp, ap);
853 return mem_ap_write_u32(swjdp, address, value);
854 }
855
856 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
857 uint32_t address, uint32_t *value)
858 {
859 dap_ap_select(swjdp, ap);
860 return mem_ap_read_atomic_u32(swjdp, address, value);
861 }
862
863 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
864 uint32_t address, uint32_t value)
865 {
866 dap_ap_select(swjdp, ap);
867 return mem_ap_write_atomic_u32(swjdp, address, value);
868 }
869
870 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
871 uint8_t *buffer, int count, uint32_t address)
872 {
873 dap_ap_select(swjdp, ap);
874 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
875 }
876
877 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
878 uint8_t *buffer, int count, uint32_t address)
879 {
880 dap_ap_select(swjdp, ap);
881 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
882 }
883
884 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
885 uint8_t *buffer, int count, uint32_t address)
886 {
887 dap_ap_select(swjdp, ap);
888 return mem_ap_read_buf_u32(swjdp, buffer, count, address);
889 }
890
891 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
892 const uint8_t *buffer, int count, uint32_t address)
893 {
894 dap_ap_select(swjdp, ap);
895 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
896 }
897
898 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
899 const uint8_t *buffer, int count, uint32_t address)
900 {
901 dap_ap_select(swjdp, ap);
902 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
903 }
904
905 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
906 const uint8_t *buffer, int count, uint32_t address)
907 {
908 dap_ap_select(swjdp, ap);
909 return mem_ap_write_buf_u32(swjdp, buffer, count, address);
910 }
911
912 #define MDM_REG_STAT 0x00
913 #define MDM_REG_CTRL 0x04
914 #define MDM_REG_ID 0xfc
915
916 #define MDM_STAT_FMEACK (1<<0)
917 #define MDM_STAT_FREADY (1<<1)
918 #define MDM_STAT_SYSSEC (1<<2)
919 #define MDM_STAT_SYSRES (1<<3)
920 #define MDM_STAT_FMEEN (1<<5)
921 #define MDM_STAT_BACKDOOREN (1<<6)
922 #define MDM_STAT_LPEN (1<<7)
923 #define MDM_STAT_VLPEN (1<<8)
924 #define MDM_STAT_LLSMODEXIT (1<<9)
925 #define MDM_STAT_VLLSXMODEXIT (1<<10)
926 #define MDM_STAT_CORE_HALTED (1<<16)
927 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
928 #define MDM_STAT_CORESLEEPING (1<<18)
929
930 #define MEM_CTRL_FMEIP (1<<0)
931 #define MEM_CTRL_DBG_DIS (1<<1)
932 #define MEM_CTRL_DBG_REQ (1<<2)
933 #define MEM_CTRL_SYS_RES_REQ (1<<3)
934 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
935 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
936 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
937 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
938
939 /**
940 *
941 */
942 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
943 {
944 uint32_t val;
945 int retval;
946 enum reset_types jtag_reset_config = jtag_get_reset_config();
947
948 dap_ap_select(dap, 1);
949
950 /* first check mdm-ap id register */
951 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
952 if (retval != ERROR_OK)
953 return retval;
954 dap_run(dap);
955
956 if (val != 0x001C0000) {
957 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val);
958 dap_ap_select(dap, 0);
959 return ERROR_FAIL;
960 }
961
962 /* read and parse status register
963 * it's important that the device is out of
964 * reset here
965 */
966 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
967 if (retval != ERROR_OK)
968 return retval;
969 dap_run(dap);
970
971 LOG_DEBUG("MDM_REG_STAT %08X", val);
972
973 if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) {
974 LOG_DEBUG("MDMAP: system is secured, masserase needed");
975
976 if (!(val & MDM_STAT_FMEEN))
977 LOG_DEBUG("MDMAP: masserase is disabled");
978 else {
979 /* we need to assert reset */
980 if (jtag_reset_config & RESET_HAS_SRST) {
981 /* default to asserting srst */
982 adapter_assert_reset();
983 } else {
984 LOG_DEBUG("SRST not configured");
985 dap_ap_select(dap, 0);
986 return ERROR_FAIL;
987 }
988
989 while (1) {
990 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
991 if (retval != ERROR_OK)
992 return retval;
993 dap_run(dap);
994 /* read status register and wait for ready */
995 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
996 if (retval != ERROR_OK)
997 return retval;
998 dap_run(dap);
999 LOG_DEBUG("MDM_REG_STAT %08X", val);
1000
1001 if ((val & 1))
1002 break;
1003 }
1004
1005 while (1) {
1006 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
1007 if (retval != ERROR_OK)
1008 return retval;
1009 dap_run(dap);
1010 /* read status register */
1011 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1012 if (retval != ERROR_OK)
1013 return retval;
1014 dap_run(dap);
1015 LOG_DEBUG("MDM_REG_STAT %08X", val);
1016 /* read control register and wait for ready */
1017 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
1018 if (retval != ERROR_OK)
1019 return retval;
1020 dap_run(dap);
1021 LOG_DEBUG("MDM_REG_CTRL %08X", val);
1022
1023 if (val == 0x00)
1024 break;
1025 }
1026 }
1027 }
1028
1029 dap_ap_select(dap, 0);
1030
1031 return ERROR_OK;
1032 }
1033
1034 /** */
1035 struct dap_syssec_filter {
1036 /** */
1037 uint32_t idcode;
1038 /** */
1039 int (*dap_init)(struct adiv5_dap *dap);
1040 };
1041
1042 /** */
1043 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1044 { 0x4BA00477, dap_syssec_kinetis_mdmap }
1045 };
1046
1047 /**
1048 *
1049 */
1050 int dap_syssec(struct adiv5_dap *dap)
1051 {
1052 unsigned int i;
1053 struct jtag_tap *tap;
1054
1055 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
1056 tap = dap->jtag_info->tap;
1057
1058 while (tap != NULL) {
1059 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
1060 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode);
1061 dap_syssec_filter_data[i].dap_init(dap);
1062 }
1063 tap = tap->next_tap;
1064 }
1065 }
1066
1067 return ERROR_OK;
1068 }
1069
1070 /*--------------------------------------------------------------------------*/
1071
1072
1073 /* FIXME don't import ... just initialize as
1074 * part of DAP transport setup
1075 */
1076 extern const struct dap_ops jtag_dp_ops;
1077
1078 /*--------------------------------------------------------------------------*/
1079
1080 /**
1081 * Initialize a DAP. This sets up the power domains, prepares the DP
1082 * for further use, and arranges to use AP #0 for all AP operations
1083 * until dap_ap-select() changes that policy.
1084 *
1085 * @param dap The DAP being initialized.
1086 *
1087 * @todo Rename this. We also need an initialization scheme which account
1088 * for SWD transports not just JTAG; that will need to address differences
1089 * in layering. (JTAG is useful without any debug target; but not SWD.)
1090 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1091 */
1092 int ahbap_debugport_init(struct adiv5_dap *dap)
1093 {
1094 uint32_t ctrlstat;
1095 int cnt = 0;
1096 int retval;
1097
1098 LOG_DEBUG(" ");
1099
1100 /* JTAG-DP or SWJ-DP, in JTAG mode
1101 * ... for SWD mode this is patched as part
1102 * of link switchover
1103 */
1104 if (!dap->ops)
1105 dap->ops = &jtag_dp_ops;
1106
1107 /* Default MEM-AP setup.
1108 *
1109 * REVISIT AP #0 may be an inappropriate default for this.
1110 * Should we probe, or take a hint from the caller?
1111 * Presumably we can ignore the possibility of multiple APs.
1112 */
1113 dap->ap_current = !0;
1114 dap_ap_select(dap, 0);
1115
1116 /* DP initialization */
1117
1118 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1119 if (retval != ERROR_OK)
1120 return retval;
1121
1122 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1123 if (retval != ERROR_OK)
1124 return retval;
1125
1126 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1127 if (retval != ERROR_OK)
1128 return retval;
1129
1130 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1131 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1132 if (retval != ERROR_OK)
1133 return retval;
1134
1135 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1136 if (retval != ERROR_OK)
1137 return retval;
1138 retval = dap_run(dap);
1139 if (retval != ERROR_OK)
1140 return retval;
1141
1142 /* Check that we have debug power domains activated */
1143 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
1144 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1145 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1146 if (retval != ERROR_OK)
1147 return retval;
1148 retval = dap_run(dap);
1149 if (retval != ERROR_OK)
1150 return retval;
1151 alive_sleep(10);
1152 }
1153
1154 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
1155 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1156 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1157 if (retval != ERROR_OK)
1158 return retval;
1159 retval = dap_run(dap);
1160 if (retval != ERROR_OK)
1161 return retval;
1162 alive_sleep(10);
1163 }
1164
1165 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1166 if (retval != ERROR_OK)
1167 return retval;
1168 /* With debug power on we can activate OVERRUN checking */
1169 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1170 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1171 if (retval != ERROR_OK)
1172 return retval;
1173 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1174 if (retval != ERROR_OK)
1175 return retval;
1176
1177 dap_syssec(dap);
1178
1179 return ERROR_OK;
1180 }
1181
1182 /* CID interpretation -- see ARM IHI 0029B section 3
1183 * and ARM IHI 0031A table 13-3.
1184 */
1185 static const char *class_description[16] = {
1186 "Reserved", "ROM table", "Reserved", "Reserved",
1187 "Reserved", "Reserved", "Reserved", "Reserved",
1188 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1189 "Reserved", "OptimoDE DESS",
1190 "Generic IP component", "PrimeCell or System component"
1191 };
1192
1193 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1194 {
1195 return cid3 == 0xb1 && cid2 == 0x05
1196 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1197 }
1198
1199 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1200 uint32_t *out_dbgbase, uint32_t *out_apid)
1201 {
1202 uint32_t ap_old;
1203 int retval;
1204 uint32_t dbgbase, apid;
1205
1206 /* AP address is in bits 31:24 of DP_SELECT */
1207 if (ap >= 256)
1208 return ERROR_COMMAND_SYNTAX_ERROR;
1209
1210 ap_old = dap->ap_current;
1211 dap_ap_select(dap, ap);
1212
1213 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1214 if (retval != ERROR_OK)
1215 return retval;
1216 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1217 if (retval != ERROR_OK)
1218 return retval;
1219 retval = dap_run(dap);
1220 if (retval != ERROR_OK)
1221 return retval;
1222
1223 /* Excavate the device ID code */
1224 struct jtag_tap *tap = dap->jtag_info->tap;
1225 while (tap != NULL) {
1226 if (tap->hasidcode)
1227 break;
1228 tap = tap->next_tap;
1229 }
1230 if (tap == NULL || !tap->hasidcode)
1231 return ERROR_OK;
1232
1233 dap_ap_select(dap, ap_old);
1234
1235 /* The asignment happens only here to prevent modification of these
1236 * values before they are certain. */
1237 *out_dbgbase = dbgbase;
1238 *out_apid = apid;
1239
1240 return ERROR_OK;
1241 }
1242
1243 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1244 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1245 {
1246 uint32_t ap_old;
1247 uint32_t romentry, entry_offset = 0, component_base, devtype;
1248 int retval = ERROR_FAIL;
1249
1250 if (ap >= 256)
1251 return ERROR_COMMAND_SYNTAX_ERROR;
1252
1253 ap_old = dap->ap_current;
1254 dap_ap_select(dap, ap);
1255
1256 do {
1257 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1258 entry_offset, &romentry);
1259 if (retval != ERROR_OK)
1260 return retval;
1261
1262 component_base = (dbgbase & 0xFFFFF000)
1263 + (romentry & 0xFFFFF000);
1264
1265 if (romentry & 0x1) {
1266 retval = mem_ap_read_atomic_u32(dap,
1267 (component_base & 0xfffff000) | 0xfcc,
1268 &devtype);
1269 if (retval != ERROR_OK)
1270 return retval;
1271 if ((devtype & 0xff) == type) {
1272 *addr = component_base;
1273 retval = ERROR_OK;
1274 break;
1275 }
1276 }
1277 entry_offset += 4;
1278 } while (romentry > 0);
1279
1280 dap_ap_select(dap, ap_old);
1281
1282 return retval;
1283 }
1284
1285 static int dap_info_command(struct command_context *cmd_ctx,
1286 struct adiv5_dap *dap, int ap)
1287 {
1288 int retval;
1289 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1290 int romtable_present = 0;
1291 uint8_t mem_ap;
1292 uint32_t ap_old;
1293
1294 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1295 if (retval != ERROR_OK)
1296 return retval;
1297
1298 ap_old = dap->ap_current;
1299 dap_ap_select(dap, ap);
1300
1301 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1302 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1303 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1304 if (apid) {
1305 switch (apid&0x0F) {
1306 case 0:
1307 command_print(cmd_ctx, "\tType is JTAG-AP");
1308 break;
1309 case 1:
1310 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1311 break;
1312 case 2:
1313 command_print(cmd_ctx, "\tType is MEM-AP APB");
1314 break;
1315 default:
1316 command_print(cmd_ctx, "\tUnknown AP type");
1317 break;
1318 }
1319
1320 /* NOTE: a MEM-AP may have a single CoreSight component that's
1321 * not a ROM table ... or have no such components at all.
1322 */
1323 if (mem_ap)
1324 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1325 } else
1326 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1327
1328 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1329 if (romtable_present) {
1330 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1331 uint16_t entry_offset;
1332
1333 /* bit 16 of apid indicates a memory access port */
1334 if (dbgbase & 0x02)
1335 command_print(cmd_ctx, "\tValid ROM table present");
1336 else
1337 command_print(cmd_ctx, "\tROM table in legacy format");
1338
1339 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1340 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1341 if (retval != ERROR_OK)
1342 return retval;
1343 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1344 if (retval != ERROR_OK)
1345 return retval;
1346 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1347 if (retval != ERROR_OK)
1348 return retval;
1349 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1350 if (retval != ERROR_OK)
1351 return retval;
1352 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1353 if (retval != ERROR_OK)
1354 return retval;
1355 retval = dap_run(dap);
1356 if (retval != ERROR_OK)
1357 return retval;
1358
1359 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1360 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1361 ", CID2 0x%2.2x"
1362 ", CID1 0x%2.2x"
1363 ", CID0 0x%2.2x",
1364 (unsigned) cid3, (unsigned)cid2,
1365 (unsigned) cid1, (unsigned) cid0);
1366 if (memtype & 0x01)
1367 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1368 else
1369 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1370 "Dedicated debug bus.");
1371
1372 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1373 entry_offset = 0;
1374 do {
1375 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1376 if (retval != ERROR_OK)
1377 return retval;
1378 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1379 if (romentry & 0x01) {
1380 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1381 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1382 uint32_t component_base;
1383 unsigned part_num;
1384 char *type, *full;
1385
1386 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1387
1388 /* IDs are in last 4K section */
1389 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1390 if (retval != ERROR_OK)
1391 return retval;
1392 c_pid0 &= 0xff;
1393 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1394 if (retval != ERROR_OK)
1395 return retval;
1396 c_pid1 &= 0xff;
1397 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1398 if (retval != ERROR_OK)
1399 return retval;
1400 c_pid2 &= 0xff;
1401 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1402 if (retval != ERROR_OK)
1403 return retval;
1404 c_pid3 &= 0xff;
1405 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1406 if (retval != ERROR_OK)
1407 return retval;
1408 c_pid4 &= 0xff;
1409
1410 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1411 if (retval != ERROR_OK)
1412 return retval;
1413 c_cid0 &= 0xff;
1414 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1415 if (retval != ERROR_OK)
1416 return retval;
1417 c_cid1 &= 0xff;
1418 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1419 if (retval != ERROR_OK)
1420 return retval;
1421 c_cid2 &= 0xff;
1422 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1423 if (retval != ERROR_OK)
1424 return retval;
1425 c_cid3 &= 0xff;
1426
1427 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1428 "start address 0x%" PRIx32, component_base,
1429 /* component may take multiple 4K pages */
1430 component_base - 0x1000*(c_pid4 >> 4));
1431 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1432 (int) (c_cid1 >> 4) & 0xf,
1433 /* See ARM IHI 0029B Table 3-3 */
1434 class_description[(c_cid1 >> 4) & 0xf]);
1435
1436 /* CoreSight component? */
1437 if (((c_cid1 >> 4) & 0x0f) == 9) {
1438 uint32_t devtype;
1439 unsigned minor;
1440 char *major = "Reserved", *subtype = "Reserved";
1441
1442 retval = mem_ap_read_atomic_u32(dap,
1443 (component_base & 0xfffff000) | 0xfcc,
1444 &devtype);
1445 if (retval != ERROR_OK)
1446 return retval;
1447 minor = (devtype >> 4) & 0x0f;
1448 switch (devtype & 0x0f) {
1449 case 0:
1450 major = "Miscellaneous";
1451 switch (minor) {
1452 case 0:
1453 subtype = "other";
1454 break;
1455 case 4:
1456 subtype = "Validation component";
1457 break;
1458 }
1459 break;
1460 case 1:
1461 major = "Trace Sink";
1462 switch (minor) {
1463 case 0:
1464 subtype = "other";
1465 break;
1466 case 1:
1467 subtype = "Port";
1468 break;
1469 case 2:
1470 subtype = "Buffer";
1471 break;
1472 }
1473 break;
1474 case 2:
1475 major = "Trace Link";
1476 switch (minor) {
1477 case 0:
1478 subtype = "other";
1479 break;
1480 case 1:
1481 subtype = "Funnel, router";
1482 break;
1483 case 2:
1484 subtype = "Filter";
1485 break;
1486 case 3:
1487 subtype = "FIFO, buffer";
1488 break;
1489 }
1490 break;
1491 case 3:
1492 major = "Trace Source";
1493 switch (minor) {
1494 case 0:
1495 subtype = "other";
1496 break;
1497 case 1:
1498 subtype = "Processor";
1499 break;
1500 case 2:
1501 subtype = "DSP";
1502 break;
1503 case 3:
1504 subtype = "Engine/Coprocessor";
1505 break;
1506 case 4:
1507 subtype = "Bus";
1508 break;
1509 }
1510 break;
1511 case 4:
1512 major = "Debug Control";
1513 switch (minor) {
1514 case 0:
1515 subtype = "other";
1516 break;
1517 case 1:
1518 subtype = "Trigger Matrix";
1519 break;
1520 case 2:
1521 subtype = "Debug Auth";
1522 break;
1523 }
1524 break;
1525 case 5:
1526 major = "Debug Logic";
1527 switch (minor) {
1528 case 0:
1529 subtype = "other";
1530 break;
1531 case 1:
1532 subtype = "Processor";
1533 break;
1534 case 2:
1535 subtype = "DSP";
1536 break;
1537 case 3:
1538 subtype = "Engine/Coprocessor";
1539 break;
1540 }
1541 break;
1542 }
1543 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1544 (unsigned) (devtype & 0xff),
1545 major, subtype);
1546 /* REVISIT also show 0xfc8 DevId */
1547 }
1548
1549 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1550 command_print(cmd_ctx,
1551 "\t\tCID3 0%2.2x"
1552 ", CID2 0%2.2x"
1553 ", CID1 0%2.2x"
1554 ", CID0 0%2.2x",
1555 (int) c_cid3,
1556 (int) c_cid2,
1557 (int)c_cid1,
1558 (int)c_cid0);
1559 command_print(cmd_ctx,
1560 "\t\tPeripheral ID[4..0] = hex "
1561 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1562 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1563 (int) c_pid1, (int) c_pid0);
1564
1565 /* Part number interpretations are from Cortex
1566 * core specs, the CoreSight components TRM
1567 * (ARM DDI 0314H), CoreSight System Design
1568 * Guide (ARM DGI 0012D) and ETM specs; also
1569 * from chip observation (e.g. TI SDTI).
1570 */
1571 part_num = (c_pid0 & 0xff);
1572 part_num |= (c_pid1 & 0x0f) << 8;
1573 switch (part_num) {
1574 case 0x000:
1575 type = "Cortex-M3 NVIC";
1576 full = "(Interrupt Controller)";
1577 break;
1578 case 0x001:
1579 type = "Cortex-M3 ITM";
1580 full = "(Instrumentation Trace Module)";
1581 break;
1582 case 0x002:
1583 type = "Cortex-M3 DWT";
1584 full = "(Data Watchpoint and Trace)";
1585 break;
1586 case 0x003:
1587 type = "Cortex-M3 FBP";
1588 full = "(Flash Patch and Breakpoint)";
1589 break;
1590 case 0x00c:
1591 type = "Cortex-M4 SCS";
1592 full = "(System Control Space)";
1593 break;
1594 case 0x00d:
1595 type = "CoreSight ETM11";
1596 full = "(Embedded Trace)";
1597 break;
1598 /* case 0x113: what? */
1599 case 0x120: /* from OMAP3 memmap */
1600 type = "TI SDTI";
1601 full = "(System Debug Trace Interface)";
1602 break;
1603 case 0x343: /* from OMAP3 memmap */
1604 type = "TI DAPCTL";
1605 full = "";
1606 break;
1607 case 0x906:
1608 type = "Coresight CTI";
1609 full = "(Cross Trigger)";
1610 break;
1611 case 0x907:
1612 type = "Coresight ETB";
1613 full = "(Trace Buffer)";
1614 break;
1615 case 0x908:
1616 type = "Coresight CSTF";
1617 full = "(Trace Funnel)";
1618 break;
1619 case 0x910:
1620 type = "CoreSight ETM9";
1621 full = "(Embedded Trace)";
1622 break;
1623 case 0x912:
1624 type = "Coresight TPIU";
1625 full = "(Trace Port Interface Unit)";
1626 break;
1627 case 0x921:
1628 type = "Cortex-A8 ETM";
1629 full = "(Embedded Trace)";
1630 break;
1631 case 0x922:
1632 type = "Cortex-A8 CTI";
1633 full = "(Cross Trigger)";
1634 break;
1635 case 0x923:
1636 type = "Cortex-M3 TPIU";
1637 full = "(Trace Port Interface Unit)";
1638 break;
1639 case 0x924:
1640 type = "Cortex-M3 ETM";
1641 full = "(Embedded Trace)";
1642 break;
1643 case 0x925:
1644 type = "Cortex-M4 ETM";
1645 full = "(Embedded Trace)";
1646 break;
1647 case 0x930:
1648 type = "Cortex-R4 ETM";
1649 full = "(Embedded Trace)";
1650 break;
1651 case 0x9a1:
1652 type = "Cortex-M4 TPUI";
1653 full = "(Trace Port Interface Unit)";
1654 break;
1655 case 0xc08:
1656 type = "Cortex-A8 Debug";
1657 full = "(Debug Unit)";
1658 break;
1659 default:
1660 type = "-*- unrecognized -*-";
1661 full = "";
1662 break;
1663 }
1664 command_print(cmd_ctx, "\t\tPart is %s %s",
1665 type, full);
1666 } else {
1667 if (romentry)
1668 command_print(cmd_ctx, "\t\tComponent not present");
1669 else
1670 command_print(cmd_ctx, "\t\tEnd of ROM table");
1671 }
1672 entry_offset += 4;
1673 } while (romentry > 0);
1674 } else
1675 command_print(cmd_ctx, "\tNo ROM table present");
1676 dap_ap_select(dap, ap_old);
1677
1678 return ERROR_OK;
1679 }
1680
1681 COMMAND_HANDLER(handle_dap_info_command)
1682 {
1683 struct target *target = get_current_target(CMD_CTX);
1684 struct arm *arm = target_to_arm(target);
1685 struct adiv5_dap *dap = arm->dap;
1686 uint32_t apsel;
1687
1688 switch (CMD_ARGC) {
1689 case 0:
1690 apsel = dap->apsel;
1691 break;
1692 case 1:
1693 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1694 break;
1695 default:
1696 return ERROR_COMMAND_SYNTAX_ERROR;
1697 }
1698
1699 return dap_info_command(CMD_CTX, dap, apsel);
1700 }
1701
1702 COMMAND_HANDLER(dap_baseaddr_command)
1703 {
1704 struct target *target = get_current_target(CMD_CTX);
1705 struct arm *arm = target_to_arm(target);
1706 struct adiv5_dap *dap = arm->dap;
1707
1708 uint32_t apsel, baseaddr;
1709 int retval;
1710
1711 switch (CMD_ARGC) {
1712 case 0:
1713 apsel = dap->apsel;
1714 break;
1715 case 1:
1716 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1717 /* AP address is in bits 31:24 of DP_SELECT */
1718 if (apsel >= 256)
1719 return ERROR_COMMAND_SYNTAX_ERROR;
1720 break;
1721 default:
1722 return ERROR_COMMAND_SYNTAX_ERROR;
1723 }
1724
1725 dap_ap_select(dap, apsel);
1726
1727 /* NOTE: assumes we're talking to a MEM-AP, which
1728 * has a base address. There are other kinds of AP,
1729 * though they're not common for now. This should
1730 * use the ID register to verify it's a MEM-AP.
1731 */
1732 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1733 if (retval != ERROR_OK)
1734 return retval;
1735 retval = dap_run(dap);
1736 if (retval != ERROR_OK)
1737 return retval;
1738
1739 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1740
1741 return retval;
1742 }
1743
1744 COMMAND_HANDLER(dap_memaccess_command)
1745 {
1746 struct target *target = get_current_target(CMD_CTX);
1747 struct arm *arm = target_to_arm(target);
1748 struct adiv5_dap *dap = arm->dap;
1749
1750 uint32_t memaccess_tck;
1751
1752 switch (CMD_ARGC) {
1753 case 0:
1754 memaccess_tck = dap->memaccess_tck;
1755 break;
1756 case 1:
1757 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1758 break;
1759 default:
1760 return ERROR_COMMAND_SYNTAX_ERROR;
1761 }
1762 dap->memaccess_tck = memaccess_tck;
1763
1764 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1765 dap->memaccess_tck);
1766
1767 return ERROR_OK;
1768 }
1769
1770 COMMAND_HANDLER(dap_apsel_command)
1771 {
1772 struct target *target = get_current_target(CMD_CTX);
1773 struct arm *arm = target_to_arm(target);
1774 struct adiv5_dap *dap = arm->dap;
1775
1776 uint32_t apsel, apid;
1777 int retval;
1778
1779 switch (CMD_ARGC) {
1780 case 0:
1781 apsel = 0;
1782 break;
1783 case 1:
1784 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1785 /* AP address is in bits 31:24 of DP_SELECT */
1786 if (apsel >= 256)
1787 return ERROR_COMMAND_SYNTAX_ERROR;
1788 break;
1789 default:
1790 return ERROR_COMMAND_SYNTAX_ERROR;
1791 }
1792
1793 dap->apsel = apsel;
1794 dap_ap_select(dap, apsel);
1795
1796 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1797 if (retval != ERROR_OK)
1798 return retval;
1799 retval = dap_run(dap);
1800 if (retval != ERROR_OK)
1801 return retval;
1802
1803 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1804 apsel, apid);
1805
1806 return retval;
1807 }
1808
1809 COMMAND_HANDLER(dap_apid_command)
1810 {
1811 struct target *target = get_current_target(CMD_CTX);
1812 struct arm *arm = target_to_arm(target);
1813 struct adiv5_dap *dap = arm->dap;
1814
1815 uint32_t apsel, apid;
1816 int retval;
1817
1818 switch (CMD_ARGC) {
1819 case 0:
1820 apsel = dap->apsel;
1821 break;
1822 case 1:
1823 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1824 /* AP address is in bits 31:24 of DP_SELECT */
1825 if (apsel >= 256)
1826 return ERROR_COMMAND_SYNTAX_ERROR;
1827 break;
1828 default:
1829 return ERROR_COMMAND_SYNTAX_ERROR;
1830 }
1831
1832 dap_ap_select(dap, apsel);
1833
1834 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1835 if (retval != ERROR_OK)
1836 return retval;
1837 retval = dap_run(dap);
1838 if (retval != ERROR_OK)
1839 return retval;
1840
1841 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1842
1843 return retval;
1844 }
1845
1846 static const struct command_registration dap_commands[] = {
1847 {
1848 .name = "info",
1849 .handler = handle_dap_info_command,
1850 .mode = COMMAND_EXEC,
1851 .help = "display ROM table for MEM-AP "
1852 "(default currently selected AP)",
1853 .usage = "[ap_num]",
1854 },
1855 {
1856 .name = "apsel",
1857 .handler = dap_apsel_command,
1858 .mode = COMMAND_EXEC,
1859 .help = "Set the currently selected AP (default 0) "
1860 "and display the result",
1861 .usage = "[ap_num]",
1862 },
1863 {
1864 .name = "apid",
1865 .handler = dap_apid_command,
1866 .mode = COMMAND_EXEC,
1867 .help = "return ID register from AP "
1868 "(default currently selected AP)",
1869 .usage = "[ap_num]",
1870 },
1871 {
1872 .name = "baseaddr",
1873 .handler = dap_baseaddr_command,
1874 .mode = COMMAND_EXEC,
1875 .help = "return debug base address from MEM-AP "
1876 "(default currently selected AP)",
1877 .usage = "[ap_num]",
1878 },
1879 {
1880 .name = "memaccess",
1881 .handler = dap_memaccess_command,
1882 .mode = COMMAND_EXEC,
1883 .help = "set/get number of extra tck for MEM-AP memory "
1884 "bus access [0-255]",
1885 .usage = "[cycles]",
1886 },
1887 COMMAND_REGISTRATION_DONE
1888 };
1889
1890 const struct command_registration dap_command_handlers[] = {
1891 {
1892 .name = "dap",
1893 .mode = COMMAND_EXEC,
1894 .help = "DAP command group",
1895 .usage = "",
1896 .chain = dap_commands,
1897 },
1898 COMMAND_REGISTRATION_DONE
1899 };
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