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ARM: ADIv5 code shrinkage, cleanup
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 *
46 * @todo Remove modality (queued/nonqueued, via DAP trans_mode) from all
47 * procedure interfaces. Modal programming interfaces are very error prone.
48 * Procedures should be either queued, or synchronous. Otherwise input
49 * and output constraints are context-sensitive, and it's hard to know
50 * what a block of code will do just by reading it.
51 */
52
53 /*
54 * Relevant specifications from ARM include:
55 *
56 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
57 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
58 *
59 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
60 * Cortex-M3(tm) TRM, ARM DDI 0337G
61 */
62
63 #ifdef HAVE_CONFIG_H
64 #include "config.h"
65 #endif
66
67 #include "arm_adi_v5.h"
68 #include <helper/time_support.h>
69
70 /*
71 * Transaction Mode:
72 * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
73 * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
74 * result checking until swjdp_end_transaction()
75 * This must be done before using or deallocating any return variables.
76 * swjdp->trans_mode == TRANS_MODE_ATOMIC
77 * All reads and writes to the AHB bus are checked for valid completion, and return values
78 * are immediatley available.
79 */
80
81
82 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83
84 /*
85 uint32_t tar_block_size(uint32_t address)
86 Return the largest block starting at address that does not cross a tar block size alignment boundary
87 */
88 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
89 {
90 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
91 }
92
93 /***************************************************************************
94 * *
95 * DPACC and APACC scanchain access through JTAG-DP *
96 * *
97 ***************************************************************************/
98
99 /**
100 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
101 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
102 * discusses operations which access these registers.
103 *
104 * Note that only one scan is performed. If RnW is set, a separate scan
105 * will be needed to collect the data which was read; the "invalue" collects
106 * the posted result of a preceding operation, not the current one.
107 *
108 * @param swjdp the DAP
109 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
110 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
111 * SELECT register has more addressing bits.
112 * @param RnW false iff outvalue will be written to the DP or AP
113 * @param outvalue points to a 32-bit (little-endian) integer
114 * @param invalue NULL, or points to a 32-bit (little-endian) integer
115 * @param ack points to where the three bit JTAG_ACK_* code will be stored
116 */
117 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
118 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
119 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
120 {
121 struct arm_jtag *jtag_info = swjdp->jtag_info;
122 struct scan_field fields[2];
123 uint8_t out_addr_buf;
124
125 jtag_set_end_state(TAP_IDLE);
126 arm_jtag_set_instr(jtag_info, instr, NULL);
127
128 /* Add specified number of tck clocks before accessing memory bus */
129
130 /* REVISIT these TCK cycles should be *AFTER* updating APACC, since
131 * they provide more time for the (MEM) AP to complete the read ...
132 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
133 */
134 if ((instr == JTAG_DP_APACC)
135 && ((reg_addr == AP_REG_DRW)
136 || ((reg_addr & 0xF0) == AP_REG_BD0))
137 && (swjdp->memaccess_tck != 0))
138 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
139
140 /* Scan out a read or write operation using some DP or AP register.
141 * For APACC access with any sticky error flag set, this is discarded.
142 */
143 fields[0].tap = jtag_info->tap;
144 fields[0].num_bits = 3;
145 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
146 fields[0].out_value = &out_addr_buf;
147 fields[0].in_value = ack;
148
149 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
150 * complete; data we write is discarded, data we read is unpredictable.
151 * When overrun detect is active, STICKYORUN is set.
152 */
153
154 fields[1].tap = jtag_info->tap;
155 fields[1].num_bits = 32;
156 fields[1].out_value = outvalue;
157 fields[1].in_value = invalue;
158
159 jtag_add_dr_scan(2, fields, jtag_get_end_state());
160
161 return jtag_get_error();
162 }
163
164 /**
165 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
166 * This is exactly like adi_jtag_dp_scan(), except that endianness
167 * conversions are performed (so the types of invalue and outvalue
168 * must be different).
169 */
170 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
171 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
172 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
173 {
174 uint8_t out_value_buf[4];
175 int retval;
176
177 buf_set_u32(out_value_buf, 0, 32, outvalue);
178
179 retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
180 out_value_buf, (uint8_t *)invalue, ack);
181 if (retval != ERROR_OK)
182 return retval;
183
184 if (invalue)
185 jtag_add_callback(arm_le_to_h_u32,
186 (jtag_callback_data_t) invalue);
187
188 return retval;
189 }
190
191 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
192 static int scan_inout_check(struct swjdp_common *swjdp,
193 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
194 uint8_t *outvalue, uint8_t *invalue)
195 {
196 adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
197
198 if ((RnW == DPAP_READ) && (invalue != NULL))
199 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
200 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
201
202 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
203 * ack = OK/FAULT and the check CTRL_STAT
204 */
205 if ((instr == JTAG_DP_APACC)
206 && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
207 return jtagdp_transaction_endcheck(swjdp);
208
209 return ERROR_OK;
210 }
211
212 static int scan_inout_check_u32(struct swjdp_common *swjdp,
213 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
214 uint32_t outvalue, uint32_t *invalue)
215 {
216 /* Issue the read or write */
217 adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
218
219 /* For reads, collect posted value; RDBUFF has no other effect.
220 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
221 */
222 if ((RnW == DPAP_READ) && (invalue != NULL))
223 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
224 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
225
226 /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
227 * ack = OK/FAULT and then check CTRL_STAT
228 */
229 if ((instr == JTAG_DP_APACC)
230 && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
231 return jtagdp_transaction_endcheck(swjdp);
232
233 return ERROR_OK;
234 }
235
236 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
237 {
238 int retval;
239 uint32_t ctrlstat;
240
241 /* too expensive to call keep_alive() here */
242
243 #if 0
244 /* Danger!!!! BROKEN!!!! */
245 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
246 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
247 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
248 R956 introduced the check on return value here and now Michael Schwingen reports
249 that this code no longer works....
250
251 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
252 */
253 if ((retval = jtag_execute_queue()) != ERROR_OK)
254 {
255 LOG_ERROR("BUG: Why does this fail the first time????");
256 }
257 /* Why??? second time it works??? */
258 #endif
259
260 /* Post CTRL/STAT read; discard any previous posted read value
261 * but collect its ACK status.
262 */
263 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
264 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
265 if ((retval = jtag_execute_queue()) != ERROR_OK)
266 return retval;
267
268 swjdp->ack = swjdp->ack & 0x7;
269
270 /* common code path avoids calling timeval_ms() */
271 if (swjdp->ack != JTAG_ACK_OK_FAULT)
272 {
273 long long then = timeval_ms();
274
275 while (swjdp->ack != JTAG_ACK_OK_FAULT)
276 {
277 if (swjdp->ack == JTAG_ACK_WAIT)
278 {
279 if ((timeval_ms()-then) > 1000)
280 {
281 /* NOTE: this would be a good spot
282 * to use JTAG_DP_ABORT.
283 */
284 LOG_WARNING("Timeout (1000ms) waiting "
285 "for ACK=OK/FAULT "
286 "in JTAG-DP transaction");
287 return ERROR_JTAG_DEVICE_ERROR;
288 }
289 }
290 else
291 {
292 LOG_WARNING("Invalid ACK %#x "
293 "in JTAG-DP transaction",
294 swjdp->ack);
295 return ERROR_JTAG_DEVICE_ERROR;
296 }
297
298 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
299 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
300 if ((retval = jtag_execute_queue()) != ERROR_OK)
301 return retval;
302 swjdp->ack = swjdp->ack & 0x7;
303 }
304 }
305
306 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
307
308 /* Check for STICKYERR and STICKYORUN */
309 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
310 {
311 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
312 /* Check power to debug regions */
313 if ((ctrlstat & 0xf0000000) != 0xf0000000)
314 ahbap_debugport_init(swjdp);
315 else
316 {
317 uint32_t mem_ap_csw, mem_ap_tar;
318
319 /* Maybe print information about last intended
320 * MEM-AP access; but not if autoincrementing.
321 * *Real* CSW and TAR values are always shown.
322 */
323 if (swjdp->ap_tar_value != (uint32_t) -1)
324 LOG_DEBUG("MEM-AP Cached values: "
325 "ap_bank 0x%" PRIx32
326 ", ap_csw 0x%" PRIx32
327 ", ap_tar 0x%" PRIx32,
328 swjdp->ap_bank_value,
329 swjdp->ap_csw_value,
330 swjdp->ap_tar_value);
331
332 if (ctrlstat & SSTICKYORUN)
333 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
334 "memaccess, or reduce jtag speed");
335
336 if (ctrlstat & SSTICKYERR)
337 LOG_ERROR("JTAG-DP STICKY ERROR");
338
339 /* Clear Sticky Error Bits */
340 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
341 DP_CTRL_STAT, DPAP_WRITE,
342 swjdp->dp_ctrl_stat | SSTICKYORUN
343 | SSTICKYERR, NULL);
344 scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
345 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
346 if ((retval = jtag_execute_queue()) != ERROR_OK)
347 return retval;
348
349 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
350
351 dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
352 dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
353 if ((retval = jtag_execute_queue()) != ERROR_OK)
354 return retval;
355 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
356 PRIx32, mem_ap_csw, mem_ap_tar);
357
358 }
359 if ((retval = jtag_execute_queue()) != ERROR_OK)
360 return retval;
361 return ERROR_JTAG_DEVICE_ERROR;
362 }
363
364 return ERROR_OK;
365 }
366
367 /***************************************************************************
368 * *
369 * DP and MEM-AP register access through APACC and DPACC *
370 * *
371 ***************************************************************************/
372
373 static int dap_dp_write_reg(struct swjdp_common *swjdp,
374 uint32_t value, uint8_t reg_addr)
375 {
376 return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
377 reg_addr, DPAP_WRITE, value, NULL);
378 }
379
380 static int dap_dp_read_reg(struct swjdp_common *swjdp,
381 uint32_t *value, uint8_t reg_addr)
382 {
383 return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
384 reg_addr, DPAP_READ, 0, value);
385 }
386
387 /**
388 * Select one of the APs connected to the specified DAP. The
389 * selection is implicitly used with future AP transactions.
390 * This is a NOP if the specified AP is already selected.
391 *
392 * @param swjdp The DAP
393 * @param apsel Number of the AP to (implicitly) use with further
394 * transactions. This normally identifies a MEM-AP.
395 */
396 void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
397 {
398 uint32_t select = (apsel << 24) & 0xFF000000;
399
400 if (select != swjdp->apsel)
401 {
402 swjdp->apsel = select;
403 /* Switching AP invalidates cached values.
404 * Values MUST BE UPDATED BEFORE AP ACCESS.
405 */
406 swjdp->ap_bank_value = -1;
407 swjdp->ap_csw_value = -1;
408 swjdp->ap_tar_value = -1;
409 }
410 }
411
412 /** Select the AP register bank matching bits 7:4 of ap_reg. */
413 static int dap_ap_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
414 {
415 uint32_t select = (ap_reg & 0x000000F0);
416
417 if (select != swjdp->ap_bank_value)
418 {
419 swjdp->ap_bank_value = select;
420 select |= swjdp->apsel;
421 return dap_dp_write_reg(swjdp, select, DP_SELECT);
422 } else
423 return ERROR_OK;
424 }
425
426 static int dap_ap_write_reg(struct swjdp_common *swjdp,
427 uint32_t reg_addr, uint8_t *out_value_buf)
428 {
429 int retval;
430
431 retval = dap_ap_bankselect(swjdp, reg_addr);
432 if (retval != ERROR_OK)
433 return retval;
434
435 return scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
436 DPAP_WRITE, out_value_buf, NULL);
437 }
438
439 /**
440 * Write an AP register value.
441 * This is synchronous iff the mode is set to ATOMIC, in which
442 * case any queued transactions are flushed.
443 *
444 * @param swjdp The DAP whose currently selected AP will be written.
445 * @param reg_addr Eight bit AP register address.
446 * @param value Word to be written at reg_addr
447 *
448 * @return In synchronous mode: ERROR_OK for success, and the register holds
449 * the specified value; else a fault code. In asynchronous mode, a status
450 * code reflecting whether the transaction was properly queued.
451 */
452 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
453 uint32_t reg_addr, uint32_t value)
454 {
455 uint8_t out_value_buf[4];
456
457 buf_set_u32(out_value_buf, 0, 32, value);
458 return dap_ap_write_reg(swjdp,
459 reg_addr, out_value_buf);
460 }
461
462 /**
463 * Read an AP register value.
464 * This is synchronous iff the mode is set to ATOMIC, in which
465 * case any queued transactions are flushed.
466 *
467 * @param swjdp The DAP whose currently selected AP will be read.
468 * @param reg_addr Eight bit AP register address.
469 * @param value Points to where the 32-bit (little-endian) word will be stored.
470 *
471 * @return In synchronous mode: ERROR_OK for success, and *value holds
472 * the specified value; else a fault code. In asynchronous mode, a status
473 * code reflecting whether the transaction was properly queued.
474 */
475 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
476 uint32_t reg_addr, uint32_t *value)
477 {
478 int retval;
479
480 retval = dap_ap_bankselect(swjdp, reg_addr);
481 if (retval != ERROR_OK)
482 return retval;
483
484 return scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
485 DPAP_READ, 0, value);
486 }
487
488 /**
489 * Set up transfer parameters for the currently selected MEM-AP.
490 * This is synchronous iff the mode is set to ATOMIC, in which
491 * case any queued transactions are flushed.
492 *
493 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
494 * initiate data reads or writes using memory or peripheral addresses.
495 * If the CSW is configured for it, the TAR may be automatically
496 * incremented after each transfer.
497 *
498 * @todo Rename to reflect it being specifically a MEM-AP function.
499 *
500 * @param swjdp The DAP connected to the MEM-AP.
501 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
502 * matches the cached value, the register is not changed.
503 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
504 * matches the cached address, the register is not changed.
505 *
506 * @return In synchronous mode: ERROR_OK for success, and the AP is set
507 * up as requested else a fault code. In asynchronous mode, a status
508 * code reflecting whether the transaction was properly queued.
509 */
510 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
511 {
512 int retval;
513
514 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
515 if (csw != swjdp->ap_csw_value)
516 {
517 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
518 retval = dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
519 if (retval != ERROR_OK)
520 return retval;
521 swjdp->ap_csw_value = csw;
522 }
523 if (tar != swjdp->ap_tar_value)
524 {
525 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
526 retval = dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
527 if (retval != ERROR_OK)
528 return retval;
529 swjdp->ap_tar_value = tar;
530 }
531 /* Disable TAR cache when autoincrementing */
532 if (csw & CSW_ADDRINC_MASK)
533 swjdp->ap_tar_value = -1;
534 return ERROR_OK;
535 }
536
537 /**
538 * Asynchronous (queued) read of a word from memory or a system register.
539 *
540 * @param swjdp The DAP connected to the MEM-AP performing the read.
541 * @param address Address of the 32-bit word to read; it must be
542 * readable by the currently selected MEM-AP.
543 * @param value points to where the word will be stored when the
544 * transaction queue is flushed (assuming no errors).
545 *
546 * @return ERROR_OK for success. Otherwise a fault code.
547 */
548 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
549 uint32_t *value)
550 {
551 int retval;
552
553 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
554
555 /* Use banked addressing (REG_BDx) to avoid some link traffic
556 * (updating TAR) when reading several consecutive addresses.
557 */
558 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
559 address & 0xFFFFFFF0);
560 if (retval != ERROR_OK)
561 return retval;
562
563 return dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
564 }
565
566 /**
567 * Synchronous read of a word from memory or a system register.
568 * As a side effect, this flushes any queued transactions.
569 *
570 * @param swjdp The DAP connected to the MEM-AP performing the read.
571 * @param address Address of the 32-bit word to read; it must be
572 * readable by the currently selected MEM-AP.
573 * @param value points to where the result will be stored.
574 *
575 * @return ERROR_OK for success; *value holds the result.
576 * Otherwise a fault code.
577 */
578 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
579 uint32_t *value)
580 {
581 int retval;
582
583 retval = mem_ap_read_u32(swjdp, address, value);
584 if (retval != ERROR_OK)
585 return retval;
586
587 return jtagdp_transaction_endcheck(swjdp);
588 }
589
590 /**
591 * Asynchronous (queued) write of a word to memory or a system register.
592 *
593 * @param swjdp The DAP connected to the MEM-AP.
594 * @param address Address to be written; it must be writable by
595 * the currently selected MEM-AP.
596 * @param value Word that will be written to the address when transaction
597 * queue is flushed (assuming no errors).
598 *
599 * @return ERROR_OK for success. Otherwise a fault code.
600 */
601 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
602 uint32_t value)
603 {
604 int retval;
605
606 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
607
608 /* Use banked addressing (REG_BDx) to avoid some link traffic
609 * (updating TAR) when writing several consecutive addresses.
610 */
611 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
612 address & 0xFFFFFFF0);
613 if (retval != ERROR_OK)
614 return retval;
615
616 return dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC),
617 value);
618 }
619
620 /**
621 * Synchronous write of a word to memory or a system register.
622 * As a side effect, this flushes any queued transactions.
623 *
624 * @param swjdp The DAP connected to the MEM-AP.
625 * @param address Address to be written; it must be writable by
626 * the currently selected MEM-AP.
627 * @param value Word that will be written.
628 *
629 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
630 */
631 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
632 uint32_t value)
633 {
634 int retval = mem_ap_write_u32(swjdp, address, value);
635
636 if (retval != ERROR_OK)
637 return retval;
638
639 return jtagdp_transaction_endcheck(swjdp);
640 }
641
642 /*****************************************************************************
643 * *
644 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
645 * *
646 * Write a buffer in target order (little endian) *
647 * *
648 *****************************************************************************/
649 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
650 {
651 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
652 uint32_t adr = address;
653 uint8_t* pBuffer = buffer;
654
655 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
656
657 count >>= 2;
658 wcount = count;
659
660 /* if we have an unaligned access - reorder data */
661 if (adr & 0x3u)
662 {
663 for (writecount = 0; writecount < count; writecount++)
664 {
665 int i;
666 uint32_t outvalue;
667 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
668
669 for (i = 0; i < 4; i++)
670 {
671 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
672 outvalue >>= 8;
673 adr++;
674 }
675 pBuffer += sizeof(uint32_t);
676 }
677 }
678
679 while (wcount > 0)
680 {
681 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
682 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
683 if (wcount < blocksize)
684 blocksize = wcount;
685
686 /* handle unaligned data at 4k boundary */
687 if (blocksize == 0)
688 blocksize = 1;
689
690 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
691
692 for (writecount = 0; writecount < blocksize; writecount++)
693 {
694 dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
695 }
696
697 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
698 {
699 wcount = wcount - blocksize;
700 address = address + 4 * blocksize;
701 buffer = buffer + 4 * blocksize;
702 }
703 else
704 {
705 errorcount++;
706 }
707
708 if (errorcount > 1)
709 {
710 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
711 return ERROR_JTAG_DEVICE_ERROR;
712 }
713 }
714
715 return retval;
716 }
717
718 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
719 uint8_t *buffer, int count, uint32_t address)
720 {
721 int retval = ERROR_OK;
722 int wcount, blocksize, writecount, i;
723
724 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
725
726 wcount = count >> 1;
727
728 while (wcount > 0)
729 {
730 int nbytes;
731
732 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
733 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
734
735 if (wcount < blocksize)
736 blocksize = wcount;
737
738 /* handle unaligned data at 4k boundary */
739 if (blocksize == 0)
740 blocksize = 1;
741
742 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
743 writecount = blocksize;
744
745 do
746 {
747 nbytes = MIN((writecount << 1), 4);
748
749 if (nbytes < 4)
750 {
751 if (mem_ap_write_buf_u16(swjdp, buffer,
752 nbytes, address) != ERROR_OK)
753 {
754 LOG_WARNING("Block write error address "
755 "0x%" PRIx32 ", count 0x%x",
756 address, count);
757 return ERROR_JTAG_DEVICE_ERROR;
758 }
759
760 address += nbytes >> 1;
761 }
762 else
763 {
764 uint32_t outvalue;
765 memcpy(&outvalue, buffer, sizeof(uint32_t));
766
767 for (i = 0; i < nbytes; i++)
768 {
769 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
770 outvalue >>= 8;
771 address++;
772 }
773
774 memcpy(&outvalue, buffer, sizeof(uint32_t));
775 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
776 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
777 {
778 LOG_WARNING("Block write error address "
779 "0x%" PRIx32 ", count 0x%x",
780 address, count);
781 return ERROR_JTAG_DEVICE_ERROR;
782 }
783 }
784
785 buffer += nbytes >> 1;
786 writecount -= nbytes >> 1;
787
788 } while (writecount);
789 wcount -= blocksize;
790 }
791
792 return retval;
793 }
794
795 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
796 {
797 int retval = ERROR_OK;
798
799 if (count >= 4)
800 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
801
802 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
803
804 while (count > 0)
805 {
806 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
807 uint16_t svalue;
808 memcpy(&svalue, buffer, sizeof(uint16_t));
809 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
810 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
811 retval = jtagdp_transaction_endcheck(swjdp);
812 count -= 2;
813 address += 2;
814 buffer += 2;
815 }
816
817 return retval;
818 }
819
820 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
821 uint8_t *buffer, int count, uint32_t address)
822 {
823 int retval = ERROR_OK;
824 int wcount, blocksize, writecount, i;
825
826 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
827
828 wcount = count;
829
830 while (wcount > 0)
831 {
832 int nbytes;
833
834 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
835 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
836
837 if (wcount < blocksize)
838 blocksize = wcount;
839
840 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
841 writecount = blocksize;
842
843 do
844 {
845 nbytes = MIN(writecount, 4);
846
847 if (nbytes < 4)
848 {
849 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
850 {
851 LOG_WARNING("Block write error address "
852 "0x%" PRIx32 ", count 0x%x",
853 address, count);
854 return ERROR_JTAG_DEVICE_ERROR;
855 }
856
857 address += nbytes;
858 }
859 else
860 {
861 uint32_t outvalue;
862 memcpy(&outvalue, buffer, sizeof(uint32_t));
863
864 for (i = 0; i < nbytes; i++)
865 {
866 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
867 outvalue >>= 8;
868 address++;
869 }
870
871 memcpy(&outvalue, buffer, sizeof(uint32_t));
872 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
873 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
874 {
875 LOG_WARNING("Block write error address "
876 "0x%" PRIx32 ", count 0x%x",
877 address, count);
878 return ERROR_JTAG_DEVICE_ERROR;
879 }
880 }
881
882 buffer += nbytes;
883 writecount -= nbytes;
884
885 } while (writecount);
886 wcount -= blocksize;
887 }
888
889 return retval;
890 }
891
892 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
893 {
894 int retval = ERROR_OK;
895
896 if (count >= 4)
897 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
898
899 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
900
901 while (count > 0)
902 {
903 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
904 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
905 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
906 retval = jtagdp_transaction_endcheck(swjdp);
907 count--;
908 address++;
909 buffer++;
910 }
911
912 return retval;
913 }
914
915 /*********************************************************************************
916 * *
917 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
918 * *
919 * Read block fast in target order (little endian) into a buffer *
920 * *
921 **********************************************************************************/
922 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
923 {
924 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
925 uint32_t adr = address;
926 uint8_t* pBuffer = buffer;
927
928 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
929
930 count >>= 2;
931 wcount = count;
932
933 while (wcount > 0)
934 {
935 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
936 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
937 if (wcount < blocksize)
938 blocksize = wcount;
939
940 /* handle unaligned data at 4k boundary */
941 if (blocksize == 0)
942 blocksize = 1;
943
944 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
945
946 /* Scan out first read */
947 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
948 DPAP_READ, 0, NULL, NULL);
949 for (readcount = 0; readcount < blocksize - 1; readcount++)
950 {
951 /* Scan out next read; scan in posted value for the
952 * previous one. Assumes read is acked "OK/FAULT",
953 * and CTRL_STAT says that meant "OK".
954 */
955 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
956 DPAP_READ, 0, buffer + 4 * readcount,
957 &swjdp->ack);
958 }
959
960 /* Scan in last posted value; RDBUFF has no other effect,
961 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
962 */
963 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
964 DPAP_READ, 0, buffer + 4 * readcount,
965 &swjdp->ack);
966 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
967 {
968 wcount = wcount - blocksize;
969 address += 4 * blocksize;
970 buffer += 4 * blocksize;
971 }
972 else
973 {
974 errorcount++;
975 }
976
977 if (errorcount > 1)
978 {
979 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
980 return ERROR_JTAG_DEVICE_ERROR;
981 }
982 }
983
984 /* if we have an unaligned access - reorder data */
985 if (adr & 0x3u)
986 {
987 for (readcount = 0; readcount < count; readcount++)
988 {
989 int i;
990 uint32_t data;
991 memcpy(&data, pBuffer, sizeof(uint32_t));
992
993 for (i = 0; i < 4; i++)
994 {
995 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
996 pBuffer++;
997 adr++;
998 }
999 }
1000 }
1001
1002 return retval;
1003 }
1004
1005 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
1006 uint8_t *buffer, int count, uint32_t address)
1007 {
1008 uint32_t invalue;
1009 int retval = ERROR_OK;
1010 int wcount, blocksize, readcount, i;
1011
1012 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1013
1014 wcount = count >> 1;
1015
1016 while (wcount > 0)
1017 {
1018 int nbytes;
1019
1020 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1021 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1022 if (wcount < blocksize)
1023 blocksize = wcount;
1024
1025 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
1026
1027 /* handle unaligned data at 4k boundary */
1028 if (blocksize == 0)
1029 blocksize = 1;
1030 readcount = blocksize;
1031
1032 do
1033 {
1034 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1035 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1036 {
1037 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1038 return ERROR_JTAG_DEVICE_ERROR;
1039 }
1040
1041 nbytes = MIN((readcount << 1), 4);
1042
1043 for (i = 0; i < nbytes; i++)
1044 {
1045 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1046 buffer++;
1047 address++;
1048 }
1049
1050 readcount -= (nbytes >> 1);
1051 } while (readcount);
1052 wcount -= blocksize;
1053 }
1054
1055 return retval;
1056 }
1057
1058 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1059 {
1060 uint32_t invalue, i;
1061 int retval = ERROR_OK;
1062
1063 if (count >= 4)
1064 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
1065
1066 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1067
1068 while (count > 0)
1069 {
1070 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
1071 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1072 retval = jtagdp_transaction_endcheck(swjdp);
1073 if (address & 0x1)
1074 {
1075 for (i = 0; i < 2; i++)
1076 {
1077 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1078 buffer++;
1079 address++;
1080 }
1081 }
1082 else
1083 {
1084 uint16_t svalue = (invalue >> 8 * (address & 0x3));
1085 memcpy(buffer, &svalue, sizeof(uint16_t));
1086 address += 2;
1087 buffer += 2;
1088 }
1089 count -= 2;
1090 }
1091
1092 return retval;
1093 }
1094
1095 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1096 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1097 *
1098 * The solution is to arrange for a large out/in scan in this loop and
1099 * and convert data afterwards.
1100 */
1101 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
1102 uint8_t *buffer, int count, uint32_t address)
1103 {
1104 uint32_t invalue;
1105 int retval = ERROR_OK;
1106 int wcount, blocksize, readcount, i;
1107
1108 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1109
1110 wcount = count;
1111
1112 while (wcount > 0)
1113 {
1114 int nbytes;
1115
1116 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1117 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1118
1119 if (wcount < blocksize)
1120 blocksize = wcount;
1121
1122 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1123 readcount = blocksize;
1124
1125 do
1126 {
1127 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1128 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1129 {
1130 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1131 return ERROR_JTAG_DEVICE_ERROR;
1132 }
1133
1134 nbytes = MIN(readcount, 4);
1135
1136 for (i = 0; i < nbytes; i++)
1137 {
1138 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1139 buffer++;
1140 address++;
1141 }
1142
1143 readcount -= nbytes;
1144 } while (readcount);
1145 wcount -= blocksize;
1146 }
1147
1148 return retval;
1149 }
1150
1151 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1152 {
1153 uint32_t invalue;
1154 int retval = ERROR_OK;
1155
1156 if (count >= 4)
1157 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1158
1159 swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1160
1161 while (count > 0)
1162 {
1163 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1164 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1165 retval = jtagdp_transaction_endcheck(swjdp);
1166 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1167 count--;
1168 address++;
1169 buffer++;
1170 }
1171
1172 return retval;
1173 }
1174
1175 /**
1176 * Initialize a DAP. This sets up the power domains, prepares the DP
1177 * for further use, and arranges to use AP #0 for all AP operations
1178 * until dap_ap-select() changes that policy.
1179 *
1180 * @param swjdp The DAP being initialized.
1181 *
1182 * @todo Rename this. We also need an initialization scheme which account
1183 * for SWD transports not just JTAG; that will need to address differences
1184 * in layering. (JTAG is useful without any debug target; but not SWD.)
1185 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1186 */
1187 int ahbap_debugport_init(struct swjdp_common *swjdp)
1188 {
1189 uint32_t idreg, romaddr, dummy;
1190 uint32_t ctrlstat;
1191 int cnt = 0;
1192 int retval;
1193
1194 LOG_DEBUG(" ");
1195
1196 /* Default MEM-AP setup.
1197 *
1198 * REVISIT AP #0 may be an inappropriate default for this.
1199 * Should we probe, or take a hint from the caller?
1200 * Presumably we can ignore the possibility of multiple APs.
1201 */
1202 swjdp->apsel = !0;
1203 dap_ap_select(swjdp, 0);
1204
1205 /* DP initialization */
1206 swjdp->trans_mode = TRANS_MODE_ATOMIC;
1207 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1208 dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1209 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1210
1211 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1212
1213 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1214 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1215 if ((retval = jtag_execute_queue()) != ERROR_OK)
1216 return retval;
1217
1218 /* Check that we have debug power domains activated */
1219 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1220 {
1221 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1222 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1223 if ((retval = jtag_execute_queue()) != ERROR_OK)
1224 return retval;
1225 alive_sleep(10);
1226 }
1227
1228 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1229 {
1230 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1231 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1232 if ((retval = jtag_execute_queue()) != ERROR_OK)
1233 return retval;
1234 alive_sleep(10);
1235 }
1236
1237 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1238 /* With debug power on we can activate OVERRUN checking */
1239 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1240 dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1241 dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1242
1243 /*
1244 * REVISIT this isn't actually *initializing* anything in an AP,
1245 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1246 * Should it? If the ROM address is valid, is this the right
1247 * place to scan the table and do any topology detection?
1248 */
1249 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1250 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1251
1252 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1253 ", Debug ROM Address 0x%" PRIx32,
1254 swjdp->apsel, idreg, romaddr);
1255
1256 return ERROR_OK;
1257 }
1258
1259 /* CID interpretation -- see ARM IHI 0029B section 3
1260 * and ARM IHI 0031A table 13-3.
1261 */
1262 static const char *class_description[16] ={
1263 "Reserved", "ROM table", "Reserved", "Reserved",
1264 "Reserved", "Reserved", "Reserved", "Reserved",
1265 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1266 "Reserved", "OptimoDE DESS",
1267 "Generic IP component", "PrimeCell or System component"
1268 };
1269
1270 static bool
1271 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1272 {
1273 return cid3 == 0xb1 && cid2 == 0x05
1274 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1275 }
1276
1277 int dap_info_command(struct command_context *cmd_ctx,
1278 struct swjdp_common *swjdp, int apsel)
1279 {
1280
1281 uint32_t dbgbase, apid;
1282 int romtable_present = 0;
1283 uint8_t mem_ap;
1284 uint32_t apselold;
1285
1286 /* AP address is in bits 31:24 of DP_SELECT */
1287 if (apsel >= 256)
1288 return ERROR_INVALID_ARGUMENTS;
1289
1290 apselold = swjdp->apsel;
1291 dap_ap_select(swjdp, apsel);
1292 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1293 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1294 jtagdp_transaction_endcheck(swjdp);
1295 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1296 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1297 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1298 if (apid)
1299 {
1300 switch (apid&0x0F)
1301 {
1302 case 0:
1303 command_print(cmd_ctx, "\tType is JTAG-AP");
1304 break;
1305 case 1:
1306 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1307 break;
1308 case 2:
1309 command_print(cmd_ctx, "\tType is MEM-AP APB");
1310 break;
1311 default:
1312 command_print(cmd_ctx, "\tUnknown AP type");
1313 break;
1314 }
1315
1316 /* NOTE: a MEM-AP may have a single CoreSight component that's
1317 * not a ROM table ... or have no such components at all.
1318 */
1319 if (mem_ap)
1320 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1321 dbgbase);
1322 }
1323 else
1324 {
1325 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1326 }
1327
1328 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1329 if (romtable_present)
1330 {
1331 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1332 uint16_t entry_offset;
1333
1334 /* bit 16 of apid indicates a memory access port */
1335 if (dbgbase & 0x02)
1336 command_print(cmd_ctx, "\tValid ROM table present");
1337 else
1338 command_print(cmd_ctx, "\tROM table in legacy format");
1339
1340 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1341 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1342 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1343 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1344 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1345 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1346 jtagdp_transaction_endcheck(swjdp);
1347 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1348 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1349 ", CID2 0x%2.2" PRIx32
1350 ", CID1 0x%2.2" PRIx32
1351 ", CID0 0x%2.2" PRIx32,
1352 cid3, cid2, cid1, cid0);
1353 if (memtype & 0x01)
1354 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1355 else
1356 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1357 "Dedicated debug bus.");
1358
1359 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1360 entry_offset = 0;
1361 do
1362 {
1363 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1364 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1365 if (romentry&0x01)
1366 {
1367 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1368 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1369 uint32_t component_start, component_base;
1370 unsigned part_num;
1371 char *type, *full;
1372
1373 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1374 + (int)(romentry & 0xFFFFF000));
1375 mem_ap_read_atomic_u32(swjdp,
1376 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1377 mem_ap_read_atomic_u32(swjdp,
1378 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1379 mem_ap_read_atomic_u32(swjdp,
1380 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1381 mem_ap_read_atomic_u32(swjdp,
1382 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1383 mem_ap_read_atomic_u32(swjdp,
1384 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1385 mem_ap_read_atomic_u32(swjdp,
1386 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1387 mem_ap_read_atomic_u32(swjdp,
1388 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1389 mem_ap_read_atomic_u32(swjdp,
1390 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1391 mem_ap_read_atomic_u32(swjdp,
1392 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1393 component_start = component_base - 0x1000*(c_pid4 >> 4);
1394
1395 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1396 ", start address 0x%" PRIx32,
1397 component_base, component_start);
1398 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1399 (int) (c_cid1 >> 4) & 0xf,
1400 /* See ARM IHI 0029B Table 3-3 */
1401 class_description[(c_cid1 >> 4) & 0xf]);
1402
1403 /* CoreSight component? */
1404 if (((c_cid1 >> 4) & 0x0f) == 9) {
1405 uint32_t devtype;
1406 unsigned minor;
1407 char *major = "Reserved", *subtype = "Reserved";
1408
1409 mem_ap_read_atomic_u32(swjdp,
1410 (component_base & 0xfffff000) | 0xfcc,
1411 &devtype);
1412 minor = (devtype >> 4) & 0x0f;
1413 switch (devtype & 0x0f) {
1414 case 0:
1415 major = "Miscellaneous";
1416 switch (minor) {
1417 case 0:
1418 subtype = "other";
1419 break;
1420 case 4:
1421 subtype = "Validation component";
1422 break;
1423 }
1424 break;
1425 case 1:
1426 major = "Trace Sink";
1427 switch (minor) {
1428 case 0:
1429 subtype = "other";
1430 break;
1431 case 1:
1432 subtype = "Port";
1433 break;
1434 case 2:
1435 subtype = "Buffer";
1436 break;
1437 }
1438 break;
1439 case 2:
1440 major = "Trace Link";
1441 switch (minor) {
1442 case 0:
1443 subtype = "other";
1444 break;
1445 case 1:
1446 subtype = "Funnel, router";
1447 break;
1448 case 2:
1449 subtype = "Filter";
1450 break;
1451 case 3:
1452 subtype = "FIFO, buffer";
1453 break;
1454 }
1455 break;
1456 case 3:
1457 major = "Trace Source";
1458 switch (minor) {
1459 case 0:
1460 subtype = "other";
1461 break;
1462 case 1:
1463 subtype = "Processor";
1464 break;
1465 case 2:
1466 subtype = "DSP";
1467 break;
1468 case 3:
1469 subtype = "Engine/Coprocessor";
1470 break;
1471 case 4:
1472 subtype = "Bus";
1473 break;
1474 }
1475 break;
1476 case 4:
1477 major = "Debug Control";
1478 switch (minor) {
1479 case 0:
1480 subtype = "other";
1481 break;
1482 case 1:
1483 subtype = "Trigger Matrix";
1484 break;
1485 case 2:
1486 subtype = "Debug Auth";
1487 break;
1488 }
1489 break;
1490 case 5:
1491 major = "Debug Logic";
1492 switch (minor) {
1493 case 0:
1494 subtype = "other";
1495 break;
1496 case 1:
1497 subtype = "Processor";
1498 break;
1499 case 2:
1500 subtype = "DSP";
1501 break;
1502 case 3:
1503 subtype = "Engine/Coprocessor";
1504 break;
1505 }
1506 break;
1507 }
1508 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1509 (unsigned) (devtype & 0xff),
1510 major, subtype);
1511 /* REVISIT also show 0xfc8 DevId */
1512 }
1513
1514 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1515 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1516 ", CID2 0x%2.2" PRIx32
1517 ", CID1 0x%2.2" PRIx32
1518 ", CID0 0x%2.2" PRIx32,
1519 c_cid3, c_cid2, c_cid1, c_cid0);
1520 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1521 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1522 (int) c_pid4,
1523 (int) c_pid3, (int) c_pid2,
1524 (int) c_pid1, (int) c_pid0);
1525
1526 /* Part number interpretations are from Cortex
1527 * core specs, the CoreSight components TRM
1528 * (ARM DDI 0314H), and ETM specs; also from
1529 * chip observation (e.g. TI SDTI).
1530 */
1531 part_num = c_pid0 & 0xff;
1532 part_num |= (c_pid1 & 0x0f) << 8;
1533 switch (part_num) {
1534 case 0x000:
1535 type = "Cortex-M3 NVIC";
1536 full = "(Interrupt Controller)";
1537 break;
1538 case 0x001:
1539 type = "Cortex-M3 ITM";
1540 full = "(Instrumentation Trace Module)";
1541 break;
1542 case 0x002:
1543 type = "Cortex-M3 DWT";
1544 full = "(Data Watchpoint and Trace)";
1545 break;
1546 case 0x003:
1547 type = "Cortex-M3 FBP";
1548 full = "(Flash Patch and Breakpoint)";
1549 break;
1550 case 0x00d:
1551 type = "CoreSight ETM11";
1552 full = "(Embedded Trace)";
1553 break;
1554 // case 0x113: what?
1555 case 0x120: /* from OMAP3 memmap */
1556 type = "TI SDTI";
1557 full = "(System Debug Trace Interface)";
1558 break;
1559 case 0x343: /* from OMAP3 memmap */
1560 type = "TI DAPCTL";
1561 full = "";
1562 break;
1563 case 0x4e0:
1564 type = "Cortex-M3 ETM";
1565 full = "(Embedded Trace)";
1566 break;
1567 case 0x906:
1568 type = "Coresight CTI";
1569 full = "(Cross Trigger)";
1570 break;
1571 case 0x907:
1572 type = "Coresight ETB";
1573 full = "(Trace Buffer)";
1574 break;
1575 case 0x908:
1576 type = "Coresight CSTF";
1577 full = "(Trace Funnel)";
1578 break;
1579 case 0x910:
1580 type = "CoreSight ETM9";
1581 full = "(Embedded Trace)";
1582 break;
1583 case 0x912:
1584 type = "Coresight TPIU";
1585 full = "(Trace Port Interface Unit)";
1586 break;
1587 case 0x921:
1588 type = "Cortex-A8 ETM";
1589 full = "(Embedded Trace)";
1590 break;
1591 case 0x922:
1592 type = "Cortex-A8 CTI";
1593 full = "(Cross Trigger)";
1594 break;
1595 case 0x923:
1596 type = "Cortex-M3 TPIU";
1597 full = "(Trace Port Interface Unit)";
1598 break;
1599 case 0xc08:
1600 type = "Cortex-A8 Debug";
1601 full = "(Debug Unit)";
1602 break;
1603 default:
1604 type = "-*- unrecognized -*-";
1605 full = "";
1606 break;
1607 }
1608 command_print(cmd_ctx, "\t\tPart is %s %s",
1609 type, full);
1610 }
1611 else
1612 {
1613 if (romentry)
1614 command_print(cmd_ctx, "\t\tComponent not present");
1615 else
1616 command_print(cmd_ctx, "\t\tEnd of ROM table");
1617 }
1618 entry_offset += 4;
1619 } while (romentry > 0);
1620 }
1621 else
1622 {
1623 command_print(cmd_ctx, "\tNo ROM table present");
1624 }
1625 dap_ap_select(swjdp, apselold);
1626
1627 return ERROR_OK;
1628 }
1629
1630 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1631 {
1632 uint32_t apsel, apselsave, baseaddr;
1633 int retval;
1634
1635 apselsave = swjdp->apsel;
1636 switch (CMD_ARGC) {
1637 case 0:
1638 apsel = swjdp->apsel;
1639 break;
1640 case 1:
1641 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1642 /* AP address is in bits 31:24 of DP_SELECT */
1643 if (apsel >= 256)
1644 return ERROR_INVALID_ARGUMENTS;
1645 break;
1646 default:
1647 return ERROR_COMMAND_SYNTAX_ERROR;
1648 }
1649
1650 if (apselsave != apsel)
1651 dap_ap_select(swjdp, apsel);
1652
1653 /* NOTE: assumes we're talking to a MEM-AP, which
1654 * has a base address. There are other kinds of AP,
1655 * though they're not common for now. This should
1656 * use the ID register to verify it's a MEM-AP.
1657 */
1658 dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1659 retval = jtagdp_transaction_endcheck(swjdp);
1660 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1661
1662 if (apselsave != apsel)
1663 dap_ap_select(swjdp, apselsave);
1664
1665 return retval;
1666 }
1667
1668 DAP_COMMAND_HANDLER(dap_memaccess_command)
1669 {
1670 uint32_t memaccess_tck;
1671
1672 switch (CMD_ARGC) {
1673 case 0:
1674 memaccess_tck = swjdp->memaccess_tck;
1675 break;
1676 case 1:
1677 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1678 break;
1679 default:
1680 return ERROR_COMMAND_SYNTAX_ERROR;
1681 }
1682 swjdp->memaccess_tck = memaccess_tck;
1683
1684 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1685 swjdp->memaccess_tck);
1686
1687 return ERROR_OK;
1688 }
1689
1690 DAP_COMMAND_HANDLER(dap_apsel_command)
1691 {
1692 uint32_t apsel, apid;
1693 int retval;
1694
1695 switch (CMD_ARGC) {
1696 case 0:
1697 apsel = 0;
1698 break;
1699 case 1:
1700 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1701 /* AP address is in bits 31:24 of DP_SELECT */
1702 if (apsel >= 256)
1703 return ERROR_INVALID_ARGUMENTS;
1704 break;
1705 default:
1706 return ERROR_COMMAND_SYNTAX_ERROR;
1707 }
1708
1709 dap_ap_select(swjdp, apsel);
1710 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1711 retval = jtagdp_transaction_endcheck(swjdp);
1712 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1713 apsel, apid);
1714
1715 return retval;
1716 }
1717
1718 DAP_COMMAND_HANDLER(dap_apid_command)
1719 {
1720 uint32_t apsel, apselsave, apid;
1721 int retval;
1722
1723 apselsave = swjdp->apsel;
1724 switch (CMD_ARGC) {
1725 case 0:
1726 apsel = swjdp->apsel;
1727 break;
1728 case 1:
1729 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1730 /* AP address is in bits 31:24 of DP_SELECT */
1731 if (apsel >= 256)
1732 return ERROR_INVALID_ARGUMENTS;
1733 break;
1734 default:
1735 return ERROR_COMMAND_SYNTAX_ERROR;
1736 }
1737
1738 if (apselsave != apsel)
1739 dap_ap_select(swjdp, apsel);
1740
1741 dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1742 retval = jtagdp_transaction_endcheck(swjdp);
1743 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1744 if (apselsave != apsel)
1745 dap_ap_select(swjdp, apselsave);
1746
1747 return retval;
1748 }
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