1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
72 #include "arm_adi_v5.h"
73 #include <helper/time_support.h>
76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
79 uint32_t tar_block_size(uint32_t address)
80 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
84 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
87 /***************************************************************************
89 * DPACC and APACC scanchain access through JTAG-DP *
91 ***************************************************************************/
94 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
95 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
96 * discusses operations which access these registers.
98 * Note that only one scan is performed. If RnW is set, a separate scan
99 * will be needed to collect the data which was read; the "invalue" collects
100 * the posted result of a preceding operation, not the current one.
102 * @param swjdp the DAP
103 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
104 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
105 * SELECT register has more addressing bits.
106 * @param RnW false iff outvalue will be written to the DP or AP
107 * @param outvalue points to a 32-bit (little-endian) integer
108 * @param invalue NULL, or points to a 32-bit (little-endian) integer
109 * @param ack points to where the three bit JTAG_ACK_* code will be stored
111 static int adi_jtag_dp_scan(struct swjdp_common
*swjdp
,
112 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
113 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
)
115 struct arm_jtag
*jtag_info
= swjdp
->jtag_info
;
116 struct scan_field fields
[2];
117 uint8_t out_addr_buf
;
119 jtag_set_end_state(TAP_IDLE
);
120 arm_jtag_set_instr(jtag_info
, instr
, NULL
);
122 /* Scan out a read or write operation using some DP or AP register.
123 * For APACC access with any sticky error flag set, this is discarded.
125 fields
[0].tap
= jtag_info
->tap
;
126 fields
[0].num_bits
= 3;
127 buf_set_u32(&out_addr_buf
, 0, 3, ((reg_addr
>> 1) & 0x6) | (RnW
& 0x1));
128 fields
[0].out_value
= &out_addr_buf
;
129 fields
[0].in_value
= ack
;
131 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
132 * complete; data we write is discarded, data we read is unpredictable.
133 * When overrun detect is active, STICKYORUN is set.
136 fields
[1].tap
= jtag_info
->tap
;
137 fields
[1].num_bits
= 32;
138 fields
[1].out_value
= outvalue
;
139 fields
[1].in_value
= invalue
;
141 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
143 /* Add specified number of tck clocks after starting memory bus
144 * access, giving the hardware time to complete the access.
145 * They provide more time for the (MEM) AP to complete the read ...
146 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
148 if ((instr
== JTAG_DP_APACC
)
149 && ((reg_addr
== AP_REG_DRW
)
150 || ((reg_addr
& 0xF0) == AP_REG_BD0
))
151 && (swjdp
->memaccess_tck
!= 0))
152 jtag_add_runtest(swjdp
->memaccess_tck
,
153 jtag_set_end_state(TAP_IDLE
));
155 return jtag_get_error();
159 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
160 * This is exactly like adi_jtag_dp_scan(), except that endianness
161 * conversions are performed (so the types of invalue and outvalue
162 * must be different).
164 static int adi_jtag_dp_scan_u32(struct swjdp_common
*swjdp
,
165 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
166 uint32_t outvalue
, uint32_t *invalue
, uint8_t *ack
)
168 uint8_t out_value_buf
[4];
171 buf_set_u32(out_value_buf
, 0, 32, outvalue
);
173 retval
= adi_jtag_dp_scan(swjdp
, instr
, reg_addr
, RnW
,
174 out_value_buf
, (uint8_t *)invalue
, ack
);
175 if (retval
!= ERROR_OK
)
179 jtag_add_callback(arm_le_to_h_u32
,
180 (jtag_callback_data_t
) invalue
);
186 * Utility to write AP registers.
188 static inline int adi_jtag_ap_write_check(struct swjdp_common
*dap
,
189 uint8_t reg_addr
, uint8_t *outvalue
)
191 return adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, reg_addr
, DPAP_WRITE
,
192 outvalue
, NULL
, NULL
);
195 static int adi_jtag_scan_inout_check_u32(struct swjdp_common
*swjdp
,
196 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
197 uint32_t outvalue
, uint32_t *invalue
)
201 /* Issue the read or write */
202 retval
= adi_jtag_dp_scan_u32(swjdp
, instr
, reg_addr
,
203 RnW
, outvalue
, NULL
, NULL
);
204 if (retval
!= ERROR_OK
)
207 /* For reads, collect posted value; RDBUFF has no other effect.
208 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
210 if ((RnW
== DPAP_READ
) && (invalue
!= NULL
))
211 retval
= adi_jtag_dp_scan_u32(swjdp
, JTAG_DP_DPACC
,
212 DP_RDBUFF
, DPAP_READ
, 0, invalue
, &swjdp
->ack
);
216 static int jtagdp_transaction_endcheck(struct swjdp_common
*swjdp
)
221 /* too expensive to call keep_alive() here */
224 /* Danger!!!! BROKEN!!!! */
225 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
226 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
227 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
228 R956 introduced the check on return value here and now Michael Schwingen reports
229 that this code no longer works....
231 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
233 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
235 LOG_ERROR("BUG: Why does this fail the first time????");
237 /* Why??? second time it works??? */
240 /* Post CTRL/STAT read; discard any previous posted read value
241 * but collect its ACK status.
243 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
244 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
245 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
248 swjdp
->ack
= swjdp
->ack
& 0x7;
250 /* common code path avoids calling timeval_ms() */
251 if (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
253 long long then
= timeval_ms();
255 while (swjdp
->ack
!= JTAG_ACK_OK_FAULT
)
257 if (swjdp
->ack
== JTAG_ACK_WAIT
)
259 if ((timeval_ms()-then
) > 1000)
261 /* NOTE: this would be a good spot
262 * to use JTAG_DP_ABORT.
264 LOG_WARNING("Timeout (1000ms) waiting "
266 "in JTAG-DP transaction");
267 return ERROR_JTAG_DEVICE_ERROR
;
272 LOG_WARNING("Invalid ACK %#x "
273 "in JTAG-DP transaction",
275 return ERROR_JTAG_DEVICE_ERROR
;
278 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
279 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
280 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
282 swjdp
->ack
= swjdp
->ack
& 0x7;
286 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
288 /* Check for STICKYERR and STICKYORUN */
289 if (ctrlstat
& (SSTICKYORUN
| SSTICKYERR
))
291 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32
, ctrlstat
);
292 /* Check power to debug regions */
293 if ((ctrlstat
& 0xf0000000) != 0xf0000000)
294 ahbap_debugport_init(swjdp
);
297 uint32_t mem_ap_csw
, mem_ap_tar
;
299 /* Maybe print information about last intended
300 * MEM-AP access; but not if autoincrementing.
301 * *Real* CSW and TAR values are always shown.
303 if (swjdp
->ap_tar_value
!= (uint32_t) -1)
304 LOG_DEBUG("MEM-AP Cached values: "
306 ", ap_csw 0x%" PRIx32
307 ", ap_tar 0x%" PRIx32
,
308 swjdp
->ap_bank_value
,
310 swjdp
->ap_tar_value
);
312 if (ctrlstat
& SSTICKYORUN
)
313 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
314 "memaccess, or reduce jtag speed");
316 if (ctrlstat
& SSTICKYERR
)
317 LOG_ERROR("JTAG-DP STICKY ERROR");
319 /* Clear Sticky Error Bits */
320 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
321 DP_CTRL_STAT
, DPAP_WRITE
,
322 swjdp
->dp_ctrl_stat
| SSTICKYORUN
324 adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
325 DP_CTRL_STAT
, DPAP_READ
, 0, &ctrlstat
);
326 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
329 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32
, ctrlstat
);
331 dap_ap_read_reg_u32(swjdp
, AP_REG_CSW
, &mem_ap_csw
);
332 dap_ap_read_reg_u32(swjdp
, AP_REG_TAR
, &mem_ap_tar
);
333 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
335 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32
", MEM_AP_TAR 0x%"
336 PRIx32
, mem_ap_csw
, mem_ap_tar
);
339 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
341 return ERROR_JTAG_DEVICE_ERROR
;
347 /***************************************************************************
349 * DP and MEM-AP register access through APACC and DPACC *
351 ***************************************************************************/
353 /* FIXME remove dap_dp_{read,write}_reg() ... these should become the
354 * bodies of the JTAG implementations of dap_queue_dp_{read,write}() and
355 * callers should switch over to the transport-neutral calls.
358 static int dap_dp_write_reg(struct swjdp_common
*swjdp
,
359 uint32_t value
, uint8_t reg_addr
)
361 return adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
362 reg_addr
, DPAP_WRITE
, value
, NULL
);
365 static int dap_dp_read_reg(struct swjdp_common
*swjdp
,
366 uint32_t *value
, uint8_t reg_addr
)
368 return adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_DPACC
,
369 reg_addr
, DPAP_READ
, 0, value
);
373 * Select one of the APs connected to the specified DAP. The
374 * selection is implicitly used with future AP transactions.
375 * This is a NOP if the specified AP is already selected.
377 * @param swjdp The DAP
378 * @param apsel Number of the AP to (implicitly) use with further
379 * transactions. This normally identifies a MEM-AP.
381 void dap_ap_select(struct swjdp_common
*swjdp
,uint8_t apsel
)
383 uint32_t select
= (apsel
<< 24) & 0xFF000000;
385 if (select
!= swjdp
->apsel
)
387 swjdp
->apsel
= select
;
388 /* Switching AP invalidates cached values.
389 * Values MUST BE UPDATED BEFORE AP ACCESS.
391 swjdp
->ap_bank_value
= -1;
392 swjdp
->ap_csw_value
= -1;
393 swjdp
->ap_tar_value
= -1;
397 /** Select the AP register bank matching bits 7:4 of ap_reg. */
398 static int dap_ap_bankselect(struct swjdp_common
*swjdp
, uint32_t ap_reg
)
400 uint32_t select
= (ap_reg
& 0x000000F0);
402 if (select
!= swjdp
->ap_bank_value
)
404 swjdp
->ap_bank_value
= select
;
405 select
|= swjdp
->apsel
;
406 return dap_dp_write_reg(swjdp
, select
, DP_SELECT
);
411 /* FIXME remove dap_ap_{read,write}_reg() and dap_ap_write_reg_u32()
412 * ... these should become the bodies of the JTAG implementations of
413 * dap_queue_ap_{read,write}(), then all their current callers should
414 * switch over to the transport-neutral calls.
417 static int dap_ap_write_reg(struct swjdp_common
*swjdp
,
418 uint32_t reg_addr
, uint8_t *out_value_buf
)
422 retval
= dap_ap_bankselect(swjdp
, reg_addr
);
423 if (retval
!= ERROR_OK
)
426 return adi_jtag_ap_write_check(swjdp
, reg_addr
, out_value_buf
);
430 * Asynchronous (queued) AP register write.
432 * @param swjdp The DAP whose currently selected AP will be written.
433 * @param reg_addr Eight bit AP register address.
434 * @param value Word to be written at reg_addr
436 * @return ERROR_OK if the transaction was properly queued, else a fault code.
438 int dap_ap_write_reg_u32(struct swjdp_common
*swjdp
,
439 uint32_t reg_addr
, uint32_t value
)
441 uint8_t out_value_buf
[4];
443 buf_set_u32(out_value_buf
, 0, 32, value
);
444 return dap_ap_write_reg(swjdp
,
445 reg_addr
, out_value_buf
);
449 * Asynchronous (queued) AP register eread.
451 * @param swjdp The DAP whose currently selected AP will be read.
452 * @param reg_addr Eight bit AP register address.
453 * @param value Points to where the 32-bit (little-endian) word will be stored.
455 * @return ERROR_OK if the transaction was properly queued, else a fault code.
457 int dap_ap_read_reg_u32(struct swjdp_common
*swjdp
,
458 uint32_t reg_addr
, uint32_t *value
)
462 retval
= dap_ap_bankselect(swjdp
, reg_addr
);
463 if (retval
!= ERROR_OK
)
466 return adi_jtag_scan_inout_check_u32(swjdp
, JTAG_DP_APACC
, reg_addr
,
467 DPAP_READ
, 0, value
);
471 * Queue transactions setting up transfer parameters for the
472 * currently selected MEM-AP.
474 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
475 * initiate data reads or writes using memory or peripheral addresses.
476 * If the CSW is configured for it, the TAR may be automatically
477 * incremented after each transfer.
479 * @todo Rename to reflect it being specifically a MEM-AP function.
481 * @param swjdp The DAP connected to the MEM-AP.
482 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
483 * matches the cached value, the register is not changed.
484 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
485 * matches the cached address, the register is not changed.
487 * @return ERROR_OK if the transaction was properly queued, else a fault code.
489 int dap_setup_accessport(struct swjdp_common
*swjdp
, uint32_t csw
, uint32_t tar
)
493 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
494 if (csw
!= swjdp
->ap_csw_value
)
496 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
497 retval
= dap_ap_write_reg_u32(swjdp
, AP_REG_CSW
, csw
);
498 if (retval
!= ERROR_OK
)
500 swjdp
->ap_csw_value
= csw
;
502 if (tar
!= swjdp
->ap_tar_value
)
504 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
505 retval
= dap_ap_write_reg_u32(swjdp
, AP_REG_TAR
, tar
);
506 if (retval
!= ERROR_OK
)
508 swjdp
->ap_tar_value
= tar
;
510 /* Disable TAR cache when autoincrementing */
511 if (csw
& CSW_ADDRINC_MASK
)
512 swjdp
->ap_tar_value
= -1;
517 * Asynchronous (queued) read of a word from memory or a system register.
519 * @param swjdp The DAP connected to the MEM-AP performing the read.
520 * @param address Address of the 32-bit word to read; it must be
521 * readable by the currently selected MEM-AP.
522 * @param value points to where the word will be stored when the
523 * transaction queue is flushed (assuming no errors).
525 * @return ERROR_OK for success. Otherwise a fault code.
527 int mem_ap_read_u32(struct swjdp_common
*swjdp
, uint32_t address
,
532 /* Use banked addressing (REG_BDx) to avoid some link traffic
533 * (updating TAR) when reading several consecutive addresses.
535 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
,
536 address
& 0xFFFFFFF0);
537 if (retval
!= ERROR_OK
)
540 return dap_ap_read_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC), value
);
544 * Synchronous read of a word from memory or a system register.
545 * As a side effect, this flushes any queued transactions.
547 * @param swjdp The DAP connected to the MEM-AP performing the read.
548 * @param address Address of the 32-bit word to read; it must be
549 * readable by the currently selected MEM-AP.
550 * @param value points to where the result will be stored.
552 * @return ERROR_OK for success; *value holds the result.
553 * Otherwise a fault code.
555 int mem_ap_read_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
,
560 retval
= mem_ap_read_u32(swjdp
, address
, value
);
561 if (retval
!= ERROR_OK
)
564 return dap_run(swjdp
);
568 * Asynchronous (queued) write of a word to memory or a system register.
570 * @param swjdp The DAP connected to the MEM-AP.
571 * @param address Address to be written; it must be writable by
572 * the currently selected MEM-AP.
573 * @param value Word that will be written to the address when transaction
574 * queue is flushed (assuming no errors).
576 * @return ERROR_OK for success. Otherwise a fault code.
578 int mem_ap_write_u32(struct swjdp_common
*swjdp
, uint32_t address
,
583 /* Use banked addressing (REG_BDx) to avoid some link traffic
584 * (updating TAR) when writing several consecutive addresses.
586 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
,
587 address
& 0xFFFFFFF0);
588 if (retval
!= ERROR_OK
)
591 return dap_ap_write_reg_u32(swjdp
, AP_REG_BD0
| (address
& 0xC),
596 * Synchronous write of a word to memory or a system register.
597 * As a side effect, this flushes any queued transactions.
599 * @param swjdp The DAP connected to the MEM-AP.
600 * @param address Address to be written; it must be writable by
601 * the currently selected MEM-AP.
602 * @param value Word that will be written.
604 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
606 int mem_ap_write_atomic_u32(struct swjdp_common
*swjdp
, uint32_t address
,
609 int retval
= mem_ap_write_u32(swjdp
, address
, value
);
611 if (retval
!= ERROR_OK
)
614 return dap_run(swjdp
);
617 /*****************************************************************************
619 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
621 * Write a buffer in target order (little endian) *
623 *****************************************************************************/
624 int mem_ap_write_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
626 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
627 uint32_t adr
= address
;
628 uint8_t* pBuffer
= buffer
;
633 /* if we have an unaligned access - reorder data */
636 for (writecount
= 0; writecount
< count
; writecount
++)
640 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
642 for (i
= 0; i
< 4; i
++)
644 *((uint8_t*)pBuffer
+ (adr
& 0x3)) = outvalue
;
648 pBuffer
+= sizeof(uint32_t);
654 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
655 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
656 if (wcount
< blocksize
)
659 /* handle unaligned data at 4k boundary */
663 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
665 for (writecount
= 0; writecount
< blocksize
; writecount
++)
667 dap_ap_write_reg(swjdp
, AP_REG_DRW
, buffer
+ 4 * writecount
);
670 if (dap_run(swjdp
) == ERROR_OK
)
672 wcount
= wcount
- blocksize
;
673 address
= address
+ 4 * blocksize
;
674 buffer
= buffer
+ 4 * blocksize
;
683 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
684 /* REVISIT return the *actual* fault code */
685 return ERROR_JTAG_DEVICE_ERROR
;
692 static int mem_ap_write_buf_packed_u16(struct swjdp_common
*swjdp
,
693 uint8_t *buffer
, int count
, uint32_t address
)
695 int retval
= ERROR_OK
;
696 int wcount
, blocksize
, writecount
, i
;
704 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
705 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
707 if (wcount
< blocksize
)
710 /* handle unaligned data at 4k boundary */
714 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
715 writecount
= blocksize
;
719 nbytes
= MIN((writecount
<< 1), 4);
723 if (mem_ap_write_buf_u16(swjdp
, buffer
,
724 nbytes
, address
) != ERROR_OK
)
726 LOG_WARNING("Block write error address "
727 "0x%" PRIx32
", count 0x%x",
729 return ERROR_JTAG_DEVICE_ERROR
;
732 address
+= nbytes
>> 1;
737 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
739 for (i
= 0; i
< nbytes
; i
++)
741 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
746 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
747 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
748 if (dap_run(swjdp
) != ERROR_OK
)
750 LOG_WARNING("Block write error address "
751 "0x%" PRIx32
", count 0x%x",
753 /* REVISIT return *actual* fault code */
754 return ERROR_JTAG_DEVICE_ERROR
;
758 buffer
+= nbytes
>> 1;
759 writecount
-= nbytes
>> 1;
761 } while (writecount
);
768 int mem_ap_write_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
770 int retval
= ERROR_OK
;
773 return mem_ap_write_buf_packed_u16(swjdp
, buffer
, count
, address
);
777 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
779 memcpy(&svalue
, buffer
, sizeof(uint16_t));
780 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
781 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
782 retval
= dap_run(swjdp
);
783 if (retval
!= ERROR_OK
)
794 static int mem_ap_write_buf_packed_u8(struct swjdp_common
*swjdp
,
795 uint8_t *buffer
, int count
, uint32_t address
)
797 int retval
= ERROR_OK
;
798 int wcount
, blocksize
, writecount
, i
;
806 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
807 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
809 if (wcount
< blocksize
)
812 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
813 writecount
= blocksize
;
817 nbytes
= MIN(writecount
, 4);
821 if (mem_ap_write_buf_u8(swjdp
, buffer
, nbytes
, address
) != ERROR_OK
)
823 LOG_WARNING("Block write error address "
824 "0x%" PRIx32
", count 0x%x",
826 return ERROR_JTAG_DEVICE_ERROR
;
834 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
836 for (i
= 0; i
< nbytes
; i
++)
838 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
843 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
844 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
845 if (dap_run(swjdp
) != ERROR_OK
)
847 LOG_WARNING("Block write error address "
848 "0x%" PRIx32
", count 0x%x",
850 /* REVISIT return *actual* fault code */
851 return ERROR_JTAG_DEVICE_ERROR
;
856 writecount
-= nbytes
;
858 } while (writecount
);
865 int mem_ap_write_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
, int count
, uint32_t address
)
867 int retval
= ERROR_OK
;
870 return mem_ap_write_buf_packed_u8(swjdp
, buffer
, count
, address
);
874 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
875 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
876 dap_ap_write_reg_u32(swjdp
, AP_REG_DRW
, outvalue
);
877 retval
= dap_run(swjdp
);
878 if (retval
!= ERROR_OK
)
890 * Synchronously read a block of 32-bit words into a buffer
891 * @param swjdp The DAP connected to the MEM-AP.
892 * @param buffer where the words will be stored (in host byte order).
893 * @param count How many words to read.
894 * @param address Memory address from which to read words; all the
895 * words must be readable by the currently selected MEM-AP.
897 int mem_ap_read_buf_u32(struct swjdp_common
*swjdp
, uint8_t *buffer
,
898 int count
, uint32_t address
)
900 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
901 uint32_t adr
= address
;
902 uint8_t* pBuffer
= buffer
;
909 /* Adjust to read blocks within boundaries aligned to the
910 * TAR autoincrement size (at least 2^10). Autoincrement
911 * mode avoids an extra per-word roundtrip to update TAR.
913 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
,
915 if (wcount
< blocksize
)
918 /* handle unaligned data at 4k boundary */
922 dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_SINGLE
,
925 /* Scan out first read */
926 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
927 DPAP_READ
, 0, NULL
, NULL
);
928 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
930 /* Scan out next read; scan in posted value for the
931 * previous one. Assumes read is acked "OK/FAULT",
932 * and CTRL_STAT says that meant "OK".
934 adi_jtag_dp_scan(swjdp
, JTAG_DP_APACC
, AP_REG_DRW
,
935 DPAP_READ
, 0, buffer
+ 4 * readcount
,
939 /* Scan in last posted value; RDBUFF has no other effect,
940 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
942 adi_jtag_dp_scan(swjdp
, JTAG_DP_DPACC
, DP_RDBUFF
,
943 DPAP_READ
, 0, buffer
+ 4 * readcount
,
945 if (dap_run(swjdp
) == ERROR_OK
)
947 wcount
= wcount
- blocksize
;
948 address
+= 4 * blocksize
;
949 buffer
+= 4 * blocksize
;
958 LOG_WARNING("Block read error address 0x%" PRIx32
959 ", count 0x%x", address
, count
);
960 /* REVISIT return the *actual* fault code */
961 return ERROR_JTAG_DEVICE_ERROR
;
965 /* if we have an unaligned access - reorder data */
968 for (readcount
= 0; readcount
< count
; readcount
++)
972 memcpy(&data
, pBuffer
, sizeof(uint32_t));
974 for (i
= 0; i
< 4; i
++)
976 *((uint8_t*)pBuffer
) =
977 (data
>> 8 * (adr
& 0x3));
987 static int mem_ap_read_buf_packed_u16(struct swjdp_common
*swjdp
,
988 uint8_t *buffer
, int count
, uint32_t address
)
991 int retval
= ERROR_OK
;
992 int wcount
, blocksize
, readcount
, i
;
1000 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1001 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
1002 if (wcount
< blocksize
)
1005 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
1007 /* handle unaligned data at 4k boundary */
1010 readcount
= blocksize
;
1014 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1015 if (dap_run(swjdp
) != ERROR_OK
)
1017 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
1018 /* REVISIT return the *actual* fault code */
1019 return ERROR_JTAG_DEVICE_ERROR
;
1022 nbytes
= MIN((readcount
<< 1), 4);
1024 for (i
= 0; i
< nbytes
; i
++)
1026 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1031 readcount
-= (nbytes
>> 1);
1032 } while (readcount
);
1033 wcount
-= blocksize
;
1040 * Synchronously read a block of 16-bit halfwords into a buffer
1041 * @param swjdp The DAP connected to the MEM-AP.
1042 * @param buffer where the halfwords will be stored (in host byte order).
1043 * @param count How many halfwords to read.
1044 * @param address Memory address from which to read words; all the
1045 * words must be readable by the currently selected MEM-AP.
1047 int mem_ap_read_buf_u16(struct swjdp_common
*swjdp
, uint8_t *buffer
,
1048 int count
, uint32_t address
)
1050 uint32_t invalue
, i
;
1051 int retval
= ERROR_OK
;
1054 return mem_ap_read_buf_packed_u16(swjdp
, buffer
, count
, address
);
1058 dap_setup_accessport(swjdp
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
1059 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1060 retval
= dap_run(swjdp
);
1061 if (retval
!= ERROR_OK
)
1066 for (i
= 0; i
< 2; i
++)
1068 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1075 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
1076 memcpy(buffer
, &svalue
, sizeof(uint16_t));
1086 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1087 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1089 * The solution is to arrange for a large out/in scan in this loop and
1090 * and convert data afterwards.
1092 static int mem_ap_read_buf_packed_u8(struct swjdp_common
*swjdp
,
1093 uint8_t *buffer
, int count
, uint32_t address
)
1096 int retval
= ERROR_OK
;
1097 int wcount
, blocksize
, readcount
, i
;
1105 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1106 blocksize
= max_tar_block_size(swjdp
->tar_autoincr_block
, address
);
1108 if (wcount
< blocksize
)
1111 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
1112 readcount
= blocksize
;
1116 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1117 if (dap_run(swjdp
) != ERROR_OK
)
1119 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
1120 /* REVISIT return the *actual* fault code */
1121 return ERROR_JTAG_DEVICE_ERROR
;
1124 nbytes
= MIN(readcount
, 4);
1126 for (i
= 0; i
< nbytes
; i
++)
1128 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1133 readcount
-= nbytes
;
1134 } while (readcount
);
1135 wcount
-= blocksize
;
1142 * Synchronously read a block of bytes into a buffer
1143 * @param swjdp The DAP connected to the MEM-AP.
1144 * @param buffer where the bytes will be stored.
1145 * @param count How many bytes to read.
1146 * @param address Memory address from which to read data; all the
1147 * data must be readable by the currently selected MEM-AP.
1149 int mem_ap_read_buf_u8(struct swjdp_common
*swjdp
, uint8_t *buffer
,
1150 int count
, uint32_t address
)
1153 int retval
= ERROR_OK
;
1156 return mem_ap_read_buf_packed_u8(swjdp
, buffer
, count
, address
);
1160 dap_setup_accessport(swjdp
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
1161 dap_ap_read_reg_u32(swjdp
, AP_REG_DRW
, &invalue
);
1162 retval
= dap_run(swjdp
);
1163 if (retval
!= ERROR_OK
)
1166 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
1175 /*--------------------------------------------------------------------------*/
1177 static int jtag_idcode_q_read(struct swjdp_common
*dap
,
1178 uint8_t *ack
, uint32_t *data
)
1180 struct arm_jtag
*jtag_info
= dap
->jtag_info
;
1182 struct scan_field fields
[1];
1184 jtag_set_end_state(TAP_IDLE
);
1186 /* This is a standard JTAG operation -- no DAP tweakage */
1187 retval
= arm_jtag_set_instr(jtag_info
, JTAG_DP_IDCODE
, NULL
);
1188 if (retval
!= ERROR_OK
)
1191 fields
[0].tap
= jtag_info
->tap
;
1192 fields
[0].num_bits
= 32;
1193 fields
[0].out_value
= NULL
;
1194 fields
[0].in_value
= (void *) data
;
1196 jtag_add_dr_scan(1, fields
, jtag_get_end_state());
1197 retval
= jtag_get_error();
1198 if (retval
!= ERROR_OK
)
1201 jtag_add_callback(arm_le_to_h_u32
,
1202 (jtag_callback_data_t
) data
);
1207 static int jtag_dp_q_read(struct swjdp_common
*dap
, unsigned reg
,
1210 return dap_dp_read_reg(dap
, data
, reg
);
1213 static int jtag_dp_q_write(struct swjdp_common
*dap
, unsigned reg
,
1216 return dap_dp_write_reg(dap
, data
, reg
);
1219 static int jtag_ap_q_bankselect(struct swjdp_common
*dap
, unsigned reg
)
1221 uint32_t select
= reg
& 0x000000F0;
1223 if (select
== dap
->ap_bank_value
)
1225 dap
->ap_bank_value
= select
;
1227 select
|= dap
->apsel
;
1229 return jtag_dp_q_write(dap
, DP_SELECT
, select
);
1232 static int jtag_ap_q_read(struct swjdp_common
*dap
, unsigned reg
,
1235 int retval
= jtag_ap_q_bankselect(dap
, reg
);
1237 if (retval
!= ERROR_OK
)
1239 return dap_ap_read_reg_u32(dap
, reg
, data
);
1242 static int jtag_ap_q_write(struct swjdp_common
*dap
, unsigned reg
,
1245 int retval
= jtag_ap_q_bankselect(dap
, reg
);
1247 if (retval
!= ERROR_OK
)
1249 return dap_ap_write_reg_u32(dap
, reg
, data
);
1252 static int jtag_ap_q_abort(struct swjdp_common
*dap
, uint8_t *ack
)
1254 /* for JTAG, this is the only valid ABORT register operation */
1255 return adi_jtag_dp_scan_u32(dap
, JTAG_DP_ABORT
,
1256 0, DPAP_WRITE
, 1, NULL
, ack
);
1259 static int jtag_dp_run(struct swjdp_common
*dap
)
1261 return jtagdp_transaction_endcheck(dap
);
1264 static const struct dap_ops jtag_dp_ops
= {
1265 .queue_idcode_read
= jtag_idcode_q_read
,
1266 .queue_dp_read
= jtag_dp_q_read
,
1267 .queue_dp_write
= jtag_dp_q_write
,
1268 .queue_ap_read
= jtag_ap_q_read
,
1269 .queue_ap_write
= jtag_ap_q_write
,
1270 .queue_ap_abort
= jtag_ap_q_abort
,
1274 /*--------------------------------------------------------------------------*/
1277 * Initialize a DAP. This sets up the power domains, prepares the DP
1278 * for further use, and arranges to use AP #0 for all AP operations
1279 * until dap_ap-select() changes that policy.
1281 * @param swjdp The DAP being initialized.
1283 * @todo Rename this. We also need an initialization scheme which account
1284 * for SWD transports not just JTAG; that will need to address differences
1285 * in layering. (JTAG is useful without any debug target; but not SWD.)
1286 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1288 int ahbap_debugport_init(struct swjdp_common
*swjdp
)
1290 uint32_t idreg
, romaddr
, dummy
;
1297 /* JTAG-DP or SWJ-DP, in JTAG mode */
1298 swjdp
->ops
= &jtag_dp_ops
;
1300 /* Default MEM-AP setup.
1302 * REVISIT AP #0 may be an inappropriate default for this.
1303 * Should we probe, or take a hint from the caller?
1304 * Presumably we can ignore the possibility of multiple APs.
1307 dap_ap_select(swjdp
, 0);
1309 /* DP initialization */
1310 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1311 dap_dp_write_reg(swjdp
, SSTICKYERR
, DP_CTRL_STAT
);
1312 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1314 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
1316 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1317 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1318 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
1321 /* Check that we have debug power domains activated */
1322 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
1324 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1325 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1326 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
1331 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
1333 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1334 dap_dp_read_reg(swjdp
, &ctrlstat
, DP_CTRL_STAT
);
1335 if ((retval
= dap_run(swjdp
)) != ERROR_OK
)
1340 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1341 /* With debug power on we can activate OVERRUN checking */
1342 swjdp
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
1343 dap_dp_write_reg(swjdp
, swjdp
->dp_ctrl_stat
, DP_CTRL_STAT
);
1344 dap_dp_read_reg(swjdp
, &dummy
, DP_CTRL_STAT
);
1347 * REVISIT this isn't actually *initializing* anything in an AP,
1348 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1349 * Should it? If the ROM address is valid, is this the right
1350 * place to scan the table and do any topology detection?
1352 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &idreg
);
1353 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &romaddr
);
1355 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1356 ", Debug ROM Address 0x%" PRIx32
,
1357 swjdp
->apsel
, idreg
, romaddr
);
1362 /* CID interpretation -- see ARM IHI 0029B section 3
1363 * and ARM IHI 0031A table 13-3.
1365 static const char *class_description
[16] ={
1366 "Reserved", "ROM table", "Reserved", "Reserved",
1367 "Reserved", "Reserved", "Reserved", "Reserved",
1368 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1369 "Reserved", "OptimoDE DESS",
1370 "Generic IP component", "PrimeCell or System component"
1374 is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1376 return cid3
== 0xb1 && cid2
== 0x05
1377 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1380 int dap_info_command(struct command_context
*cmd_ctx
,
1381 struct swjdp_common
*swjdp
, int apsel
)
1384 uint32_t dbgbase
, apid
;
1385 int romtable_present
= 0;
1389 /* AP address is in bits 31:24 of DP_SELECT */
1391 return ERROR_INVALID_ARGUMENTS
;
1393 apselold
= swjdp
->apsel
;
1394 dap_ap_select(swjdp
, apsel
);
1395 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &dbgbase
);
1396 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1397 retval
= dap_run(swjdp
);
1398 if (retval
!= ERROR_OK
)
1401 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1402 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1403 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1409 command_print(cmd_ctx
, "\tType is JTAG-AP");
1412 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1415 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1418 command_print(cmd_ctx
, "\tUnknown AP type");
1422 /* NOTE: a MEM-AP may have a single CoreSight component that's
1423 * not a ROM table ... or have no such components at all.
1426 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
,
1431 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1434 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1435 if (romtable_present
)
1437 uint32_t cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1438 uint16_t entry_offset
;
1440 /* bit 16 of apid indicates a memory access port */
1442 command_print(cmd_ctx
, "\tValid ROM table present");
1444 command_print(cmd_ctx
, "\tROM table in legacy format");
1446 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1447 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1448 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1449 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1450 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1451 mem_ap_read_u32(swjdp
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1452 retval
= dap_run(swjdp
);
1453 if (retval
!= ERROR_OK
)
1456 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1457 command_print(cmd_ctx
, "\tCID3 0x%2.2" PRIx32
1458 ", CID2 0x%2.2" PRIx32
1459 ", CID1 0x%2.2" PRIx32
1460 ", CID0 0x%2.2" PRIx32
,
1461 cid3
, cid2
, cid1
, cid0
);
1463 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1465 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1466 "Dedicated debug bus.");
1468 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1472 mem_ap_read_atomic_u32(swjdp
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1473 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"",entry_offset
,romentry
);
1476 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1477 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1478 uint32_t component_start
, component_base
;
1482 component_base
= (uint32_t)((dbgbase
& 0xFFFFF000)
1483 + (int)(romentry
& 0xFFFFF000));
1484 mem_ap_read_atomic_u32(swjdp
,
1485 (component_base
& 0xFFFFF000) | 0xFE0, &c_pid0
);
1486 mem_ap_read_atomic_u32(swjdp
,
1487 (component_base
& 0xFFFFF000) | 0xFE4, &c_pid1
);
1488 mem_ap_read_atomic_u32(swjdp
,
1489 (component_base
& 0xFFFFF000) | 0xFE8, &c_pid2
);
1490 mem_ap_read_atomic_u32(swjdp
,
1491 (component_base
& 0xFFFFF000) | 0xFEC, &c_pid3
);
1492 mem_ap_read_atomic_u32(swjdp
,
1493 (component_base
& 0xFFFFF000) | 0xFD0, &c_pid4
);
1494 mem_ap_read_atomic_u32(swjdp
,
1495 (component_base
& 0xFFFFF000) | 0xFF0, &c_cid0
);
1496 mem_ap_read_atomic_u32(swjdp
,
1497 (component_base
& 0xFFFFF000) | 0xFF4, &c_cid1
);
1498 mem_ap_read_atomic_u32(swjdp
,
1499 (component_base
& 0xFFFFF000) | 0xFF8, &c_cid2
);
1500 mem_ap_read_atomic_u32(swjdp
,
1501 (component_base
& 0xFFFFF000) | 0xFFC, &c_cid3
);
1502 component_start
= component_base
- 0x1000*(c_pid4
>> 4);
1504 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
1505 ", start address 0x%" PRIx32
,
1506 component_base
, component_start
);
1507 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1508 (int) (c_cid1
>> 4) & 0xf,
1509 /* See ARM IHI 0029B Table 3-3 */
1510 class_description
[(c_cid1
>> 4) & 0xf]);
1512 /* CoreSight component? */
1513 if (((c_cid1
>> 4) & 0x0f) == 9) {
1516 char *major
= "Reserved", *subtype
= "Reserved";
1518 mem_ap_read_atomic_u32(swjdp
,
1519 (component_base
& 0xfffff000) | 0xfcc,
1521 minor
= (devtype
>> 4) & 0x0f;
1522 switch (devtype
& 0x0f) {
1524 major
= "Miscellaneous";
1530 subtype
= "Validation component";
1535 major
= "Trace Sink";
1549 major
= "Trace Link";
1555 subtype
= "Funnel, router";
1561 subtype
= "FIFO, buffer";
1566 major
= "Trace Source";
1572 subtype
= "Processor";
1578 subtype
= "Engine/Coprocessor";
1586 major
= "Debug Control";
1592 subtype
= "Trigger Matrix";
1595 subtype
= "Debug Auth";
1600 major
= "Debug Logic";
1606 subtype
= "Processor";
1612 subtype
= "Engine/Coprocessor";
1617 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1618 (unsigned) (devtype
& 0xff),
1620 /* REVISIT also show 0xfc8 DevId */
1623 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1624 command_print(cmd_ctx
, "\t\tCID3 0x%2.2" PRIx32
1625 ", CID2 0x%2.2" PRIx32
1626 ", CID1 0x%2.2" PRIx32
1627 ", CID0 0x%2.2" PRIx32
,
1628 c_cid3
, c_cid2
, c_cid1
, c_cid0
);
1629 command_print(cmd_ctx
, "\t\tPeripheral ID[4..0] = hex "
1630 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1632 (int) c_pid3
, (int) c_pid2
,
1633 (int) c_pid1
, (int) c_pid0
);
1635 /* Part number interpretations are from Cortex
1636 * core specs, the CoreSight components TRM
1637 * (ARM DDI 0314H), and ETM specs; also from
1638 * chip observation (e.g. TI SDTI).
1640 part_num
= c_pid0
& 0xff;
1641 part_num
|= (c_pid1
& 0x0f) << 8;
1644 type
= "Cortex-M3 NVIC";
1645 full
= "(Interrupt Controller)";
1648 type
= "Cortex-M3 ITM";
1649 full
= "(Instrumentation Trace Module)";
1652 type
= "Cortex-M3 DWT";
1653 full
= "(Data Watchpoint and Trace)";
1656 type
= "Cortex-M3 FBP";
1657 full
= "(Flash Patch and Breakpoint)";
1660 type
= "CoreSight ETM11";
1661 full
= "(Embedded Trace)";
1663 // case 0x113: what?
1664 case 0x120: /* from OMAP3 memmap */
1666 full
= "(System Debug Trace Interface)";
1668 case 0x343: /* from OMAP3 memmap */
1673 type
= "Coresight CTI";
1674 full
= "(Cross Trigger)";
1677 type
= "Coresight ETB";
1678 full
= "(Trace Buffer)";
1681 type
= "Coresight CSTF";
1682 full
= "(Trace Funnel)";
1685 type
= "CoreSight ETM9";
1686 full
= "(Embedded Trace)";
1689 type
= "Coresight TPIU";
1690 full
= "(Trace Port Interface Unit)";
1693 type
= "Cortex-A8 ETM";
1694 full
= "(Embedded Trace)";
1697 type
= "Cortex-A8 CTI";
1698 full
= "(Cross Trigger)";
1701 type
= "Cortex-M3 TPIU";
1702 full
= "(Trace Port Interface Unit)";
1705 type
= "Cortex-M3 ETM";
1706 full
= "(Embedded Trace)";
1709 type
= "Cortex-A8 Debug";
1710 full
= "(Debug Unit)";
1713 type
= "-*- unrecognized -*-";
1717 command_print(cmd_ctx
, "\t\tPart is %s %s",
1723 command_print(cmd_ctx
, "\t\tComponent not present");
1725 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1728 } while (romentry
> 0);
1732 command_print(cmd_ctx
, "\tNo ROM table present");
1734 dap_ap_select(swjdp
, apselold
);
1739 DAP_COMMAND_HANDLER(dap_baseaddr_command
)
1741 uint32_t apsel
, apselsave
, baseaddr
;
1744 apselsave
= swjdp
->apsel
;
1747 apsel
= swjdp
->apsel
;
1750 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1751 /* AP address is in bits 31:24 of DP_SELECT */
1753 return ERROR_INVALID_ARGUMENTS
;
1756 return ERROR_COMMAND_SYNTAX_ERROR
;
1759 if (apselsave
!= apsel
)
1760 dap_ap_select(swjdp
, apsel
);
1762 /* NOTE: assumes we're talking to a MEM-AP, which
1763 * has a base address. There are other kinds of AP,
1764 * though they're not common for now. This should
1765 * use the ID register to verify it's a MEM-AP.
1767 dap_ap_read_reg_u32(swjdp
, AP_REG_BASE
, &baseaddr
);
1768 retval
= dap_run(swjdp
);
1769 if (retval
!= ERROR_OK
)
1772 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1774 if (apselsave
!= apsel
)
1775 dap_ap_select(swjdp
, apselsave
);
1780 DAP_COMMAND_HANDLER(dap_memaccess_command
)
1782 uint32_t memaccess_tck
;
1786 memaccess_tck
= swjdp
->memaccess_tck
;
1789 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1792 return ERROR_COMMAND_SYNTAX_ERROR
;
1794 swjdp
->memaccess_tck
= memaccess_tck
;
1796 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1797 swjdp
->memaccess_tck
);
1802 DAP_COMMAND_HANDLER(dap_apsel_command
)
1804 uint32_t apsel
, apid
;
1812 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1813 /* AP address is in bits 31:24 of DP_SELECT */
1815 return ERROR_INVALID_ARGUMENTS
;
1818 return ERROR_COMMAND_SYNTAX_ERROR
;
1821 dap_ap_select(swjdp
, apsel
);
1822 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1823 retval
= dap_run(swjdp
);
1824 if (retval
!= ERROR_OK
)
1827 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1833 DAP_COMMAND_HANDLER(dap_apid_command
)
1835 uint32_t apsel
, apselsave
, apid
;
1838 apselsave
= swjdp
->apsel
;
1841 apsel
= swjdp
->apsel
;
1844 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1845 /* AP address is in bits 31:24 of DP_SELECT */
1847 return ERROR_INVALID_ARGUMENTS
;
1850 return ERROR_COMMAND_SYNTAX_ERROR
;
1853 if (apselsave
!= apsel
)
1854 dap_ap_select(swjdp
, apsel
);
1856 dap_ap_read_reg_u32(swjdp
, AP_REG_IDR
, &apid
);
1857 retval
= dap_run(swjdp
);
1858 if (retval
!= ERROR_OK
)
1861 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1862 if (apselsave
!= apsel
)
1863 dap_ap_select(swjdp
, apselsave
);
1869 * This represents the bits which must be sent out on TMS/SWDIO to
1870 * switch a DAP implemented using an SWJ-DP module into SWD mode.
1871 * These bits are stored (and transmitted) LSB-first.
1873 * See the DAP-Lite specification, section 2.2.5 for information
1874 * about making the debug link select SWD or JTAG. (Similar info
1875 * is in a few other ARM documents.)
1877 static const uint8_t jtag2swd_bitseq
[] = {
1878 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1879 * putting both JTAG and SWD logic into reset state.
1881 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1882 /* Switching sequence enables SWD and disables JTAG
1883 * NOTE: bits in the DP's IDCODE may expose the need for
1884 * an old/deprecated sequence (0xb6 0xed).
1887 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1888 * putting both JTAG and SWD logic into reset state.
1890 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1894 * Put the debug link into SWD mode, if the target supports it.
1895 * The link's initial mode may be either JTAG (for example,
1896 * with SWJ-DP after reset) or SWD.
1898 * @param target Enters SWD mode (if possible).
1900 * Note that targets using the JTAG-DP do not support SWD, and that
1901 * some targets which could otherwise support it may have have been
1902 * configured to disable SWD signaling
1904 * @return ERROR_OK or else a fault code.
1906 int dap_to_swd(struct target
*target
)
1910 LOG_DEBUG("Enter SWD mode");
1912 /* REVISIT it's nasty to need to make calls to a "jtag"
1913 * subsystem if the link isn't in JTAG mode...
1916 retval
= jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq
),
1917 jtag2swd_bitseq
, TAP_INVALID
);
1918 if (retval
== ERROR_OK
)
1919 retval
= jtag_execute_queue();
1921 /* REVISIT set up the DAP's ops vector for SWD mode. */
1927 * This represents the bits which must be sent out on TMS/SWDIO to
1928 * switch a DAP implemented using an SWJ-DP module into JTAG mode.
1929 * These bits are stored (and transmitted) LSB-first.
1931 * These bits are stored (and transmitted) LSB-first.
1933 static const uint8_t swd2jtag_bitseq
[] = {
1934 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1935 * putting both JTAG and SWD logic into reset state.
1937 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1938 /* Switching equence disables SWD and enables JTAG
1939 * NOTE: bits in the DP's IDCODE can expose the need for
1940 * the old/deprecated sequence (0xae 0xde).
1943 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
1944 * putting both JTAG and SWD logic into reset state.
1945 * NOTE: some docs say "at least 5".
1947 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1950 /** Put the debug link into JTAG mode, if the target supports it.
1951 * The link's initial mode may be either SWD or JTAG.
1953 * @param target Enters JTAG mode (if possible).
1955 * Note that targets implemented with SW-DP do not support JTAG, and
1956 * that some targets which could otherwise support it may have been
1957 * configured to disable JTAG signaling
1959 * @return ERROR_OK or else a fault code.
1961 int dap_to_jtag(struct target
*target
)
1965 LOG_DEBUG("Enter JTAG mode");
1967 /* REVISIT it's nasty to need to make calls to a "jtag"
1968 * subsystem if the link isn't in JTAG mode...
1971 retval
= jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq
),
1972 swd2jtag_bitseq
, TAP_RESET
);
1973 if (retval
== ERROR_OK
)
1974 retval
= jtag_execute_queue();
1976 /* REVISIT set up the DAP's ops vector for JTAG mode. */
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