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CORTEX A8: Fix broken CPU identification
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 *
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
56 */
57
58 /*
59 * Relevant specifications from ARM include:
60 *
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
63 *
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
66 */
67
68 #ifdef HAVE_CONFIG_H
69 #include "config.h"
70 #endif
71
72 #include "arm.h"
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
75
76
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
78
79 /*
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 */
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
84 {
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
86 }
87
88 /***************************************************************************
89 * *
90 * DP and MEM-AP register access through APACC and DPACC *
91 * *
92 ***************************************************************************/
93
94 /**
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
98 *
99 * @param dap The DAP
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
102 */
103 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
104 {
105 uint32_t select_apsel = (apsel << 24) & 0xFF000000;
106
107 if (select_apsel != dap->apsel)
108 {
109 dap->apsel = select_apsel;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
112 */
113 dap->ap_bank_value = -1;
114 dap->ap_csw_value = -1;
115 dap->ap_tar_value = -1;
116 }
117 }
118
119 /**
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
122 *
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
127 *
128 * @todo Rename to reflect it being specifically a MEM-AP function.
129 *
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
135 *
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
137 */
138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
139 {
140 int retval;
141
142 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
143 if (csw != dap->ap_csw_value)
144 {
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
147 if (retval != ERROR_OK)
148 return retval;
149 dap->ap_csw_value = csw;
150 }
151 if (tar != dap->ap_tar_value)
152 {
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
155 if (retval != ERROR_OK)
156 return retval;
157 dap->ap_tar_value = tar;
158 }
159 /* Disable TAR cache when autoincrementing */
160 if (csw & CSW_ADDRINC_MASK)
161 dap->ap_tar_value = -1;
162 return ERROR_OK;
163 }
164
165 /**
166 * Asynchronous (queued) read of a word from memory or a system register.
167 *
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
173 *
174 * @return ERROR_OK for success. Otherwise a fault code.
175 */
176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
177 uint32_t *value)
178 {
179 int retval;
180
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
183 */
184 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
185 address & 0xFFFFFFF0);
186 if (retval != ERROR_OK)
187 return retval;
188
189 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
190 }
191
192 /**
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
195 *
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
200 *
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
203 */
204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
205 uint32_t *value)
206 {
207 int retval;
208
209 retval = mem_ap_read_u32(dap, address, value);
210 if (retval != ERROR_OK)
211 return retval;
212
213 return dap_run(dap);
214 }
215
216 /**
217 * Asynchronous (queued) write of a word to memory or a system register.
218 *
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
224 *
225 * @return ERROR_OK for success. Otherwise a fault code.
226 */
227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
228 uint32_t value)
229 {
230 int retval;
231
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
234 */
235 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
236 address & 0xFFFFFFF0);
237 if (retval != ERROR_OK)
238 return retval;
239
240 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
241 value);
242 }
243
244 /**
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
247 *
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
252 *
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
254 */
255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
256 uint32_t value)
257 {
258 int retval = mem_ap_write_u32(dap, address, value);
259
260 if (retval != ERROR_OK)
261 return retval;
262
263 return dap_run(dap);
264 }
265
266 /*****************************************************************************
267 * *
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
269 * *
270 * Write a buffer in target order (little endian) *
271 * *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
274 {
275 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
276 uint32_t adr = address;
277 uint8_t* pBuffer = buffer;
278
279 count >>= 2;
280 wcount = count;
281
282 /* if we have an unaligned access - reorder data */
283 if (adr & 0x3u)
284 {
285 for (writecount = 0; writecount < count; writecount++)
286 {
287 int i;
288 uint32_t outvalue;
289 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
290
291 for (i = 0; i < 4; i++)
292 {
293 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
294 outvalue >>= 8;
295 adr++;
296 }
297 pBuffer += sizeof(uint32_t);
298 }
299 }
300
301 while (wcount > 0)
302 {
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
305 if (wcount < blocksize)
306 blocksize = wcount;
307
308 /* handle unaligned data at 4k boundary */
309 if (blocksize == 0)
310 blocksize = 1;
311
312 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
313 if (retval != ERROR_OK)
314 return retval;
315
316 for (writecount = 0; writecount < blocksize; writecount++)
317 {
318 retval = dap_queue_ap_write(dap, AP_REG_DRW,
319 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
320 if (retval != ERROR_OK)
321 break;
322 }
323
324 if ((retval = dap_run(dap)) == ERROR_OK)
325 {
326 wcount = wcount - blocksize;
327 address = address + 4 * blocksize;
328 buffer = buffer + 4 * blocksize;
329 }
330 else
331 {
332 errorcount++;
333 }
334
335 if (errorcount > 1)
336 {
337 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
338 return retval;
339 }
340 }
341
342 return retval;
343 }
344
345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
346 uint8_t *buffer, int count, uint32_t address)
347 {
348 int retval = ERROR_OK;
349 int wcount, blocksize, writecount, i;
350
351 wcount = count >> 1;
352
353 while (wcount > 0)
354 {
355 int nbytes;
356
357 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
358 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
359
360 if (wcount < blocksize)
361 blocksize = wcount;
362
363 /* handle unaligned data at 4k boundary */
364 if (blocksize == 0)
365 blocksize = 1;
366
367 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
368 if (retval != ERROR_OK)
369 return retval;
370 writecount = blocksize;
371
372 do
373 {
374 nbytes = MIN((writecount << 1), 4);
375
376 if (nbytes < 4)
377 {
378 retval = mem_ap_write_buf_u16(dap, buffer,
379 nbytes, address);
380 if (retval != ERROR_OK)
381 {
382 LOG_WARNING("Block write error address "
383 "0x%" PRIx32 ", count 0x%x",
384 address, count);
385 return retval;
386 }
387
388 address += nbytes >> 1;
389 }
390 else
391 {
392 uint32_t outvalue;
393 memcpy(&outvalue, buffer, sizeof(uint32_t));
394
395 for (i = 0; i < nbytes; i++)
396 {
397 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
398 outvalue >>= 8;
399 address++;
400 }
401
402 memcpy(&outvalue, buffer, sizeof(uint32_t));
403 retval = dap_queue_ap_write(dap,
404 AP_REG_DRW, outvalue);
405 if (retval != ERROR_OK)
406 break;
407
408 if ((retval = dap_run(dap)) != ERROR_OK)
409 {
410 LOG_WARNING("Block write error address "
411 "0x%" PRIx32 ", count 0x%x",
412 address, count);
413 return retval;
414 }
415 }
416
417 buffer += nbytes >> 1;
418 writecount -= nbytes >> 1;
419
420 } while (writecount);
421 wcount -= blocksize;
422 }
423
424 return retval;
425 }
426
427 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
428 {
429 int retval = ERROR_OK;
430
431 if (count >= 4)
432 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
433
434 while (count > 0)
435 {
436 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
437 if (retval != ERROR_OK)
438 return retval;
439 uint16_t svalue;
440 memcpy(&svalue, buffer, sizeof(uint16_t));
441 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
442 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
443 if (retval != ERROR_OK)
444 break;
445
446 retval = dap_run(dap);
447 if (retval != ERROR_OK)
448 break;
449
450 count -= 2;
451 address += 2;
452 buffer += 2;
453 }
454
455 return retval;
456 }
457
458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
459 uint8_t *buffer, int count, uint32_t address)
460 {
461 int retval = ERROR_OK;
462 int wcount, blocksize, writecount, i;
463
464 wcount = count;
465
466 while (wcount > 0)
467 {
468 int nbytes;
469
470 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
471 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
472
473 if (wcount < blocksize)
474 blocksize = wcount;
475
476 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
477 if (retval != ERROR_OK)
478 return retval;
479 writecount = blocksize;
480
481 do
482 {
483 nbytes = MIN(writecount, 4);
484
485 if (nbytes < 4)
486 {
487 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
488 if (retval != ERROR_OK)
489 {
490 LOG_WARNING("Block write error address "
491 "0x%" PRIx32 ", count 0x%x",
492 address, count);
493 return retval;
494 }
495
496 address += nbytes;
497 }
498 else
499 {
500 uint32_t outvalue;
501 memcpy(&outvalue, buffer, sizeof(uint32_t));
502
503 for (i = 0; i < nbytes; i++)
504 {
505 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
506 outvalue >>= 8;
507 address++;
508 }
509
510 memcpy(&outvalue, buffer, sizeof(uint32_t));
511 retval = dap_queue_ap_write(dap,
512 AP_REG_DRW, outvalue);
513 if (retval != ERROR_OK)
514 break;
515
516 if ((retval = dap_run(dap)) != ERROR_OK)
517 {
518 LOG_WARNING("Block write error address "
519 "0x%" PRIx32 ", count 0x%x",
520 address, count);
521 return retval;
522 }
523 }
524
525 buffer += nbytes;
526 writecount -= nbytes;
527
528 } while (writecount);
529 wcount -= blocksize;
530 }
531
532 return retval;
533 }
534
535 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
536 {
537 int retval = ERROR_OK;
538
539 if (count >= 4)
540 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
541
542 while (count > 0)
543 {
544 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
545 if (retval != ERROR_OK)
546 return retval;
547 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
548 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
549 if (retval != ERROR_OK)
550 break;
551
552 retval = dap_run(dap);
553 if (retval != ERROR_OK)
554 break;
555
556 count--;
557 address++;
558 buffer++;
559 }
560
561 return retval;
562 }
563
564 /* FIXME don't import ... this is a temporary workaround for the
565 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
566 */
567 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
568 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
569 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
570
571 /**
572 * Synchronously read a block of 32-bit words into a buffer
573 * @param dap The DAP connected to the MEM-AP.
574 * @param buffer where the words will be stored (in host byte order).
575 * @param count How many words to read.
576 * @param address Memory address from which to read words; all the
577 * words must be readable by the currently selected MEM-AP.
578 */
579 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
580 int count, uint32_t address)
581 {
582 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
583 uint32_t adr = address;
584 uint8_t* pBuffer = buffer;
585
586 count >>= 2;
587 wcount = count;
588
589 while (wcount > 0)
590 {
591 /* Adjust to read blocks within boundaries aligned to the
592 * TAR autoincrement size (at least 2^10). Autoincrement
593 * mode avoids an extra per-word roundtrip to update TAR.
594 */
595 blocksize = max_tar_block_size(dap->tar_autoincr_block,
596 address);
597 if (wcount < blocksize)
598 blocksize = wcount;
599
600 /* handle unaligned data at 4k boundary */
601 if (blocksize == 0)
602 blocksize = 1;
603
604 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
605 address);
606 if (retval != ERROR_OK)
607 return retval;
608
609 /* FIXME remove these three calls to adi_jtag_dp_scan(),
610 * so this routine becomes transport-neutral. Be careful
611 * not to cause performance problems with JTAG; would it
612 * suffice to loop over dap_queue_ap_read(), or would that
613 * be slower when JTAG is the chosen transport?
614 */
615
616 /* Scan out first read */
617 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
618 DPAP_READ, 0, NULL, NULL);
619 if (retval != ERROR_OK)
620 return retval;
621 for (readcount = 0; readcount < blocksize - 1; readcount++)
622 {
623 /* Scan out next read; scan in posted value for the
624 * previous one. Assumes read is acked "OK/FAULT",
625 * and CTRL_STAT says that meant "OK".
626 */
627 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
628 DPAP_READ, 0, buffer + 4 * readcount,
629 &dap->ack);
630 if (retval != ERROR_OK)
631 return retval;
632 }
633
634 /* Scan in last posted value; RDBUFF has no other effect,
635 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
636 */
637 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
638 DPAP_READ, 0, buffer + 4 * readcount,
639 &dap->ack);
640 if (retval != ERROR_OK)
641 return retval;
642
643 retval = dap_run(dap);
644 if (retval != ERROR_OK)
645 {
646 errorcount++;
647 if (errorcount <= 1)
648 {
649 /* try again */
650 continue;
651 }
652 LOG_WARNING("Block read error address 0x%" PRIx32, address);
653 return retval;
654 }
655 wcount = wcount - blocksize;
656 address += 4 * blocksize;
657 buffer += 4 * blocksize;
658 }
659
660 /* if we have an unaligned access - reorder data */
661 if (adr & 0x3u)
662 {
663 for (readcount = 0; readcount < count; readcount++)
664 {
665 int i;
666 uint32_t data;
667 memcpy(&data, pBuffer, sizeof(uint32_t));
668
669 for (i = 0; i < 4; i++)
670 {
671 *((uint8_t*)pBuffer) =
672 (data >> 8 * (adr & 0x3));
673 pBuffer++;
674 adr++;
675 }
676 }
677 }
678
679 return retval;
680 }
681
682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
683 uint8_t *buffer, int count, uint32_t address)
684 {
685 uint32_t invalue;
686 int retval = ERROR_OK;
687 int wcount, blocksize, readcount, i;
688
689 wcount = count >> 1;
690
691 while (wcount > 0)
692 {
693 int nbytes;
694
695 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
696 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
697 if (wcount < blocksize)
698 blocksize = wcount;
699
700 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
701 if (retval != ERROR_OK)
702 return retval;
703
704 /* handle unaligned data at 4k boundary */
705 if (blocksize == 0)
706 blocksize = 1;
707 readcount = blocksize;
708
709 do
710 {
711 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
712 if (retval != ERROR_OK)
713 return retval;
714 if ((retval = dap_run(dap)) != ERROR_OK)
715 {
716 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
717 return retval;
718 }
719
720 nbytes = MIN((readcount << 1), 4);
721
722 for (i = 0; i < nbytes; i++)
723 {
724 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
725 buffer++;
726 address++;
727 }
728
729 readcount -= (nbytes >> 1);
730 } while (readcount);
731 wcount -= blocksize;
732 }
733
734 return retval;
735 }
736
737 /**
738 * Synchronously read a block of 16-bit halfwords into a buffer
739 * @param dap The DAP connected to the MEM-AP.
740 * @param buffer where the halfwords will be stored (in host byte order).
741 * @param count How many halfwords to read.
742 * @param address Memory address from which to read words; all the
743 * words must be readable by the currently selected MEM-AP.
744 */
745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
746 int count, uint32_t address)
747 {
748 uint32_t invalue, i;
749 int retval = ERROR_OK;
750
751 if (count >= 4)
752 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
753
754 while (count > 0)
755 {
756 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
757 if (retval != ERROR_OK)
758 return retval;
759 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
760 if (retval != ERROR_OK)
761 break;
762
763 retval = dap_run(dap);
764 if (retval != ERROR_OK)
765 break;
766
767 if (address & 0x1)
768 {
769 for (i = 0; i < 2; i++)
770 {
771 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
772 buffer++;
773 address++;
774 }
775 }
776 else
777 {
778 uint16_t svalue = (invalue >> 8 * (address & 0x3));
779 memcpy(buffer, &svalue, sizeof(uint16_t));
780 address += 2;
781 buffer += 2;
782 }
783 count -= 2;
784 }
785
786 return retval;
787 }
788
789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
790 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
791 *
792 * The solution is to arrange for a large out/in scan in this loop and
793 * and convert data afterwards.
794 */
795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
796 uint8_t *buffer, int count, uint32_t address)
797 {
798 uint32_t invalue;
799 int retval = ERROR_OK;
800 int wcount, blocksize, readcount, i;
801
802 wcount = count;
803
804 while (wcount > 0)
805 {
806 int nbytes;
807
808 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
809 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
810
811 if (wcount < blocksize)
812 blocksize = wcount;
813
814 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
815 if (retval != ERROR_OK)
816 return retval;
817 readcount = blocksize;
818
819 do
820 {
821 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
822 if (retval != ERROR_OK)
823 return retval;
824 if ((retval = dap_run(dap)) != ERROR_OK)
825 {
826 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
827 return retval;
828 }
829
830 nbytes = MIN(readcount, 4);
831
832 for (i = 0; i < nbytes; i++)
833 {
834 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
835 buffer++;
836 address++;
837 }
838
839 readcount -= nbytes;
840 } while (readcount);
841 wcount -= blocksize;
842 }
843
844 return retval;
845 }
846
847 /**
848 * Synchronously read a block of bytes into a buffer
849 * @param dap The DAP connected to the MEM-AP.
850 * @param buffer where the bytes will be stored.
851 * @param count How many bytes to read.
852 * @param address Memory address from which to read data; all the
853 * data must be readable by the currently selected MEM-AP.
854 */
855 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
856 int count, uint32_t address)
857 {
858 uint32_t invalue;
859 int retval = ERROR_OK;
860
861 if (count >= 4)
862 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
863
864 while (count > 0)
865 {
866 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
867 if (retval != ERROR_OK)
868 return retval;
869 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
870 if (retval != ERROR_OK)
871 return retval;
872 retval = dap_run(dap);
873 if (retval != ERROR_OK)
874 break;
875
876 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
877 count--;
878 address++;
879 buffer++;
880 }
881
882 return retval;
883 }
884
885 /*--------------------------------------------------------------------------*/
886
887
888 /* FIXME don't import ... just initialize as
889 * part of DAP transport setup
890 */
891 extern const struct dap_ops jtag_dp_ops;
892
893 /*--------------------------------------------------------------------------*/
894
895 /**
896 * Initialize a DAP. This sets up the power domains, prepares the DP
897 * for further use, and arranges to use AP #0 for all AP operations
898 * until dap_ap-select() changes that policy.
899 *
900 * @param dap The DAP being initialized.
901 *
902 * @todo Rename this. We also need an initialization scheme which account
903 * for SWD transports not just JTAG; that will need to address differences
904 * in layering. (JTAG is useful without any debug target; but not SWD.)
905 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
906 */
907 int ahbap_debugport_init(struct adiv5_dap *dap)
908 {
909 uint32_t dummy;
910 uint32_t ctrlstat;
911 int cnt = 0;
912 int retval;
913
914 LOG_DEBUG(" ");
915
916 /* JTAG-DP or SWJ-DP, in JTAG mode
917 * ... for SWD mode this is patched as part
918 * of link switchover
919 */
920 if (!dap->ops)
921 dap->ops = &jtag_dp_ops;
922
923 /* Default MEM-AP setup.
924 *
925 * REVISIT AP #0 may be an inappropriate default for this.
926 * Should we probe, or take a hint from the caller?
927 * Presumably we can ignore the possibility of multiple APs.
928 */
929 dap->apsel = !0;
930 dap_ap_select(dap, 0);
931
932 /* DP initialization */
933
934 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
935 if (retval != ERROR_OK)
936 return retval;
937
938 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
939 if (retval != ERROR_OK)
940 return retval;
941
942 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
943 if (retval != ERROR_OK)
944 return retval;
945
946 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
947 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
948 if (retval != ERROR_OK)
949 return retval;
950
951 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
952 if (retval != ERROR_OK)
953 return retval;
954 if ((retval = dap_run(dap)) != ERROR_OK)
955 return retval;
956
957 /* Check that we have debug power domains activated */
958 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
959 {
960 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
961 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
962 if (retval != ERROR_OK)
963 return retval;
964 if ((retval = dap_run(dap)) != ERROR_OK)
965 return retval;
966 alive_sleep(10);
967 }
968
969 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
970 {
971 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
972 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
973 if (retval != ERROR_OK)
974 return retval;
975 if ((retval = dap_run(dap)) != ERROR_OK)
976 return retval;
977 alive_sleep(10);
978 }
979
980 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
981 if (retval != ERROR_OK)
982 return retval;
983 /* With debug power on we can activate OVERRUN checking */
984 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
985 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
986 if (retval != ERROR_OK)
987 return retval;
988 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
989 if (retval != ERROR_OK)
990 return retval;
991
992 return ERROR_OK;
993 }
994
995 /* CID interpretation -- see ARM IHI 0029B section 3
996 * and ARM IHI 0031A table 13-3.
997 */
998 static const char *class_description[16] ={
999 "Reserved", "ROM table", "Reserved", "Reserved",
1000 "Reserved", "Reserved", "Reserved", "Reserved",
1001 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1002 "Reserved", "OptimoDE DESS",
1003 "Generic IP component", "PrimeCell or System component"
1004 };
1005
1006 static bool
1007 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1008 {
1009 return cid3 == 0xb1 && cid2 == 0x05
1010 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1011 }
1012
1013 struct broken_cpu {
1014 uint32_t dbgbase;
1015 uint32_t apid;
1016 uint32_t idcode;
1017 uint32_t correct_dbgbase;
1018 char *model;
1019 } broken_cpus[] = {
1020 { 0x80000000, 0x04770002, 0x1ba00477, 0x60000000, "imx51" },
1021 };
1022
1023 int dap_get_debugbase(struct adiv5_dap *dap, int apsel,
1024 uint32_t *out_dbgbase, uint32_t *out_apid)
1025 {
1026 uint32_t apselold;
1027 int retval;
1028 unsigned int i;
1029 uint32_t dbgbase, apid, idcode;
1030
1031 /* AP address is in bits 31:24 of DP_SELECT */
1032 if (apsel >= 256)
1033 return ERROR_INVALID_ARGUMENTS;
1034
1035 apselold = dap->apsel;
1036 dap_ap_select(dap, apsel);
1037
1038 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1039 if (retval != ERROR_OK)
1040 return retval;
1041 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1042 if (retval != ERROR_OK)
1043 return retval;
1044 retval = dap_run(dap);
1045 if (retval != ERROR_OK)
1046 return retval;
1047
1048 /* Excavate the device ID code */
1049 struct jtag_tap *tap = dap->jtag_info->tap;
1050 while (tap != NULL) {
1051 if (tap->hasidcode) {
1052 idcode = tap->idcode;
1053 break;
1054 }
1055 tap = tap->next_tap;
1056 }
1057 if (tap == NULL || !tap->hasidcode)
1058 return ERROR_OK;
1059
1060 /* Some CPUs are messed up, so fixup if needed. */
1061 for (i = 0; i < sizeof(broken_cpus)/sizeof(struct broken_cpu); i++)
1062 if (broken_cpus[i].dbgbase == dbgbase &&
1063 broken_cpus[i].apid == apid &&
1064 broken_cpus[i].idcode == idcode) {
1065 LOG_WARNING("Found broken CPU (%s), trying to fixup "
1066 "ROM Table location from 0x%08x to 0x%08x",
1067 broken_cpus[i].model, dbgbase,
1068 broken_cpus[i].correct_dbgbase);
1069 dbgbase = broken_cpus[i].correct_dbgbase;
1070 break;
1071 }
1072
1073 dap_ap_select(dap, apselold);
1074
1075 /* The asignment happens only here to prevent modification of these
1076 * values before they are certain. */
1077 *out_dbgbase = dbgbase;
1078 *out_apid = apid;
1079
1080 return ERROR_OK;
1081 }
1082
1083 int dap_lookup_cs_component(struct adiv5_dap *dap, int apsel,
1084 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1085 {
1086 uint32_t apselold;
1087 uint32_t romentry, entry_offset = 0, component_base, devtype;
1088 int retval = ERROR_FAIL;
1089
1090 if (apsel >= 256)
1091 return ERROR_INVALID_ARGUMENTS;
1092
1093 apselold = dap->apsel;
1094 dap_ap_select(dap, apsel);
1095
1096 do
1097 {
1098 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1099 entry_offset, &romentry);
1100 if (retval != ERROR_OK)
1101 return retval;
1102
1103 component_base = (dbgbase & 0xFFFFF000)
1104 + (romentry & 0xFFFFF000);
1105
1106 if (romentry & 0x1) {
1107 retval = mem_ap_read_atomic_u32(dap,
1108 (component_base & 0xfffff000) | 0xfcc,
1109 &devtype);
1110 if ((devtype & 0xff) == type) {
1111 *addr = component_base;
1112 retval = ERROR_OK;
1113 break;
1114 }
1115 }
1116 entry_offset += 4;
1117 } while (romentry > 0);
1118
1119 dap_ap_select(dap, apselold);
1120
1121 return retval;
1122 }
1123
1124 static int dap_info_command(struct command_context *cmd_ctx,
1125 struct adiv5_dap *dap, int apsel)
1126 {
1127 int retval;
1128 uint32_t dbgbase, apid;
1129 int romtable_present = 0;
1130 uint8_t mem_ap;
1131 uint32_t apselold;
1132
1133 retval = dap_get_debugbase(dap, apsel, &dbgbase, &apid);
1134 if (retval != ERROR_OK)
1135 return retval;
1136
1137 apselold = dap->apsel;
1138 dap_ap_select(dap, apsel);
1139
1140 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1141 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1142 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1143 if (apid)
1144 {
1145 switch (apid&0x0F)
1146 {
1147 case 0:
1148 command_print(cmd_ctx, "\tType is JTAG-AP");
1149 break;
1150 case 1:
1151 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1152 break;
1153 case 2:
1154 command_print(cmd_ctx, "\tType is MEM-AP APB");
1155 break;
1156 default:
1157 command_print(cmd_ctx, "\tUnknown AP type");
1158 break;
1159 }
1160
1161 /* NOTE: a MEM-AP may have a single CoreSight component that's
1162 * not a ROM table ... or have no such components at all.
1163 */
1164 if (mem_ap)
1165 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1166 dbgbase);
1167 }
1168 else
1169 {
1170 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1171 }
1172
1173 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1174 if (romtable_present)
1175 {
1176 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1177 uint16_t entry_offset;
1178
1179 /* bit 16 of apid indicates a memory access port */
1180 if (dbgbase & 0x02)
1181 command_print(cmd_ctx, "\tValid ROM table present");
1182 else
1183 command_print(cmd_ctx, "\tROM table in legacy format");
1184
1185 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1186 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1187 if (retval != ERROR_OK)
1188 return retval;
1189 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1190 if (retval != ERROR_OK)
1191 return retval;
1192 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1193 if (retval != ERROR_OK)
1194 return retval;
1195 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1196 if (retval != ERROR_OK)
1197 return retval;
1198 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1199 if (retval != ERROR_OK)
1200 return retval;
1201 retval = dap_run(dap);
1202 if (retval != ERROR_OK)
1203 return retval;
1204
1205 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1206 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1207 ", CID2 0x%2.2x"
1208 ", CID1 0x%2.2x"
1209 ", CID0 0x%2.2x",
1210 (unsigned) cid3, (unsigned)cid2,
1211 (unsigned) cid1, (unsigned) cid0);
1212 if (memtype & 0x01)
1213 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1214 else
1215 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1216 "Dedicated debug bus.");
1217
1218 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1219 entry_offset = 0;
1220 do
1221 {
1222 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1223 if (retval != ERROR_OK)
1224 return retval;
1225 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1226 if (romentry&0x01)
1227 {
1228 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1229 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1230 uint32_t component_base;
1231 unsigned part_num;
1232 char *type, *full;
1233
1234 component_base = (dbgbase & 0xFFFFF000)
1235 + (romentry & 0xFFFFF000);
1236
1237 /* IDs are in last 4K section */
1238
1239
1240 retval = mem_ap_read_atomic_u32(dap,
1241 component_base + 0xFE0, &c_pid0);
1242 if (retval != ERROR_OK)
1243 return retval;
1244 c_pid0 &= 0xff;
1245 retval = mem_ap_read_atomic_u32(dap,
1246 component_base + 0xFE4, &c_pid1);
1247 if (retval != ERROR_OK)
1248 return retval;
1249 c_pid1 &= 0xff;
1250 retval = mem_ap_read_atomic_u32(dap,
1251 component_base + 0xFE8, &c_pid2);
1252 if (retval != ERROR_OK)
1253 return retval;
1254 c_pid2 &= 0xff;
1255 retval = mem_ap_read_atomic_u32(dap,
1256 component_base + 0xFEC, &c_pid3);
1257 if (retval != ERROR_OK)
1258 return retval;
1259 c_pid3 &= 0xff;
1260 retval = mem_ap_read_atomic_u32(dap,
1261 component_base + 0xFD0, &c_pid4);
1262 if (retval != ERROR_OK)
1263 return retval;
1264 c_pid4 &= 0xff;
1265
1266 retval = mem_ap_read_atomic_u32(dap,
1267 component_base + 0xFF0, &c_cid0);
1268 if (retval != ERROR_OK)
1269 return retval;
1270 c_cid0 &= 0xff;
1271 retval = mem_ap_read_atomic_u32(dap,
1272 component_base + 0xFF4, &c_cid1);
1273 if (retval != ERROR_OK)
1274 return retval;
1275 c_cid1 &= 0xff;
1276 retval = mem_ap_read_atomic_u32(dap,
1277 component_base + 0xFF8, &c_cid2);
1278 if (retval != ERROR_OK)
1279 return retval;
1280 c_cid2 &= 0xff;
1281 retval = mem_ap_read_atomic_u32(dap,
1282 component_base + 0xFFC, &c_cid3);
1283 if (retval != ERROR_OK)
1284 return retval;
1285 c_cid3 &= 0xff;
1286
1287
1288 command_print(cmd_ctx,
1289 "\t\tComponent base address 0x%" PRIx32
1290 ", start address 0x%" PRIx32,
1291 component_base,
1292 /* component may take multiple 4K pages */
1293 component_base - 0x1000*(c_pid4 >> 4));
1294 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1295 (int) (c_cid1 >> 4) & 0xf,
1296 /* See ARM IHI 0029B Table 3-3 */
1297 class_description[(c_cid1 >> 4) & 0xf]);
1298
1299 /* CoreSight component? */
1300 if (((c_cid1 >> 4) & 0x0f) == 9) {
1301 uint32_t devtype;
1302 unsigned minor;
1303 char *major = "Reserved", *subtype = "Reserved";
1304
1305 retval = mem_ap_read_atomic_u32(dap,
1306 (component_base & 0xfffff000) | 0xfcc,
1307 &devtype);
1308 if (retval != ERROR_OK)
1309 return retval;
1310 minor = (devtype >> 4) & 0x0f;
1311 switch (devtype & 0x0f) {
1312 case 0:
1313 major = "Miscellaneous";
1314 switch (minor) {
1315 case 0:
1316 subtype = "other";
1317 break;
1318 case 4:
1319 subtype = "Validation component";
1320 break;
1321 }
1322 break;
1323 case 1:
1324 major = "Trace Sink";
1325 switch (minor) {
1326 case 0:
1327 subtype = "other";
1328 break;
1329 case 1:
1330 subtype = "Port";
1331 break;
1332 case 2:
1333 subtype = "Buffer";
1334 break;
1335 }
1336 break;
1337 case 2:
1338 major = "Trace Link";
1339 switch (minor) {
1340 case 0:
1341 subtype = "other";
1342 break;
1343 case 1:
1344 subtype = "Funnel, router";
1345 break;
1346 case 2:
1347 subtype = "Filter";
1348 break;
1349 case 3:
1350 subtype = "FIFO, buffer";
1351 break;
1352 }
1353 break;
1354 case 3:
1355 major = "Trace Source";
1356 switch (minor) {
1357 case 0:
1358 subtype = "other";
1359 break;
1360 case 1:
1361 subtype = "Processor";
1362 break;
1363 case 2:
1364 subtype = "DSP";
1365 break;
1366 case 3:
1367 subtype = "Engine/Coprocessor";
1368 break;
1369 case 4:
1370 subtype = "Bus";
1371 break;
1372 }
1373 break;
1374 case 4:
1375 major = "Debug Control";
1376 switch (minor) {
1377 case 0:
1378 subtype = "other";
1379 break;
1380 case 1:
1381 subtype = "Trigger Matrix";
1382 break;
1383 case 2:
1384 subtype = "Debug Auth";
1385 break;
1386 }
1387 break;
1388 case 5:
1389 major = "Debug Logic";
1390 switch (minor) {
1391 case 0:
1392 subtype = "other";
1393 break;
1394 case 1:
1395 subtype = "Processor";
1396 break;
1397 case 2:
1398 subtype = "DSP";
1399 break;
1400 case 3:
1401 subtype = "Engine/Coprocessor";
1402 break;
1403 }
1404 break;
1405 }
1406 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1407 (unsigned) (devtype & 0xff),
1408 major, subtype);
1409 /* REVISIT also show 0xfc8 DevId */
1410 }
1411
1412 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1413 command_print(cmd_ctx,
1414 "\t\tCID3 0%2.2x"
1415 ", CID2 0%2.2x"
1416 ", CID1 0%2.2x"
1417 ", CID0 0%2.2x",
1418 (int) c_cid3,
1419 (int) c_cid2,
1420 (int)c_cid1,
1421 (int)c_cid0);
1422 command_print(cmd_ctx,
1423 "\t\tPeripheral ID[4..0] = hex "
1424 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1425 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1426 (int) c_pid1, (int) c_pid0);
1427
1428 /* Part number interpretations are from Cortex
1429 * core specs, the CoreSight components TRM
1430 * (ARM DDI 0314H), and ETM specs; also from
1431 * chip observation (e.g. TI SDTI).
1432 */
1433 part_num = (c_pid0 & 0xff);
1434 part_num |= (c_pid1 & 0x0f) << 8;
1435 switch (part_num) {
1436 case 0x000:
1437 type = "Cortex-M3 NVIC";
1438 full = "(Interrupt Controller)";
1439 break;
1440 case 0x001:
1441 type = "Cortex-M3 ITM";
1442 full = "(Instrumentation Trace Module)";
1443 break;
1444 case 0x002:
1445 type = "Cortex-M3 DWT";
1446 full = "(Data Watchpoint and Trace)";
1447 break;
1448 case 0x003:
1449 type = "Cortex-M3 FBP";
1450 full = "(Flash Patch and Breakpoint)";
1451 break;
1452 case 0x00d:
1453 type = "CoreSight ETM11";
1454 full = "(Embedded Trace)";
1455 break;
1456 // case 0x113: what?
1457 case 0x120: /* from OMAP3 memmap */
1458 type = "TI SDTI";
1459 full = "(System Debug Trace Interface)";
1460 break;
1461 case 0x343: /* from OMAP3 memmap */
1462 type = "TI DAPCTL";
1463 full = "";
1464 break;
1465 case 0x906:
1466 type = "Coresight CTI";
1467 full = "(Cross Trigger)";
1468 break;
1469 case 0x907:
1470 type = "Coresight ETB";
1471 full = "(Trace Buffer)";
1472 break;
1473 case 0x908:
1474 type = "Coresight CSTF";
1475 full = "(Trace Funnel)";
1476 break;
1477 case 0x910:
1478 type = "CoreSight ETM9";
1479 full = "(Embedded Trace)";
1480 break;
1481 case 0x912:
1482 type = "Coresight TPIU";
1483 full = "(Trace Port Interface Unit)";
1484 break;
1485 case 0x921:
1486 type = "Cortex-A8 ETM";
1487 full = "(Embedded Trace)";
1488 break;
1489 case 0x922:
1490 type = "Cortex-A8 CTI";
1491 full = "(Cross Trigger)";
1492 break;
1493 case 0x923:
1494 type = "Cortex-M3 TPIU";
1495 full = "(Trace Port Interface Unit)";
1496 break;
1497 case 0x924:
1498 type = "Cortex-M3 ETM";
1499 full = "(Embedded Trace)";
1500 break;
1501 case 0xc08:
1502 type = "Cortex-A8 Debug";
1503 full = "(Debug Unit)";
1504 break;
1505 default:
1506 type = "-*- unrecognized -*-";
1507 full = "";
1508 break;
1509 }
1510 command_print(cmd_ctx, "\t\tPart is %s %s",
1511 type, full);
1512 }
1513 else
1514 {
1515 if (romentry)
1516 command_print(cmd_ctx, "\t\tComponent not present");
1517 else
1518 command_print(cmd_ctx, "\t\tEnd of ROM table");
1519 }
1520 entry_offset += 4;
1521 } while (romentry > 0);
1522 }
1523 else
1524 {
1525 command_print(cmd_ctx, "\tNo ROM table present");
1526 }
1527 dap_ap_select(dap, apselold);
1528
1529 return ERROR_OK;
1530 }
1531
1532 COMMAND_HANDLER(handle_dap_info_command)
1533 {
1534 struct target *target = get_current_target(CMD_CTX);
1535 struct arm *arm = target_to_arm(target);
1536 struct adiv5_dap *dap = arm->dap;
1537 uint32_t apsel;
1538
1539 switch (CMD_ARGC) {
1540 case 0:
1541 apsel = dap->apsel;
1542 break;
1543 case 1:
1544 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1545 break;
1546 default:
1547 return ERROR_COMMAND_SYNTAX_ERROR;
1548 }
1549
1550 return dap_info_command(CMD_CTX, dap, apsel);
1551 }
1552
1553 COMMAND_HANDLER(dap_baseaddr_command)
1554 {
1555 struct target *target = get_current_target(CMD_CTX);
1556 struct arm *arm = target_to_arm(target);
1557 struct adiv5_dap *dap = arm->dap;
1558
1559 uint32_t apsel, apselsave, baseaddr;
1560 int retval;
1561
1562 apselsave = dap->apsel;
1563 switch (CMD_ARGC) {
1564 case 0:
1565 apsel = dap->apsel;
1566 break;
1567 case 1:
1568 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1569 /* AP address is in bits 31:24 of DP_SELECT */
1570 if (apsel >= 256)
1571 return ERROR_INVALID_ARGUMENTS;
1572 break;
1573 default:
1574 return ERROR_COMMAND_SYNTAX_ERROR;
1575 }
1576
1577 if (apselsave != apsel)
1578 dap_ap_select(dap, apsel);
1579
1580 /* NOTE: assumes we're talking to a MEM-AP, which
1581 * has a base address. There are other kinds of AP,
1582 * though they're not common for now. This should
1583 * use the ID register to verify it's a MEM-AP.
1584 */
1585 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1586 if (retval != ERROR_OK)
1587 return retval;
1588 retval = dap_run(dap);
1589 if (retval != ERROR_OK)
1590 return retval;
1591
1592 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1593
1594 if (apselsave != apsel)
1595 dap_ap_select(dap, apselsave);
1596
1597 return retval;
1598 }
1599
1600 COMMAND_HANDLER(dap_memaccess_command)
1601 {
1602 struct target *target = get_current_target(CMD_CTX);
1603 struct arm *arm = target_to_arm(target);
1604 struct adiv5_dap *dap = arm->dap;
1605
1606 uint32_t memaccess_tck;
1607
1608 switch (CMD_ARGC) {
1609 case 0:
1610 memaccess_tck = dap->memaccess_tck;
1611 break;
1612 case 1:
1613 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1614 break;
1615 default:
1616 return ERROR_COMMAND_SYNTAX_ERROR;
1617 }
1618 dap->memaccess_tck = memaccess_tck;
1619
1620 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1621 dap->memaccess_tck);
1622
1623 return ERROR_OK;
1624 }
1625
1626 COMMAND_HANDLER(dap_apsel_command)
1627 {
1628 struct target *target = get_current_target(CMD_CTX);
1629 struct arm *arm = target_to_arm(target);
1630 struct adiv5_dap *dap = arm->dap;
1631
1632 uint32_t apsel, apid;
1633 int retval;
1634
1635 switch (CMD_ARGC) {
1636 case 0:
1637 apsel = 0;
1638 break;
1639 case 1:
1640 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1641 /* AP address is in bits 31:24 of DP_SELECT */
1642 if (apsel >= 256)
1643 return ERROR_INVALID_ARGUMENTS;
1644 break;
1645 default:
1646 return ERROR_COMMAND_SYNTAX_ERROR;
1647 }
1648
1649 dap_ap_select(dap, apsel);
1650 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1651 if (retval != ERROR_OK)
1652 return retval;
1653 retval = dap_run(dap);
1654 if (retval != ERROR_OK)
1655 return retval;
1656
1657 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1658 apsel, apid);
1659
1660 return retval;
1661 }
1662
1663 COMMAND_HANDLER(dap_apid_command)
1664 {
1665 struct target *target = get_current_target(CMD_CTX);
1666 struct arm *arm = target_to_arm(target);
1667 struct adiv5_dap *dap = arm->dap;
1668
1669 uint32_t apsel, apselsave, apid;
1670 int retval;
1671
1672 apselsave = dap->apsel;
1673 switch (CMD_ARGC) {
1674 case 0:
1675 apsel = dap->apsel;
1676 break;
1677 case 1:
1678 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1679 /* AP address is in bits 31:24 of DP_SELECT */
1680 if (apsel >= 256)
1681 return ERROR_INVALID_ARGUMENTS;
1682 break;
1683 default:
1684 return ERROR_COMMAND_SYNTAX_ERROR;
1685 }
1686
1687 if (apselsave != apsel)
1688 dap_ap_select(dap, apsel);
1689
1690 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1691 if (retval != ERROR_OK)
1692 return retval;
1693 retval = dap_run(dap);
1694 if (retval != ERROR_OK)
1695 return retval;
1696
1697 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1698 if (apselsave != apsel)
1699 dap_ap_select(dap, apselsave);
1700
1701 return retval;
1702 }
1703
1704 static const struct command_registration dap_commands[] = {
1705 {
1706 .name = "info",
1707 .handler = handle_dap_info_command,
1708 .mode = COMMAND_EXEC,
1709 .help = "display ROM table for MEM-AP "
1710 "(default currently selected AP)",
1711 .usage = "[ap_num]",
1712 },
1713 {
1714 .name = "apsel",
1715 .handler = dap_apsel_command,
1716 .mode = COMMAND_EXEC,
1717 .help = "Set the currently selected AP (default 0) "
1718 "and display the result",
1719 .usage = "[ap_num]",
1720 },
1721 {
1722 .name = "apid",
1723 .handler = dap_apid_command,
1724 .mode = COMMAND_EXEC,
1725 .help = "return ID register from AP "
1726 "(default currently selected AP)",
1727 .usage = "[ap_num]",
1728 },
1729 {
1730 .name = "baseaddr",
1731 .handler = dap_baseaddr_command,
1732 .mode = COMMAND_EXEC,
1733 .help = "return debug base address from MEM-AP "
1734 "(default currently selected AP)",
1735 .usage = "[ap_num]",
1736 },
1737 {
1738 .name = "memaccess",
1739 .handler = dap_memaccess_command,
1740 .mode = COMMAND_EXEC,
1741 .help = "set/get number of extra tck for MEM-AP memory "
1742 "bus access [0-255]",
1743 .usage = "[cycles]",
1744 },
1745 COMMAND_REGISTRATION_DONE
1746 };
1747
1748 const struct command_registration dap_command_handlers[] = {
1749 {
1750 .name = "dap",
1751 .mode = COMMAND_EXEC,
1752 .help = "DAP command group",
1753 .chain = dap_commands,
1754 },
1755 COMMAND_REGISTRATION_DONE
1756 };
1757
1758
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