1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
88 return tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
106 void dap_ap_select(struct adiv5_dap
*dap
, uint8_t ap
)
108 uint32_t new_ap
= (ap
<< 24) & 0xFF000000;
110 if (new_ap
!= dap
->ap_current
) {
111 dap
->ap_current
= new_ap
;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
115 dap
->ap_bank_value
= -1;
119 static int mem_ap_setup_csw(struct adiv5_ap
*ap
, uint32_t csw
)
121 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
|
124 if (csw
!= ap
->csw_value
) {
125 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
126 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_CSW
, csw
);
127 if (retval
!= ERROR_OK
)
134 static int mem_ap_setup_tar(struct adiv5_ap
*ap
, uint32_t tar
)
136 if (tar
!= ap
->tar_value
||
137 (ap
->csw_value
& CSW_ADDRINC_MASK
)) {
138 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
139 int retval
= dap_queue_ap_write(ap
, MEM_AP_REG_TAR
, tar
);
140 if (retval
!= ERROR_OK
)
148 * Queue transactions setting up transfer parameters for the
149 * currently selected MEM-AP.
151 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
152 * initiate data reads or writes using memory or peripheral addresses.
153 * If the CSW is configured for it, the TAR may be automatically
154 * incremented after each transfer.
156 * @param ap The MEM-AP.
157 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
158 * matches the cached value, the register is not changed.
159 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
160 * matches the cached address, the register is not changed.
162 * @return ERROR_OK if the transaction was properly queued, else a fault code.
164 static int mem_ap_setup_transfer(struct adiv5_ap
*ap
, uint32_t csw
, uint32_t tar
)
167 retval
= mem_ap_setup_csw(ap
, csw
);
168 if (retval
!= ERROR_OK
)
170 retval
= mem_ap_setup_tar(ap
, tar
);
171 if (retval
!= ERROR_OK
)
177 * Asynchronous (queued) read of a word from memory or a system register.
179 * @param ap The MEM-AP to access.
180 * @param address Address of the 32-bit word to read; it must be
181 * readable by the currently selected MEM-AP.
182 * @param value points to where the word will be stored when the
183 * transaction queue is flushed (assuming no errors).
185 * @return ERROR_OK for success. Otherwise a fault code.
187 int mem_ap_read_u32(struct adiv5_ap
*ap
, uint32_t address
,
192 /* Use banked addressing (REG_BDx) to avoid some link traffic
193 * (updating TAR) when reading several consecutive addresses.
195 retval
= mem_ap_setup_transfer(ap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
196 address
& 0xFFFFFFF0);
197 if (retval
!= ERROR_OK
)
200 return dap_queue_ap_read(ap
, MEM_AP_REG_BD0
| (address
& 0xC), value
);
204 * Synchronous read of a word from memory or a system register.
205 * As a side effect, this flushes any queued transactions.
207 * @param ap The MEM-AP to access.
208 * @param address Address of the 32-bit word to read; it must be
209 * readable by the currently selected MEM-AP.
210 * @param value points to where the result will be stored.
212 * @return ERROR_OK for success; *value holds the result.
213 * Otherwise a fault code.
215 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
220 retval
= mem_ap_read_u32(ap
, address
, value
);
221 if (retval
!= ERROR_OK
)
224 return dap_run(ap
->dap
);
228 * Asynchronous (queued) write of a word to memory or a system register.
230 * @param ap The MEM-AP to access.
231 * @param address Address to be written; it must be writable by
232 * the currently selected MEM-AP.
233 * @param value Word that will be written to the address when transaction
234 * queue is flushed (assuming no errors).
236 * @return ERROR_OK for success. Otherwise a fault code.
238 int mem_ap_write_u32(struct adiv5_ap
*ap
, uint32_t address
,
243 /* Use banked addressing (REG_BDx) to avoid some link traffic
244 * (updating TAR) when writing several consecutive addresses.
246 retval
= mem_ap_setup_transfer(ap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
247 address
& 0xFFFFFFF0);
248 if (retval
!= ERROR_OK
)
251 return dap_queue_ap_write(ap
, MEM_AP_REG_BD0
| (address
& 0xC),
256 * Synchronous write of a word to memory or a system register.
257 * As a side effect, this flushes any queued transactions.
259 * @param ap The MEM-AP to access.
260 * @param address Address to be written; it must be writable by
261 * the currently selected MEM-AP.
262 * @param value Word that will be written.
264 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
266 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
269 int retval
= mem_ap_write_u32(ap
, address
, value
);
271 if (retval
!= ERROR_OK
)
274 return dap_run(ap
->dap
);
278 * Synchronous write of a block of memory, using a specific access size.
280 * @param ap The MEM-AP to access.
281 * @param buffer The data buffer to write. No particular alignment is assumed.
282 * @param size Which access size to use, in bytes. 1, 2 or 4.
283 * @param count The number of writes to do (in size units, not bytes).
284 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
285 * @param addrinc Whether the target address should be increased for each write or not. This
286 * should normally be true, except when writing to e.g. a FIFO.
287 * @return ERROR_OK on success, otherwise an error code.
289 static int mem_ap_write(struct adiv5_ap
*ap
, const uint8_t *buffer
, uint32_t size
, uint32_t count
,
290 uint32_t address
, bool addrinc
)
292 struct adiv5_dap
*dap
= ap
->dap
;
293 size_t nbytes
= size
* count
;
294 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
299 /* TI BE-32 Quirks mode:
300 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
301 * size write address bytes written in order
302 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
303 * 2 TAR ^ 2 (val >> 8), (val)
305 * For example, if you attempt to write a single byte to address 0, the processor
306 * will actually write a byte to address 3.
308 * To make writes of size < 4 work as expected, we xor a value with the address before
309 * setting the TAP, and we set the TAP after every transfer rather then relying on
310 * address increment. */
313 csw_size
= CSW_32BIT
;
315 } else if (size
== 2) {
316 csw_size
= CSW_16BIT
;
317 addr_xor
= dap
->ti_be_32_quirks
? 2 : 0;
318 } else if (size
== 1) {
320 addr_xor
= dap
->ti_be_32_quirks
? 3 : 0;
322 return ERROR_TARGET_UNALIGNED_ACCESS
;
325 if (ap
->unaligned_access_bad
&& (address
% size
!= 0))
326 return ERROR_TARGET_UNALIGNED_ACCESS
;
328 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
329 if (retval
!= ERROR_OK
)
333 uint32_t this_size
= size
;
335 /* Select packed transfer if possible */
336 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
337 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
339 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
341 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
344 if (retval
!= ERROR_OK
)
347 /* How many source bytes each transfer will consume, and their location in the DRW,
348 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
349 uint32_t outvalue
= 0;
350 if (dap
->ti_be_32_quirks
) {
353 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
354 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
355 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
356 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
359 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (address
++ & 3) ^ addr_xor
);
360 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (address
++ & 3) ^ addr_xor
);
363 outvalue
|= (uint32_t)*buffer
++ << 8 * (0 ^ (address
++ & 3) ^ addr_xor
);
369 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
370 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
372 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
374 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
380 retval
= dap_queue_ap_write(ap
, MEM_AP_REG_DRW
, outvalue
);
381 if (retval
!= ERROR_OK
)
384 /* Rewrite TAR if it wrapped or we're xoring addresses */
385 if (addrinc
&& (addr_xor
|| (address
% ap
->tar_autoincr_block
< size
&& nbytes
> 0))) {
386 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
387 if (retval
!= ERROR_OK
)
392 /* REVISIT: Might want to have a queued version of this function that does not run. */
393 if (retval
== ERROR_OK
)
394 retval
= dap_run(dap
);
396 if (retval
!= ERROR_OK
) {
398 if (dap_queue_ap_read(ap
, MEM_AP_REG_TAR
, &tar
) == ERROR_OK
399 && dap_run(dap
) == ERROR_OK
)
400 LOG_ERROR("Failed to write memory at 0x%08"PRIx32
, tar
);
402 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
409 * Synchronous read of a block of memory, using a specific access size.
411 * @param ap The MEM-AP to access.
412 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
413 * @param size Which access size to use, in bytes. 1, 2 or 4.
414 * @param count The number of reads to do (in size units, not bytes).
415 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
416 * @param addrinc Whether the target address should be increased after each read or not. This
417 * should normally be true, except when reading from e.g. a FIFO.
418 * @return ERROR_OK on success, otherwise an error code.
420 static int mem_ap_read(struct adiv5_ap
*ap
, uint8_t *buffer
, uint32_t size
, uint32_t count
,
421 uint32_t adr
, bool addrinc
)
423 struct adiv5_dap
*dap
= ap
->dap
;
424 size_t nbytes
= size
* count
;
425 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
427 uint32_t address
= adr
;
430 /* TI BE-32 Quirks mode:
431 * Reads on big-endian TMS570 behave strangely differently than writes.
432 * They read from the physical address requested, but with DRW byte-reversed.
433 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
434 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
438 csw_size
= CSW_32BIT
;
440 csw_size
= CSW_16BIT
;
444 return ERROR_TARGET_UNALIGNED_ACCESS
;
446 if (ap
->unaligned_access_bad
&& (adr
% size
!= 0))
447 return ERROR_TARGET_UNALIGNED_ACCESS
;
449 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
450 * over-allocation if packed transfers are going to be used, but determining the real need at
451 * this point would be messy. */
452 uint32_t *read_buf
= malloc(count
* sizeof(uint32_t));
453 uint32_t *read_ptr
= read_buf
;
454 if (read_buf
== NULL
) {
455 LOG_ERROR("Failed to allocate read buffer");
459 retval
= mem_ap_setup_tar(ap
, address
);
460 if (retval
!= ERROR_OK
) {
465 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
466 * useful bytes it contains, and their location in the word, depends on the type of transfer
469 uint32_t this_size
= size
;
471 /* Select packed transfer if possible */
472 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
473 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
475 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
477 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
479 if (retval
!= ERROR_OK
)
482 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_DRW
, read_ptr
++);
483 if (retval
!= ERROR_OK
)
487 address
+= this_size
;
489 /* Rewrite TAR if it wrapped */
490 if (addrinc
&& address
% ap
->tar_autoincr_block
< size
&& nbytes
> 0) {
491 retval
= mem_ap_setup_tar(ap
, address
);
492 if (retval
!= ERROR_OK
)
497 if (retval
== ERROR_OK
)
498 retval
= dap_run(dap
);
502 nbytes
= size
* count
;
505 /* If something failed, read TAR to find out how much data was successfully read, so we can
506 * at least give the caller what we have. */
507 if (retval
!= ERROR_OK
) {
509 if (dap_queue_ap_read(ap
, MEM_AP_REG_TAR
, &tar
) == ERROR_OK
510 && dap_run(dap
) == ERROR_OK
) {
511 LOG_ERROR("Failed to read memory at 0x%08"PRIx32
, tar
);
512 if (nbytes
> tar
- address
)
513 nbytes
= tar
- address
;
515 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
520 /* Replay loop to populate caller's buffer from the correct word and byte lane */
522 uint32_t this_size
= size
;
524 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
525 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
529 if (dap
->ti_be_32_quirks
) {
532 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
533 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
535 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
537 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
542 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
543 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
545 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
547 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
559 int mem_ap_read_buf(struct adiv5_ap
*ap
,
560 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
562 return mem_ap_read(ap
, buffer
, size
, count
, address
, true);
565 int mem_ap_write_buf(struct adiv5_ap
*ap
,
566 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
568 return mem_ap_write(ap
, buffer
, size
, count
, address
, true);
571 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
572 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
574 return mem_ap_read(ap
, buffer
, size
, count
, address
, false);
577 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
578 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
580 return mem_ap_write(ap
, buffer
, size
, count
, address
, false);
583 /*--------------------------------------------------------------------------*/
586 #define DAP_POWER_DOMAIN_TIMEOUT (10)
588 /* FIXME don't import ... just initialize as
589 * part of DAP transport setup
591 extern const struct dap_ops jtag_dp_ops
;
593 /*--------------------------------------------------------------------------*/
598 struct adiv5_dap
*dap_init(void)
600 struct adiv5_dap
*dap
= calloc(1, sizeof(struct adiv5_dap
));
602 /* Set up with safe defaults */
603 for (i
= 0; i
<= 255; i
++) {
604 dap
->ap
[i
].dap
= dap
;
605 dap
->ap
[i
].ap_num
= i
;
606 /* memaccess_tck max is 255 */
607 dap
->ap
[i
].memaccess_tck
= 255;
608 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
609 dap
->ap
[i
].tar_autoincr_block
= (1<<10);
611 dap
->ap_current
= -1;
612 dap
->ap_bank_value
= -1;
613 dap
->dp_bank_value
= -1;
618 * Initialize a DAP. This sets up the power domains, prepares the DP
619 * for further use and activates overrun checking.
621 * @param dap The DAP being initialized.
623 int dap_dp_init(struct adiv5_dap
*dap
)
628 /* JTAG-DP or SWJ-DP, in JTAG mode
629 * ... for SWD mode this is patched as part
631 * FIXME: This should already be setup by the respective transport specific DAP creation.
634 dap
->ops
= &jtag_dp_ops
;
636 dap
->ap_current
= -1;
637 dap
->ap_bank_value
= -1;
638 dap
->last_read
= NULL
;
640 for (size_t i
= 0; i
< 10; i
++) {
641 /* DP initialization */
643 dap
->dp_bank_value
= 0;
645 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
646 if (retval
!= ERROR_OK
)
649 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, SSTICKYERR
);
650 if (retval
!= ERROR_OK
)
653 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
654 if (retval
!= ERROR_OK
)
657 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
658 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
659 if (retval
!= ERROR_OK
)
662 /* Check that we have debug power domains activated */
663 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
664 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
665 CDBGPWRUPACK
, CDBGPWRUPACK
,
666 DAP_POWER_DOMAIN_TIMEOUT
);
667 if (retval
!= ERROR_OK
)
670 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
671 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
672 CSYSPWRUPACK
, CSYSPWRUPACK
,
673 DAP_POWER_DOMAIN_TIMEOUT
);
674 if (retval
!= ERROR_OK
)
677 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
678 if (retval
!= ERROR_OK
)
681 /* With debug power on we can activate OVERRUN checking */
682 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
683 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
684 if (retval
!= ERROR_OK
)
686 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
687 if (retval
!= ERROR_OK
)
690 retval
= dap_run(dap
);
691 if (retval
!= ERROR_OK
)
701 * Initialize a DAP. This sets up the power domains, prepares the DP
702 * for further use, and arranges to use AP #0 for all AP operations
703 * until dap_ap-select() changes that policy.
705 * @param ap The MEM-AP being initialized.
707 int mem_ap_init(struct adiv5_ap
*ap
)
709 /* check that we support packed transfers */
712 struct adiv5_dap
*dap
= ap
->dap
;
714 retval
= mem_ap_setup_transfer(ap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, 0);
715 if (retval
!= ERROR_OK
)
718 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CSW
, &csw
);
719 if (retval
!= ERROR_OK
)
722 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_CFG
, &cfg
);
723 if (retval
!= ERROR_OK
)
726 retval
= dap_run(dap
);
727 if (retval
!= ERROR_OK
)
730 if (csw
& CSW_ADDRINC_PACKED
)
731 ap
->packed_transfers
= true;
733 ap
->packed_transfers
= false;
735 /* Packed transfers on TI BE-32 processors do not work correctly in
737 if (dap
->ti_be_32_quirks
)
738 ap
->packed_transfers
= false;
740 LOG_DEBUG("MEM_AP Packed Transfers: %s",
741 ap
->packed_transfers
? "enabled" : "disabled");
743 /* The ARM ADI spec leaves implementation-defined whether unaligned
744 * memory accesses work, only work partially, or cause a sticky error.
745 * On TI BE-32 processors, reads seem to return garbage in some bytes
746 * and unaligned writes seem to cause a sticky error.
747 * TODO: it would be nice to have a way to detect whether unaligned
748 * operations are supported on other processors. */
749 ap
->unaligned_access_bad
= dap
->ti_be_32_quirks
;
751 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
752 !!(cfg
& 0x04), !!(cfg
& 0x02), !!(cfg
& 0x01));
757 /* CID interpretation -- see ARM IHI 0029B section 3
758 * and ARM IHI 0031A table 13-3.
760 static const char *class_description
[16] = {
761 "Reserved", "ROM table", "Reserved", "Reserved",
762 "Reserved", "Reserved", "Reserved", "Reserved",
763 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
764 "Reserved", "OptimoDE DESS",
765 "Generic IP component", "PrimeCell or System component"
768 static bool is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
770 return cid3
== 0xb1 && cid2
== 0x05
771 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
775 * This function checks the ID for each access port to find the requested Access Port type
777 int dap_find_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, struct adiv5_ap
**ap_out
)
781 /* Maximum AP number is 255 since the SELECT register is 8 bits */
782 for (ap_num
= 0; ap_num
<= 255; ap_num
++) {
784 /* read the IDR register of the Access Port */
787 int retval
= dap_queue_ap_read(dap_ap(dap
, ap_num
), AP_REG_IDR
, &id_val
);
788 if (retval
!= ERROR_OK
)
791 retval
= dap_run(dap
);
795 * 27-24 : JEDEC bank (0x4 for ARM)
796 * 23-17 : JEDEC code (0x3B for ARM)
797 * 16-13 : Class (0b1000=Mem-AP)
799 * 7-4 : AP Variant (non-zero for JTAG-AP)
800 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
803 /* Reading register for a non-existant AP should not cause an error,
804 * but just to be sure, try to continue searching if an error does happen.
806 if ((retval
== ERROR_OK
) && /* Register read success */
807 ((id_val
& IDR_JEP106
) == IDR_JEP106_ARM
) && /* Jedec codes match */
808 ((id_val
& IDR_TYPE
) == type_to_find
)) { /* type matches*/
810 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32
")",
811 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
812 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
813 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
814 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown",
817 *ap_out
= &dap
->ap
[ap_num
];
822 LOG_DEBUG("No %s found",
823 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
824 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
825 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
826 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown");
830 int dap_get_debugbase(struct adiv5_ap
*ap
,
831 uint32_t *dbgbase
, uint32_t *apid
)
833 struct adiv5_dap
*dap
= ap
->dap
;
836 retval
= dap_queue_ap_read(ap
, MEM_AP_REG_BASE
, dbgbase
);
837 if (retval
!= ERROR_OK
)
839 retval
= dap_queue_ap_read(ap
, AP_REG_IDR
, apid
);
840 if (retval
!= ERROR_OK
)
842 retval
= dap_run(dap
);
843 if (retval
!= ERROR_OK
)
849 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
850 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
, int32_t *idx
)
852 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
858 retval
= mem_ap_read_atomic_u32(ap
, (dbgbase
&0xFFFFF000) |
859 entry_offset
, &romentry
);
860 if (retval
!= ERROR_OK
)
863 component_base
= (dbgbase
& 0xFFFFF000)
864 + (romentry
& 0xFFFFF000);
866 if (romentry
& 0x1) {
868 retval
= mem_ap_read_atomic_u32(ap
, component_base
| 0xff4, &c_cid1
);
869 if (retval
!= ERROR_OK
) {
870 LOG_ERROR("Can't read component with base address 0x%" PRIx32
871 ", the corresponding core might be turned off", component_base
);
874 if (((c_cid1
>> 4) & 0x0f) == 1) {
875 retval
= dap_lookup_cs_component(ap
, component_base
,
877 if (retval
== ERROR_OK
)
879 if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
883 retval
= mem_ap_read_atomic_u32(ap
,
884 (component_base
& 0xfffff000) | 0xfcc,
886 if (retval
!= ERROR_OK
)
888 if ((devtype
& 0xff) == type
) {
890 *addr
= component_base
;
897 } while (romentry
> 0);
900 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
905 static int dap_rom_display(struct command_context
*cmd_ctx
,
906 struct adiv5_ap
*ap
, uint32_t dbgbase
, int depth
)
908 struct adiv5_dap
*dap
= ap
->dap
;
910 uint32_t cid0
, cid1
, cid2
, cid3
, memtype
, romentry
;
911 uint16_t entry_offset
;
915 command_print(cmd_ctx
, "\tTables too deep");
920 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
922 /* bit 16 of apid indicates a memory access port */
924 command_print(cmd_ctx
, "\t%sValid ROM table present", tabs
);
926 command_print(cmd_ctx
, "\t%sROM table in legacy format", tabs
);
928 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
929 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
930 if (retval
!= ERROR_OK
)
932 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
933 if (retval
!= ERROR_OK
)
935 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
936 if (retval
!= ERROR_OK
)
938 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
939 if (retval
!= ERROR_OK
)
941 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
942 if (retval
!= ERROR_OK
)
944 retval
= dap_run(dap
);
945 if (retval
!= ERROR_OK
)
948 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
949 command_print(cmd_ctx
, "\t%sCID3 0x%02x"
954 (unsigned)cid3
, (unsigned)cid2
,
955 (unsigned)cid1
, (unsigned)cid0
);
957 command_print(cmd_ctx
, "\t%sMEMTYPE system memory present on bus", tabs
);
959 command_print(cmd_ctx
, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs
);
961 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
962 for (entry_offset
= 0; ; entry_offset
+= 4) {
963 retval
= mem_ap_read_atomic_u32(ap
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
964 if (retval
!= ERROR_OK
)
966 command_print(cmd_ctx
, "\t%sROMTABLE[0x%x] = 0x%" PRIx32
"",
967 tabs
, entry_offset
, romentry
);
968 if (romentry
& 0x01) {
969 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
970 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
971 uint32_t component_base
;
973 const char *type
, *full
;
975 component_base
= (dbgbase
& 0xFFFFF000) + (romentry
& 0xFFFFF000);
977 /* IDs are in last 4K section */
978 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFE0, &c_pid0
);
979 if (retval
!= ERROR_OK
) {
980 command_print(cmd_ctx
, "\t%s\tCan't read component with base address 0x%" PRIx32
981 ", the corresponding core might be turned off", tabs
, component_base
);
985 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFE4, &c_pid1
);
986 if (retval
!= ERROR_OK
)
989 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFE8, &c_pid2
);
990 if (retval
!= ERROR_OK
)
993 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFEC, &c_pid3
);
994 if (retval
!= ERROR_OK
)
997 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFD0, &c_pid4
);
998 if (retval
!= ERROR_OK
)
1002 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFF0, &c_cid0
);
1003 if (retval
!= ERROR_OK
)
1006 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFF4, &c_cid1
);
1007 if (retval
!= ERROR_OK
)
1010 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFF8, &c_cid2
);
1011 if (retval
!= ERROR_OK
)
1014 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFFC, &c_cid3
);
1015 if (retval
!= ERROR_OK
)
1019 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
", "
1020 "start address 0x%" PRIx32
, component_base
,
1021 /* component may take multiple 4K pages */
1022 (uint32_t)(component_base
- 0x1000*(c_pid4
>> 4)));
1023 command_print(cmd_ctx
, "\t\tComponent class is 0x%" PRIx8
", %s",
1024 (uint8_t)((c_cid1
>> 4) & 0xf),
1025 /* See ARM IHI 0029B Table 3-3 */
1026 class_description
[(c_cid1
>> 4) & 0xf]);
1028 /* CoreSight component? */
1029 if (((c_cid1
>> 4) & 0x0f) == 9) {
1032 const char *major
= "Reserved", *subtype
= "Reserved";
1034 retval
= mem_ap_read_atomic_u32(ap
,
1035 (component_base
& 0xfffff000) | 0xfcc,
1037 if (retval
!= ERROR_OK
)
1039 minor
= (devtype
>> 4) & 0x0f;
1040 switch (devtype
& 0x0f) {
1042 major
= "Miscellaneous";
1048 subtype
= "Validation component";
1053 major
= "Trace Sink";
1070 major
= "Trace Link";
1076 subtype
= "Funnel, router";
1082 subtype
= "FIFO, buffer";
1087 major
= "Trace Source";
1093 subtype
= "Processor";
1099 subtype
= "Engine/Coprocessor";
1105 subtype
= "Software";
1110 major
= "Debug Control";
1116 subtype
= "Trigger Matrix";
1119 subtype
= "Debug Auth";
1122 subtype
= "Power Requestor";
1127 major
= "Debug Logic";
1133 subtype
= "Processor";
1139 subtype
= "Engine/Coprocessor";
1150 major
= "Perfomance Monitor";
1156 subtype
= "Processor";
1162 subtype
= "Engine/Coprocessor";
1173 command_print(cmd_ctx
, "\t\tType is 0x%02" PRIx8
", %s, %s",
1174 (uint8_t)(devtype
& 0xff),
1176 /* REVISIT also show 0xfc8 DevId */
1179 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1180 command_print(cmd_ctx
,
1189 command_print(cmd_ctx
,
1190 "\t\tPeripheral ID[4..0] = hex "
1191 "%02x %02x %02x %02x %02x",
1192 (int)c_pid4
, (int)c_pid3
, (int)c_pid2
,
1193 (int)c_pid1
, (int)c_pid0
);
1195 /* Part number interpretations are from Cortex
1196 * core specs, the CoreSight components TRM
1197 * (ARM DDI 0314H), CoreSight System Design
1198 * Guide (ARM DGI 0012D) and ETM specs; also
1199 * from chip observation (e.g. TI SDTI).
1201 part_num
= (c_pid0
& 0xff);
1202 part_num
|= (c_pid1
& 0x0f) << 8;
1205 type
= "Cortex-M3 NVIC";
1206 full
= "(Interrupt Controller)";
1209 type
= "Cortex-M3 ITM";
1210 full
= "(Instrumentation Trace Module)";
1213 type
= "Cortex-M3 DWT";
1214 full
= "(Data Watchpoint and Trace)";
1217 type
= "Cortex-M3 FBP";
1218 full
= "(Flash Patch and Breakpoint)";
1221 type
= "Cortex-M0 SCS";
1222 full
= "(System Control Space)";
1225 type
= "Cortex-M0 DWT";
1226 full
= "(Data Watchpoint and Trace)";
1229 type
= "Cortex-M0 BPU";
1230 full
= "(Breakpoint Unit)";
1233 type
= "Cortex-M4 SCS";
1234 full
= "(System Control Space)";
1237 type
= "CoreSight ETM11";
1238 full
= "(Embedded Trace)";
1240 /* case 0x113: what? */
1241 case 0x120: /* from OMAP3 memmap */
1243 full
= "(System Debug Trace Interface)";
1245 case 0x343: /* from OMAP3 memmap */
1250 type
= "Coresight CTI";
1251 full
= "(Cross Trigger)";
1254 type
= "Coresight ETB";
1255 full
= "(Trace Buffer)";
1258 type
= "Coresight CSTF";
1259 full
= "(Trace Funnel)";
1262 type
= "CoreSight ETM9";
1263 full
= "(Embedded Trace)";
1266 type
= "Coresight TPIU";
1267 full
= "(Trace Port Interface Unit)";
1270 type
= "Coresight ITM";
1271 full
= "(Instrumentation Trace Macrocell)";
1274 type
= "Coresight SWO";
1275 full
= "(Single Wire Output)";
1278 type
= "Coresight HTM";
1279 full
= "(AHB Trace Macrocell)";
1282 type
= "CoreSight ETM11";
1283 full
= "(Embedded Trace)";
1286 type
= "Cortex-A8 ETM";
1287 full
= "(Embedded Trace)";
1290 type
= "Cortex-A8 CTI";
1291 full
= "(Cross Trigger)";
1294 type
= "Cortex-M3 TPIU";
1295 full
= "(Trace Port Interface Unit)";
1298 type
= "Cortex-M3 ETM";
1299 full
= "(Embedded Trace)";
1302 type
= "Cortex-M4 ETM";
1303 full
= "(Embedded Trace)";
1306 type
= "Cortex-R4 ETM";
1307 full
= "(Embedded Trace)";
1310 type
= "CoreSight Component";
1311 full
= "(unidentified Cortex-A9 component)";
1314 type
= "CoreSight TMC";
1315 full
= "(Trace Memory Controller)";
1318 type
= "CoreSight STM";
1319 full
= "(System Trace Macrocell)";
1322 type
= "CoreSight PMU";
1323 full
= "(Performance Monitoring Unit)";
1326 type
= "Cortex-M4 TPUI";
1327 full
= "(Trace Port Interface Unit)";
1330 type
= "Cortex-A5 ETM";
1331 full
= "(Embedded Trace)";
1334 type
= "Cortex-A5 Debug";
1335 full
= "(Debug Unit)";
1338 type
= "Cortex-A8 Debug";
1339 full
= "(Debug Unit)";
1342 type
= "Cortex-A9 Debug";
1343 full
= "(Debug Unit)";
1346 type
= "Cortex-A15 Debug";
1347 full
= "(Debug Unit)";
1350 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32
, part_num
);
1351 type
= "-*- unrecognized -*-";
1355 command_print(cmd_ctx
, "\t\tPart is %s %s",
1359 if (((c_cid1
>> 4) & 0x0f) == 1) {
1360 retval
= dap_rom_display(cmd_ctx
, ap
, component_base
, depth
+ 1);
1361 if (retval
!= ERROR_OK
)
1366 command_print(cmd_ctx
, "\t\tComponent not present");
1371 command_print(cmd_ctx
, "\t%s\tEnd of ROM table", tabs
);
1375 static int dap_info_command(struct command_context
*cmd_ctx
,
1376 struct adiv5_ap
*ap
)
1379 uint32_t dbgbase
, apid
;
1380 int romtable_present
= 0;
1383 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1384 retval
= dap_get_debugbase(ap
, &dbgbase
, &apid
);
1385 if (retval
!= ERROR_OK
)
1388 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1390 command_print(cmd_ctx
, "No AP found at this ap 0x%x", ap
->ap_num
);
1394 switch (apid
& (IDR_JEP106
| IDR_TYPE
)) {
1395 case IDR_JEP106_ARM
| AP_TYPE_JTAG_AP
:
1396 command_print(cmd_ctx
, "\tType is JTAG-AP");
1398 case IDR_JEP106_ARM
| AP_TYPE_AHB_AP
:
1399 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1401 case IDR_JEP106_ARM
| AP_TYPE_APB_AP
:
1402 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1404 case IDR_JEP106_ARM
| AP_TYPE_AXI_AP
:
1405 command_print(cmd_ctx
, "\tType is MEM-AP AXI");
1408 command_print(cmd_ctx
, "\tUnknown AP type");
1412 /* NOTE: a MEM-AP may have a single CoreSight component that's
1413 * not a ROM table ... or have no such components at all.
1415 mem_ap
= (apid
& IDR_CLASS
) == AP_CLASS_MEM_AP
;
1417 command_print(cmd_ctx
, "MEM-AP BASE 0x%8.8" PRIx32
, dbgbase
);
1419 romtable_present
= dbgbase
!= 0xFFFFFFFF;
1420 if (romtable_present
)
1421 dap_rom_display(cmd_ctx
, ap
, dbgbase
, 0);
1423 command_print(cmd_ctx
, "\tNo ROM table present");
1429 COMMAND_HANDLER(handle_dap_info_command
)
1431 struct target
*target
= get_current_target(CMD_CTX
);
1432 struct arm
*arm
= target_to_arm(target
);
1433 struct adiv5_dap
*dap
= arm
->dap
;
1441 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1443 return ERROR_COMMAND_SYNTAX_ERROR
;
1446 return ERROR_COMMAND_SYNTAX_ERROR
;
1449 return dap_info_command(CMD_CTX
, &dap
->ap
[apsel
]);
1452 COMMAND_HANDLER(dap_baseaddr_command
)
1454 struct target
*target
= get_current_target(CMD_CTX
);
1455 struct arm
*arm
= target_to_arm(target
);
1456 struct adiv5_dap
*dap
= arm
->dap
;
1458 uint32_t apsel
, baseaddr
;
1466 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1467 /* AP address is in bits 31:24 of DP_SELECT */
1469 return ERROR_COMMAND_SYNTAX_ERROR
;
1472 return ERROR_COMMAND_SYNTAX_ERROR
;
1475 /* NOTE: assumes we're talking to a MEM-AP, which
1476 * has a base address. There are other kinds of AP,
1477 * though they're not common for now. This should
1478 * use the ID register to verify it's a MEM-AP.
1480 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), MEM_AP_REG_BASE
, &baseaddr
);
1481 if (retval
!= ERROR_OK
)
1483 retval
= dap_run(dap
);
1484 if (retval
!= ERROR_OK
)
1487 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1492 COMMAND_HANDLER(dap_memaccess_command
)
1494 struct target
*target
= get_current_target(CMD_CTX
);
1495 struct arm
*arm
= target_to_arm(target
);
1496 struct adiv5_dap
*dap
= arm
->dap
;
1498 uint32_t memaccess_tck
;
1502 memaccess_tck
= dap
->ap
[dap
->apsel
].memaccess_tck
;
1505 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1508 return ERROR_COMMAND_SYNTAX_ERROR
;
1510 dap
->ap
[dap
->apsel
].memaccess_tck
= memaccess_tck
;
1512 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1513 dap
->ap
[dap
->apsel
].memaccess_tck
);
1518 COMMAND_HANDLER(dap_apsel_command
)
1520 struct target
*target
= get_current_target(CMD_CTX
);
1521 struct arm
*arm
= target_to_arm(target
);
1522 struct adiv5_dap
*dap
= arm
->dap
;
1524 uint32_t apsel
, apid
;
1532 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1533 /* AP address is in bits 31:24 of DP_SELECT */
1535 return ERROR_COMMAND_SYNTAX_ERROR
;
1538 return ERROR_COMMAND_SYNTAX_ERROR
;
1543 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), AP_REG_IDR
, &apid
);
1544 if (retval
!= ERROR_OK
)
1546 retval
= dap_run(dap
);
1547 if (retval
!= ERROR_OK
)
1550 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1556 COMMAND_HANDLER(dap_apcsw_command
)
1558 struct target
*target
= get_current_target(CMD_CTX
);
1559 struct arm
*arm
= target_to_arm(target
);
1560 struct adiv5_dap
*dap
= arm
->dap
;
1562 uint32_t apcsw
= dap
->ap
[dap
->apsel
].csw_default
, sprot
= 0;
1566 command_print(CMD_CTX
, "apsel %" PRIi32
" selected, csw 0x%8.8" PRIx32
,
1567 (dap
->apsel
), apcsw
);
1570 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], sprot
);
1571 /* AP address is in bits 31:24 of DP_SELECT */
1573 return ERROR_COMMAND_SYNTAX_ERROR
;
1577 apcsw
&= ~CSW_SPROT
;
1580 return ERROR_COMMAND_SYNTAX_ERROR
;
1582 dap
->ap
[dap
->apsel
].csw_default
= apcsw
;
1589 COMMAND_HANDLER(dap_apid_command
)
1591 struct target
*target
= get_current_target(CMD_CTX
);
1592 struct arm
*arm
= target_to_arm(target
);
1593 struct adiv5_dap
*dap
= arm
->dap
;
1595 uint32_t apsel
, apid
;
1603 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1604 /* AP address is in bits 31:24 of DP_SELECT */
1606 return ERROR_COMMAND_SYNTAX_ERROR
;
1609 return ERROR_COMMAND_SYNTAX_ERROR
;
1612 retval
= dap_queue_ap_read(dap_ap(dap
, apsel
), AP_REG_IDR
, &apid
);
1613 if (retval
!= ERROR_OK
)
1615 retval
= dap_run(dap
);
1616 if (retval
!= ERROR_OK
)
1619 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1624 COMMAND_HANDLER(dap_ti_be_32_quirks_command
)
1626 struct target
*target
= get_current_target(CMD_CTX
);
1627 struct arm
*arm
= target_to_arm(target
);
1628 struct adiv5_dap
*dap
= arm
->dap
;
1630 uint32_t enable
= dap
->ti_be_32_quirks
;
1636 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], enable
);
1638 return ERROR_COMMAND_SYNTAX_ERROR
;
1641 return ERROR_COMMAND_SYNTAX_ERROR
;
1643 dap
->ti_be_32_quirks
= enable
;
1644 command_print(CMD_CTX
, "TI BE-32 quirks mode %s",
1645 enable
? "enabled" : "disabled");
1650 static const struct command_registration dap_commands
[] = {
1653 .handler
= handle_dap_info_command
,
1654 .mode
= COMMAND_EXEC
,
1655 .help
= "display ROM table for MEM-AP "
1656 "(default currently selected AP)",
1657 .usage
= "[ap_num]",
1661 .handler
= dap_apsel_command
,
1662 .mode
= COMMAND_EXEC
,
1663 .help
= "Set the currently selected AP (default 0) "
1664 "and display the result",
1665 .usage
= "[ap_num]",
1669 .handler
= dap_apcsw_command
,
1670 .mode
= COMMAND_EXEC
,
1671 .help
= "Set csw access bit ",
1677 .handler
= dap_apid_command
,
1678 .mode
= COMMAND_EXEC
,
1679 .help
= "return ID register from AP "
1680 "(default currently selected AP)",
1681 .usage
= "[ap_num]",
1685 .handler
= dap_baseaddr_command
,
1686 .mode
= COMMAND_EXEC
,
1687 .help
= "return debug base address from MEM-AP "
1688 "(default currently selected AP)",
1689 .usage
= "[ap_num]",
1692 .name
= "memaccess",
1693 .handler
= dap_memaccess_command
,
1694 .mode
= COMMAND_EXEC
,
1695 .help
= "set/get number of extra tck for MEM-AP memory "
1696 "bus access [0-255]",
1697 .usage
= "[cycles]",
1700 .name
= "ti_be_32_quirks",
1701 .handler
= dap_ti_be_32_quirks_command
,
1702 .mode
= COMMAND_CONFIG
,
1703 .help
= "set/get quirks mode for TI TMS450/TMS570 processors",
1704 .usage
= "[enable]",
1706 COMMAND_REGISTRATION_DONE
1709 const struct command_registration dap_command_handlers
[] = {
1712 .mode
= COMMAND_EXEC
,
1713 .help
= "DAP command group",
1715 .chain
= dap_commands
,
1717 COMMAND_REGISTRATION_DONE
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