e56f595bd89092e53fe8cfcecafaab0aaab818d2
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "jtag/interface.h"
76 #include "arm.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
79
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
81
82 /*
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
85 */
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
87 {
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
89 }
90
91 /***************************************************************************
92 * *
93 * DP and MEM-AP register access through APACC and DPACC *
94 * *
95 ***************************************************************************/
96
97 /**
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
101 *
102 * @param dap The DAP
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
105 */
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
107 {
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
109
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
114 */
115 dap->ap_bank_value = -1;
116 }
117 }
118
119 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
120 {
121 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
122 ap->csw_default;
123
124 if (csw != ap->csw_value) {
125 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
126 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
127 if (retval != ERROR_OK)
128 return retval;
129 ap->csw_value = csw;
130 }
131 return ERROR_OK;
132 }
133
134 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
135 {
136 if (tar != ap->tar_value ||
137 (ap->csw_value & CSW_ADDRINC_MASK)) {
138 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
139 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
140 if (retval != ERROR_OK)
141 return retval;
142 ap->tar_value = tar;
143 }
144 return ERROR_OK;
145 }
146
147 /**
148 * Queue transactions setting up transfer parameters for the
149 * currently selected MEM-AP.
150 *
151 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
152 * initiate data reads or writes using memory or peripheral addresses.
153 * If the CSW is configured for it, the TAR may be automatically
154 * incremented after each transfer.
155 *
156 * @param ap The MEM-AP.
157 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
158 * matches the cached value, the register is not changed.
159 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
160 * matches the cached address, the register is not changed.
161 *
162 * @return ERROR_OK if the transaction was properly queued, else a fault code.
163 */
164 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
165 {
166 int retval;
167 retval = mem_ap_setup_csw(ap, csw);
168 if (retval != ERROR_OK)
169 return retval;
170 retval = mem_ap_setup_tar(ap, tar);
171 if (retval != ERROR_OK)
172 return retval;
173 return ERROR_OK;
174 }
175
176 /**
177 * Asynchronous (queued) read of a word from memory or a system register.
178 *
179 * @param ap The MEM-AP to access.
180 * @param address Address of the 32-bit word to read; it must be
181 * readable by the currently selected MEM-AP.
182 * @param value points to where the word will be stored when the
183 * transaction queue is flushed (assuming no errors).
184 *
185 * @return ERROR_OK for success. Otherwise a fault code.
186 */
187 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
188 uint32_t *value)
189 {
190 int retval;
191
192 /* Use banked addressing (REG_BDx) to avoid some link traffic
193 * (updating TAR) when reading several consecutive addresses.
194 */
195 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
196 address & 0xFFFFFFF0);
197 if (retval != ERROR_OK)
198 return retval;
199
200 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
201 }
202
203 /**
204 * Synchronous read of a word from memory or a system register.
205 * As a side effect, this flushes any queued transactions.
206 *
207 * @param ap The MEM-AP to access.
208 * @param address Address of the 32-bit word to read; it must be
209 * readable by the currently selected MEM-AP.
210 * @param value points to where the result will be stored.
211 *
212 * @return ERROR_OK for success; *value holds the result.
213 * Otherwise a fault code.
214 */
215 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
216 uint32_t *value)
217 {
218 int retval;
219
220 retval = mem_ap_read_u32(ap, address, value);
221 if (retval != ERROR_OK)
222 return retval;
223
224 return dap_run(ap->dap);
225 }
226
227 /**
228 * Asynchronous (queued) write of a word to memory or a system register.
229 *
230 * @param ap The MEM-AP to access.
231 * @param address Address to be written; it must be writable by
232 * the currently selected MEM-AP.
233 * @param value Word that will be written to the address when transaction
234 * queue is flushed (assuming no errors).
235 *
236 * @return ERROR_OK for success. Otherwise a fault code.
237 */
238 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
239 uint32_t value)
240 {
241 int retval;
242
243 /* Use banked addressing (REG_BDx) to avoid some link traffic
244 * (updating TAR) when writing several consecutive addresses.
245 */
246 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
247 address & 0xFFFFFFF0);
248 if (retval != ERROR_OK)
249 return retval;
250
251 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
252 value);
253 }
254
255 /**
256 * Synchronous write of a word to memory or a system register.
257 * As a side effect, this flushes any queued transactions.
258 *
259 * @param ap The MEM-AP to access.
260 * @param address Address to be written; it must be writable by
261 * the currently selected MEM-AP.
262 * @param value Word that will be written.
263 *
264 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
265 */
266 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
267 uint32_t value)
268 {
269 int retval = mem_ap_write_u32(ap, address, value);
270
271 if (retval != ERROR_OK)
272 return retval;
273
274 return dap_run(ap->dap);
275 }
276
277 /**
278 * Synchronous write of a block of memory, using a specific access size.
279 *
280 * @param ap The MEM-AP to access.
281 * @param buffer The data buffer to write. No particular alignment is assumed.
282 * @param size Which access size to use, in bytes. 1, 2 or 4.
283 * @param count The number of writes to do (in size units, not bytes).
284 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
285 * @param addrinc Whether the target address should be increased for each write or not. This
286 * should normally be true, except when writing to e.g. a FIFO.
287 * @return ERROR_OK on success, otherwise an error code.
288 */
289 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
290 uint32_t address, bool addrinc)
291 {
292 struct adiv5_dap *dap = ap->dap;
293 size_t nbytes = size * count;
294 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
295 uint32_t csw_size;
296 uint32_t addr_xor;
297 int retval;
298
299 /* TI BE-32 Quirks mode:
300 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
301 * size write address bytes written in order
302 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
303 * 2 TAR ^ 2 (val >> 8), (val)
304 * 1 TAR ^ 3 (val)
305 * For example, if you attempt to write a single byte to address 0, the processor
306 * will actually write a byte to address 3.
307 *
308 * To make writes of size < 4 work as expected, we xor a value with the address before
309 * setting the TAP, and we set the TAP after every transfer rather then relying on
310 * address increment. */
311
312 if (size == 4) {
313 csw_size = CSW_32BIT;
314 addr_xor = 0;
315 } else if (size == 2) {
316 csw_size = CSW_16BIT;
317 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
318 } else if (size == 1) {
319 csw_size = CSW_8BIT;
320 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
321 } else {
322 return ERROR_TARGET_UNALIGNED_ACCESS;
323 }
324
325 if (ap->unaligned_access_bad && (address % size != 0))
326 return ERROR_TARGET_UNALIGNED_ACCESS;
327
328 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
329 if (retval != ERROR_OK)
330 return retval;
331
332 while (nbytes > 0) {
333 uint32_t this_size = size;
334
335 /* Select packed transfer if possible */
336 if (addrinc && ap->packed_transfers && nbytes >= 4
337 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
338 this_size = 4;
339 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
340 } else {
341 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
342 }
343
344 if (retval != ERROR_OK)
345 break;
346
347 /* How many source bytes each transfer will consume, and their location in the DRW,
348 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
349 uint32_t outvalue = 0;
350 if (dap->ti_be_32_quirks) {
351 switch (this_size) {
352 case 4:
353 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
354 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
355 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
356 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
357 break;
358 case 2:
359 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
360 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
361 break;
362 case 1:
363 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
364 break;
365 }
366 } else {
367 switch (this_size) {
368 case 4:
369 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
370 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
371 case 2:
372 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
373 case 1:
374 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
375 }
376 }
377
378 nbytes -= this_size;
379
380 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
381 if (retval != ERROR_OK)
382 break;
383
384 /* Rewrite TAR if it wrapped or we're xoring addresses */
385 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
386 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
387 if (retval != ERROR_OK)
388 break;
389 }
390 }
391
392 /* REVISIT: Might want to have a queued version of this function that does not run. */
393 if (retval == ERROR_OK)
394 retval = dap_run(dap);
395
396 if (retval != ERROR_OK) {
397 uint32_t tar;
398 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
399 && dap_run(dap) == ERROR_OK)
400 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
401 else
402 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
403 }
404
405 return retval;
406 }
407
408 /**
409 * Synchronous read of a block of memory, using a specific access size.
410 *
411 * @param ap The MEM-AP to access.
412 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
413 * @param size Which access size to use, in bytes. 1, 2 or 4.
414 * @param count The number of reads to do (in size units, not bytes).
415 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
416 * @param addrinc Whether the target address should be increased after each read or not. This
417 * should normally be true, except when reading from e.g. a FIFO.
418 * @return ERROR_OK on success, otherwise an error code.
419 */
420 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
421 uint32_t adr, bool addrinc)
422 {
423 struct adiv5_dap *dap = ap->dap;
424 size_t nbytes = size * count;
425 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
426 uint32_t csw_size;
427 uint32_t address = adr;
428 int retval;
429
430 /* TI BE-32 Quirks mode:
431 * Reads on big-endian TMS570 behave strangely differently than writes.
432 * They read from the physical address requested, but with DRW byte-reversed.
433 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
434 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
435 * so avoid them. */
436
437 if (size == 4)
438 csw_size = CSW_32BIT;
439 else if (size == 2)
440 csw_size = CSW_16BIT;
441 else if (size == 1)
442 csw_size = CSW_8BIT;
443 else
444 return ERROR_TARGET_UNALIGNED_ACCESS;
445
446 if (ap->unaligned_access_bad && (adr % size != 0))
447 return ERROR_TARGET_UNALIGNED_ACCESS;
448
449 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
450 * over-allocation if packed transfers are going to be used, but determining the real need at
451 * this point would be messy. */
452 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
453 uint32_t *read_ptr = read_buf;
454 if (read_buf == NULL) {
455 LOG_ERROR("Failed to allocate read buffer");
456 return ERROR_FAIL;
457 }
458
459 retval = mem_ap_setup_tar(ap, address);
460 if (retval != ERROR_OK) {
461 free(read_buf);
462 return retval;
463 }
464
465 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
466 * useful bytes it contains, and their location in the word, depends on the type of transfer
467 * and alignment. */
468 while (nbytes > 0) {
469 uint32_t this_size = size;
470
471 /* Select packed transfer if possible */
472 if (addrinc && ap->packed_transfers && nbytes >= 4
473 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
474 this_size = 4;
475 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
476 } else {
477 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
478 }
479 if (retval != ERROR_OK)
480 break;
481
482 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
483 if (retval != ERROR_OK)
484 break;
485
486 nbytes -= this_size;
487 address += this_size;
488
489 /* Rewrite TAR if it wrapped */
490 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
491 retval = mem_ap_setup_tar(ap, address);
492 if (retval != ERROR_OK)
493 break;
494 }
495 }
496
497 if (retval == ERROR_OK)
498 retval = dap_run(dap);
499
500 /* Restore state */
501 address = adr;
502 nbytes = size * count;
503 read_ptr = read_buf;
504
505 /* If something failed, read TAR to find out how much data was successfully read, so we can
506 * at least give the caller what we have. */
507 if (retval != ERROR_OK) {
508 uint32_t tar;
509 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
510 && dap_run(dap) == ERROR_OK) {
511 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
512 if (nbytes > tar - address)
513 nbytes = tar - address;
514 } else {
515 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
516 nbytes = 0;
517 }
518 }
519
520 /* Replay loop to populate caller's buffer from the correct word and byte lane */
521 while (nbytes > 0) {
522 uint32_t this_size = size;
523
524 if (addrinc && ap->packed_transfers && nbytes >= 4
525 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
526 this_size = 4;
527 }
528
529 if (dap->ti_be_32_quirks) {
530 switch (this_size) {
531 case 4:
532 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
533 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
534 case 2:
535 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
536 case 1:
537 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
538 }
539 } else {
540 switch (this_size) {
541 case 4:
542 *buffer++ = *read_ptr >> 8 * (address++ & 3);
543 *buffer++ = *read_ptr >> 8 * (address++ & 3);
544 case 2:
545 *buffer++ = *read_ptr >> 8 * (address++ & 3);
546 case 1:
547 *buffer++ = *read_ptr >> 8 * (address++ & 3);
548 }
549 }
550
551 read_ptr++;
552 nbytes -= this_size;
553 }
554
555 free(read_buf);
556 return retval;
557 }
558
559 int mem_ap_read_buf(struct adiv5_ap *ap,
560 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
561 {
562 return mem_ap_read(ap, buffer, size, count, address, true);
563 }
564
565 int mem_ap_write_buf(struct adiv5_ap *ap,
566 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
567 {
568 return mem_ap_write(ap, buffer, size, count, address, true);
569 }
570
571 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
572 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
573 {
574 return mem_ap_read(ap, buffer, size, count, address, false);
575 }
576
577 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
578 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
579 {
580 return mem_ap_write(ap, buffer, size, count, address, false);
581 }
582
583 /*--------------------------------------------------------------------------*/
584
585
586 #define DAP_POWER_DOMAIN_TIMEOUT (10)
587
588 /* FIXME don't import ... just initialize as
589 * part of DAP transport setup
590 */
591 extern const struct dap_ops jtag_dp_ops;
592
593 /*--------------------------------------------------------------------------*/
594
595 /**
596 * Create a new DAP
597 */
598 struct adiv5_dap *dap_init(void)
599 {
600 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
601 int i;
602 /* Set up with safe defaults */
603 for (i = 0; i <= 255; i++) {
604 dap->ap[i].dap = dap;
605 dap->ap[i].ap_num = i;
606 /* memaccess_tck max is 255 */
607 dap->ap[i].memaccess_tck = 255;
608 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
609 dap->ap[i].tar_autoincr_block = (1<<10);
610 }
611 dap->ap_current = -1;
612 dap->ap_bank_value = -1;
613 dap->dp_bank_value = -1;
614 return dap;
615 }
616
617 /**
618 * Initialize a DAP. This sets up the power domains, prepares the DP
619 * for further use and activates overrun checking.
620 *
621 * @param dap The DAP being initialized.
622 */
623 int dap_dp_init(struct adiv5_dap *dap)
624 {
625 int retval;
626
627 LOG_DEBUG(" ");
628 /* JTAG-DP or SWJ-DP, in JTAG mode
629 * ... for SWD mode this is patched as part
630 * of link switchover
631 * FIXME: This should already be setup by the respective transport specific DAP creation.
632 */
633 if (!dap->ops)
634 dap->ops = &jtag_dp_ops;
635
636 dap->ap_current = -1;
637 dap->ap_bank_value = -1;
638 dap->last_read = NULL;
639
640 for (size_t i = 0; i < 10; i++) {
641 /* DP initialization */
642
643 dap->dp_bank_value = 0;
644
645 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
646 if (retval != ERROR_OK)
647 continue;
648
649 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
650 if (retval != ERROR_OK)
651 continue;
652
653 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
654 if (retval != ERROR_OK)
655 continue;
656
657 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
658 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
659 if (retval != ERROR_OK)
660 continue;
661
662 /* Check that we have debug power domains activated */
663 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
664 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
665 CDBGPWRUPACK, CDBGPWRUPACK,
666 DAP_POWER_DOMAIN_TIMEOUT);
667 if (retval != ERROR_OK)
668 continue;
669
670 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
671 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
672 CSYSPWRUPACK, CSYSPWRUPACK,
673 DAP_POWER_DOMAIN_TIMEOUT);
674 if (retval != ERROR_OK)
675 continue;
676
677 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
678 if (retval != ERROR_OK)
679 continue;
680
681 /* With debug power on we can activate OVERRUN checking */
682 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
683 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
684 if (retval != ERROR_OK)
685 continue;
686 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
687 if (retval != ERROR_OK)
688 continue;
689
690 retval = dap_run(dap);
691 if (retval != ERROR_OK)
692 continue;
693
694 break;
695 }
696
697 return retval;
698 }
699
700 /**
701 * Initialize a DAP. This sets up the power domains, prepares the DP
702 * for further use, and arranges to use AP #0 for all AP operations
703 * until dap_ap-select() changes that policy.
704 *
705 * @param ap The MEM-AP being initialized.
706 */
707 int mem_ap_init(struct adiv5_ap *ap)
708 {
709 /* check that we support packed transfers */
710 uint32_t csw, cfg;
711 int retval;
712 struct adiv5_dap *dap = ap->dap;
713
714 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
715 if (retval != ERROR_OK)
716 return retval;
717
718 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
719 if (retval != ERROR_OK)
720 return retval;
721
722 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
723 if (retval != ERROR_OK)
724 return retval;
725
726 retval = dap_run(dap);
727 if (retval != ERROR_OK)
728 return retval;
729
730 if (csw & CSW_ADDRINC_PACKED)
731 ap->packed_transfers = true;
732 else
733 ap->packed_transfers = false;
734
735 /* Packed transfers on TI BE-32 processors do not work correctly in
736 * many cases. */
737 if (dap->ti_be_32_quirks)
738 ap->packed_transfers = false;
739
740 LOG_DEBUG("MEM_AP Packed Transfers: %s",
741 ap->packed_transfers ? "enabled" : "disabled");
742
743 /* The ARM ADI spec leaves implementation-defined whether unaligned
744 * memory accesses work, only work partially, or cause a sticky error.
745 * On TI BE-32 processors, reads seem to return garbage in some bytes
746 * and unaligned writes seem to cause a sticky error.
747 * TODO: it would be nice to have a way to detect whether unaligned
748 * operations are supported on other processors. */
749 ap->unaligned_access_bad = dap->ti_be_32_quirks;
750
751 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
752 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
753
754 return ERROR_OK;
755 }
756
757 /* CID interpretation -- see ARM IHI 0029B section 3
758 * and ARM IHI 0031A table 13-3.
759 */
760 static const char *class_description[16] = {
761 "Reserved", "ROM table", "Reserved", "Reserved",
762 "Reserved", "Reserved", "Reserved", "Reserved",
763 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
764 "Reserved", "OptimoDE DESS",
765 "Generic IP component", "PrimeCell or System component"
766 };
767
768 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
769 {
770 return cid3 == 0xb1 && cid2 == 0x05
771 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
772 }
773
774 /*
775 * This function checks the ID for each access port to find the requested Access Port type
776 */
777 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
778 {
779 int ap_num;
780
781 /* Maximum AP number is 255 since the SELECT register is 8 bits */
782 for (ap_num = 0; ap_num <= 255; ap_num++) {
783
784 /* read the IDR register of the Access Port */
785 uint32_t id_val = 0;
786
787 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
788 if (retval != ERROR_OK)
789 return retval;
790
791 retval = dap_run(dap);
792
793 /* IDR bits:
794 * 31-28 : Revision
795 * 27-24 : JEDEC bank (0x4 for ARM)
796 * 23-17 : JEDEC code (0x3B for ARM)
797 * 16-13 : Class (0b1000=Mem-AP)
798 * 12-8 : Reserved
799 * 7-4 : AP Variant (non-zero for JTAG-AP)
800 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
801 */
802
803 /* Reading register for a non-existant AP should not cause an error,
804 * but just to be sure, try to continue searching if an error does happen.
805 */
806 if ((retval == ERROR_OK) && /* Register read success */
807 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
808 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
809
810 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
811 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
812 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
813 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
814 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
815 ap_num, id_val);
816
817 *ap_out = &dap->ap[ap_num];
818 return ERROR_OK;
819 }
820 }
821
822 LOG_DEBUG("No %s found",
823 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
824 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
825 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
826 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
827 return ERROR_FAIL;
828 }
829
830 int dap_get_debugbase(struct adiv5_ap *ap,
831 uint32_t *dbgbase, uint32_t *apid)
832 {
833 struct adiv5_dap *dap = ap->dap;
834 int retval;
835
836 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
837 if (retval != ERROR_OK)
838 return retval;
839 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
840 if (retval != ERROR_OK)
841 return retval;
842 retval = dap_run(dap);
843 if (retval != ERROR_OK)
844 return retval;
845
846 return ERROR_OK;
847 }
848
849 int dap_lookup_cs_component(struct adiv5_ap *ap,
850 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
851 {
852 uint32_t romentry, entry_offset = 0, component_base, devtype;
853 int retval;
854
855 *addr = 0;
856
857 do {
858 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
859 entry_offset, &romentry);
860 if (retval != ERROR_OK)
861 return retval;
862
863 component_base = (dbgbase & 0xFFFFF000)
864 + (romentry & 0xFFFFF000);
865
866 if (romentry & 0x1) {
867 uint32_t c_cid1;
868 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
869 if (retval != ERROR_OK) {
870 LOG_ERROR("Can't read component with base address 0x%" PRIx32
871 ", the corresponding core might be turned off", component_base);
872 return retval;
873 }
874 if (((c_cid1 >> 4) & 0x0f) == 1) {
875 retval = dap_lookup_cs_component(ap, component_base,
876 type, addr, idx);
877 if (retval == ERROR_OK)
878 break;
879 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
880 return retval;
881 }
882
883 retval = mem_ap_read_atomic_u32(ap,
884 (component_base & 0xfffff000) | 0xfcc,
885 &devtype);
886 if (retval != ERROR_OK)
887 return retval;
888 if ((devtype & 0xff) == type) {
889 if (!*idx) {
890 *addr = component_base;
891 break;
892 } else
893 (*idx)--;
894 }
895 }
896 entry_offset += 4;
897 } while (romentry > 0);
898
899 if (!*addr)
900 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
901
902 return ERROR_OK;
903 }
904
905 static int dap_rom_display(struct command_context *cmd_ctx,
906 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
907 {
908 struct adiv5_dap *dap = ap->dap;
909 int retval;
910 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
911 uint16_t entry_offset;
912 char tabs[7] = "";
913
914 if (depth > 16) {
915 command_print(cmd_ctx, "\tTables too deep");
916 return ERROR_FAIL;
917 }
918
919 if (depth)
920 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
921
922 /* bit 16 of apid indicates a memory access port */
923 if (dbgbase & 0x02)
924 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
925 else
926 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
927
928 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
929 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
930 if (retval != ERROR_OK)
931 return retval;
932 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
933 if (retval != ERROR_OK)
934 return retval;
935 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
936 if (retval != ERROR_OK)
937 return retval;
938 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
939 if (retval != ERROR_OK)
940 return retval;
941 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
942 if (retval != ERROR_OK)
943 return retval;
944 retval = dap_run(dap);
945 if (retval != ERROR_OK)
946 return retval;
947
948 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
949 command_print(cmd_ctx, "\t%sCID3 0x%02x"
950 ", CID2 0x%02x"
951 ", CID1 0x%02x"
952 ", CID0 0x%02x",
953 tabs,
954 (unsigned)cid3, (unsigned)cid2,
955 (unsigned)cid1, (unsigned)cid0);
956 if (memtype & 0x01)
957 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
958 else
959 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
960
961 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
962 for (entry_offset = 0; ; entry_offset += 4) {
963 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
964 if (retval != ERROR_OK)
965 return retval;
966 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
967 tabs, entry_offset, romentry);
968 if (romentry & 0x01) {
969 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
970 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
971 uint32_t component_base;
972 uint32_t part_num;
973 const char *type, *full;
974
975 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
976
977 /* IDs are in last 4K section */
978 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
979 if (retval != ERROR_OK) {
980 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
981 ", the corresponding core might be turned off", tabs, component_base);
982 continue;
983 }
984 c_pid0 &= 0xff;
985 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
986 if (retval != ERROR_OK)
987 return retval;
988 c_pid1 &= 0xff;
989 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
990 if (retval != ERROR_OK)
991 return retval;
992 c_pid2 &= 0xff;
993 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
994 if (retval != ERROR_OK)
995 return retval;
996 c_pid3 &= 0xff;
997 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
998 if (retval != ERROR_OK)
999 return retval;
1000 c_pid4 &= 0xff;
1001
1002 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
1003 if (retval != ERROR_OK)
1004 return retval;
1005 c_cid0 &= 0xff;
1006 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
1007 if (retval != ERROR_OK)
1008 return retval;
1009 c_cid1 &= 0xff;
1010 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
1011 if (retval != ERROR_OK)
1012 return retval;
1013 c_cid2 &= 0xff;
1014 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
1015 if (retval != ERROR_OK)
1016 return retval;
1017 c_cid3 &= 0xff;
1018
1019 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1020 "start address 0x%" PRIx32, component_base,
1021 /* component may take multiple 4K pages */
1022 (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1023 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1024 (uint8_t)((c_cid1 >> 4) & 0xf),
1025 /* See ARM IHI 0029B Table 3-3 */
1026 class_description[(c_cid1 >> 4) & 0xf]);
1027
1028 /* CoreSight component? */
1029 if (((c_cid1 >> 4) & 0x0f) == 9) {
1030 uint32_t devtype;
1031 unsigned minor;
1032 const char *major = "Reserved", *subtype = "Reserved";
1033
1034 retval = mem_ap_read_atomic_u32(ap,
1035 (component_base & 0xfffff000) | 0xfcc,
1036 &devtype);
1037 if (retval != ERROR_OK)
1038 return retval;
1039 minor = (devtype >> 4) & 0x0f;
1040 switch (devtype & 0x0f) {
1041 case 0:
1042 major = "Miscellaneous";
1043 switch (minor) {
1044 case 0:
1045 subtype = "other";
1046 break;
1047 case 4:
1048 subtype = "Validation component";
1049 break;
1050 }
1051 break;
1052 case 1:
1053 major = "Trace Sink";
1054 switch (minor) {
1055 case 0:
1056 subtype = "other";
1057 break;
1058 case 1:
1059 subtype = "Port";
1060 break;
1061 case 2:
1062 subtype = "Buffer";
1063 break;
1064 case 3:
1065 subtype = "Router";
1066 break;
1067 }
1068 break;
1069 case 2:
1070 major = "Trace Link";
1071 switch (minor) {
1072 case 0:
1073 subtype = "other";
1074 break;
1075 case 1:
1076 subtype = "Funnel, router";
1077 break;
1078 case 2:
1079 subtype = "Filter";
1080 break;
1081 case 3:
1082 subtype = "FIFO, buffer";
1083 break;
1084 }
1085 break;
1086 case 3:
1087 major = "Trace Source";
1088 switch (minor) {
1089 case 0:
1090 subtype = "other";
1091 break;
1092 case 1:
1093 subtype = "Processor";
1094 break;
1095 case 2:
1096 subtype = "DSP";
1097 break;
1098 case 3:
1099 subtype = "Engine/Coprocessor";
1100 break;
1101 case 4:
1102 subtype = "Bus";
1103 break;
1104 case 6:
1105 subtype = "Software";
1106 break;
1107 }
1108 break;
1109 case 4:
1110 major = "Debug Control";
1111 switch (minor) {
1112 case 0:
1113 subtype = "other";
1114 break;
1115 case 1:
1116 subtype = "Trigger Matrix";
1117 break;
1118 case 2:
1119 subtype = "Debug Auth";
1120 break;
1121 case 3:
1122 subtype = "Power Requestor";
1123 break;
1124 }
1125 break;
1126 case 5:
1127 major = "Debug Logic";
1128 switch (minor) {
1129 case 0:
1130 subtype = "other";
1131 break;
1132 case 1:
1133 subtype = "Processor";
1134 break;
1135 case 2:
1136 subtype = "DSP";
1137 break;
1138 case 3:
1139 subtype = "Engine/Coprocessor";
1140 break;
1141 case 4:
1142 subtype = "Bus";
1143 break;
1144 case 5:
1145 subtype = "Memory";
1146 break;
1147 }
1148 break;
1149 case 6:
1150 major = "Perfomance Monitor";
1151 switch (minor) {
1152 case 0:
1153 subtype = "other";
1154 break;
1155 case 1:
1156 subtype = "Processor";
1157 break;
1158 case 2:
1159 subtype = "DSP";
1160 break;
1161 case 3:
1162 subtype = "Engine/Coprocessor";
1163 break;
1164 case 4:
1165 subtype = "Bus";
1166 break;
1167 case 5:
1168 subtype = "Memory";
1169 break;
1170 }
1171 break;
1172 }
1173 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1174 (uint8_t)(devtype & 0xff),
1175 major, subtype);
1176 /* REVISIT also show 0xfc8 DevId */
1177 }
1178
1179 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1180 command_print(cmd_ctx,
1181 "\t\tCID3 0%02x"
1182 ", CID2 0%02x"
1183 ", CID1 0%02x"
1184 ", CID0 0%02x",
1185 (int)c_cid3,
1186 (int)c_cid2,
1187 (int)c_cid1,
1188 (int)c_cid0);
1189 command_print(cmd_ctx,
1190 "\t\tPeripheral ID[4..0] = hex "
1191 "%02x %02x %02x %02x %02x",
1192 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1193 (int)c_pid1, (int)c_pid0);
1194
1195 /* Part number interpretations are from Cortex
1196 * core specs, the CoreSight components TRM
1197 * (ARM DDI 0314H), CoreSight System Design
1198 * Guide (ARM DGI 0012D) and ETM specs; also
1199 * from chip observation (e.g. TI SDTI).
1200 */
1201 part_num = (c_pid0 & 0xff);
1202 part_num |= (c_pid1 & 0x0f) << 8;
1203 switch (part_num) {
1204 case 0x000:
1205 type = "Cortex-M3 NVIC";
1206 full = "(Interrupt Controller)";
1207 break;
1208 case 0x001:
1209 type = "Cortex-M3 ITM";
1210 full = "(Instrumentation Trace Module)";
1211 break;
1212 case 0x002:
1213 type = "Cortex-M3 DWT";
1214 full = "(Data Watchpoint and Trace)";
1215 break;
1216 case 0x003:
1217 type = "Cortex-M3 FBP";
1218 full = "(Flash Patch and Breakpoint)";
1219 break;
1220 case 0x008:
1221 type = "Cortex-M0 SCS";
1222 full = "(System Control Space)";
1223 break;
1224 case 0x00a:
1225 type = "Cortex-M0 DWT";
1226 full = "(Data Watchpoint and Trace)";
1227 break;
1228 case 0x00b:
1229 type = "Cortex-M0 BPU";
1230 full = "(Breakpoint Unit)";
1231 break;
1232 case 0x00c:
1233 type = "Cortex-M4 SCS";
1234 full = "(System Control Space)";
1235 break;
1236 case 0x00d:
1237 type = "CoreSight ETM11";
1238 full = "(Embedded Trace)";
1239 break;
1240 /* case 0x113: what? */
1241 case 0x120: /* from OMAP3 memmap */
1242 type = "TI SDTI";
1243 full = "(System Debug Trace Interface)";
1244 break;
1245 case 0x343: /* from OMAP3 memmap */
1246 type = "TI DAPCTL";
1247 full = "";
1248 break;
1249 case 0x906:
1250 type = "Coresight CTI";
1251 full = "(Cross Trigger)";
1252 break;
1253 case 0x907:
1254 type = "Coresight ETB";
1255 full = "(Trace Buffer)";
1256 break;
1257 case 0x908:
1258 type = "Coresight CSTF";
1259 full = "(Trace Funnel)";
1260 break;
1261 case 0x910:
1262 type = "CoreSight ETM9";
1263 full = "(Embedded Trace)";
1264 break;
1265 case 0x912:
1266 type = "Coresight TPIU";
1267 full = "(Trace Port Interface Unit)";
1268 break;
1269 case 0x913:
1270 type = "Coresight ITM";
1271 full = "(Instrumentation Trace Macrocell)";
1272 break;
1273 case 0x914:
1274 type = "Coresight SWO";
1275 full = "(Single Wire Output)";
1276 break;
1277 case 0x917:
1278 type = "Coresight HTM";
1279 full = "(AHB Trace Macrocell)";
1280 break;
1281 case 0x920:
1282 type = "CoreSight ETM11";
1283 full = "(Embedded Trace)";
1284 break;
1285 case 0x921:
1286 type = "Cortex-A8 ETM";
1287 full = "(Embedded Trace)";
1288 break;
1289 case 0x922:
1290 type = "Cortex-A8 CTI";
1291 full = "(Cross Trigger)";
1292 break;
1293 case 0x923:
1294 type = "Cortex-M3 TPIU";
1295 full = "(Trace Port Interface Unit)";
1296 break;
1297 case 0x924:
1298 type = "Cortex-M3 ETM";
1299 full = "(Embedded Trace)";
1300 break;
1301 case 0x925:
1302 type = "Cortex-M4 ETM";
1303 full = "(Embedded Trace)";
1304 break;
1305 case 0x930:
1306 type = "Cortex-R4 ETM";
1307 full = "(Embedded Trace)";
1308 break;
1309 case 0x950:
1310 type = "CoreSight Component";
1311 full = "(unidentified Cortex-A9 component)";
1312 break;
1313 case 0x961:
1314 type = "CoreSight TMC";
1315 full = "(Trace Memory Controller)";
1316 break;
1317 case 0x962:
1318 type = "CoreSight STM";
1319 full = "(System Trace Macrocell)";
1320 break;
1321 case 0x9a0:
1322 type = "CoreSight PMU";
1323 full = "(Performance Monitoring Unit)";
1324 break;
1325 case 0x9a1:
1326 type = "Cortex-M4 TPUI";
1327 full = "(Trace Port Interface Unit)";
1328 break;
1329 case 0x9a5:
1330 type = "Cortex-A5 ETM";
1331 full = "(Embedded Trace)";
1332 break;
1333 case 0xc05:
1334 type = "Cortex-A5 Debug";
1335 full = "(Debug Unit)";
1336 break;
1337 case 0xc08:
1338 type = "Cortex-A8 Debug";
1339 full = "(Debug Unit)";
1340 break;
1341 case 0xc09:
1342 type = "Cortex-A9 Debug";
1343 full = "(Debug Unit)";
1344 break;
1345 case 0x4af:
1346 type = "Cortex-A15 Debug";
1347 full = "(Debug Unit)";
1348 break;
1349 default:
1350 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
1351 type = "-*- unrecognized -*-";
1352 full = "";
1353 break;
1354 }
1355 command_print(cmd_ctx, "\t\tPart is %s %s",
1356 type, full);
1357
1358 /* ROM Table? */
1359 if (((c_cid1 >> 4) & 0x0f) == 1) {
1360 retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
1361 if (retval != ERROR_OK)
1362 return retval;
1363 }
1364 } else {
1365 if (romentry)
1366 command_print(cmd_ctx, "\t\tComponent not present");
1367 else
1368 break;
1369 }
1370 }
1371 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1372 return ERROR_OK;
1373 }
1374
1375 static int dap_info_command(struct command_context *cmd_ctx,
1376 struct adiv5_ap *ap)
1377 {
1378 int retval;
1379 uint32_t dbgbase, apid;
1380 int romtable_present = 0;
1381 uint8_t mem_ap;
1382
1383 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1384 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1385 if (retval != ERROR_OK)
1386 return retval;
1387
1388 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1389 if (apid == 0) {
1390 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1391 return ERROR_FAIL;
1392 }
1393
1394 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1395 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1396 command_print(cmd_ctx, "\tType is JTAG-AP");
1397 break;
1398 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1399 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1400 break;
1401 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1402 command_print(cmd_ctx, "\tType is MEM-AP APB");
1403 break;
1404 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1405 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1406 break;
1407 default:
1408 command_print(cmd_ctx, "\tUnknown AP type");
1409 break;
1410 }
1411
1412 /* NOTE: a MEM-AP may have a single CoreSight component that's
1413 * not a ROM table ... or have no such components at all.
1414 */
1415 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1416 if (mem_ap) {
1417 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1418
1419 romtable_present = dbgbase != 0xFFFFFFFF;
1420 if (romtable_present)
1421 dap_rom_display(cmd_ctx, ap, dbgbase, 0);
1422 else
1423 command_print(cmd_ctx, "\tNo ROM table present");
1424 }
1425
1426 return ERROR_OK;
1427 }
1428
1429 COMMAND_HANDLER(handle_dap_info_command)
1430 {
1431 struct target *target = get_current_target(CMD_CTX);
1432 struct arm *arm = target_to_arm(target);
1433 struct adiv5_dap *dap = arm->dap;
1434 uint32_t apsel;
1435
1436 switch (CMD_ARGC) {
1437 case 0:
1438 apsel = dap->apsel;
1439 break;
1440 case 1:
1441 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1442 if (apsel >= 256)
1443 return ERROR_COMMAND_SYNTAX_ERROR;
1444 break;
1445 default:
1446 return ERROR_COMMAND_SYNTAX_ERROR;
1447 }
1448
1449 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1450 }
1451
1452 COMMAND_HANDLER(dap_baseaddr_command)
1453 {
1454 struct target *target = get_current_target(CMD_CTX);
1455 struct arm *arm = target_to_arm(target);
1456 struct adiv5_dap *dap = arm->dap;
1457
1458 uint32_t apsel, baseaddr;
1459 int retval;
1460
1461 switch (CMD_ARGC) {
1462 case 0:
1463 apsel = dap->apsel;
1464 break;
1465 case 1:
1466 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1467 /* AP address is in bits 31:24 of DP_SELECT */
1468 if (apsel >= 256)
1469 return ERROR_COMMAND_SYNTAX_ERROR;
1470 break;
1471 default:
1472 return ERROR_COMMAND_SYNTAX_ERROR;
1473 }
1474
1475 /* NOTE: assumes we're talking to a MEM-AP, which
1476 * has a base address. There are other kinds of AP,
1477 * though they're not common for now. This should
1478 * use the ID register to verify it's a MEM-AP.
1479 */
1480 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1481 if (retval != ERROR_OK)
1482 return retval;
1483 retval = dap_run(dap);
1484 if (retval != ERROR_OK)
1485 return retval;
1486
1487 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1488
1489 return retval;
1490 }
1491
1492 COMMAND_HANDLER(dap_memaccess_command)
1493 {
1494 struct target *target = get_current_target(CMD_CTX);
1495 struct arm *arm = target_to_arm(target);
1496 struct adiv5_dap *dap = arm->dap;
1497
1498 uint32_t memaccess_tck;
1499
1500 switch (CMD_ARGC) {
1501 case 0:
1502 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1503 break;
1504 case 1:
1505 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1506 break;
1507 default:
1508 return ERROR_COMMAND_SYNTAX_ERROR;
1509 }
1510 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1511
1512 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1513 dap->ap[dap->apsel].memaccess_tck);
1514
1515 return ERROR_OK;
1516 }
1517
1518 COMMAND_HANDLER(dap_apsel_command)
1519 {
1520 struct target *target = get_current_target(CMD_CTX);
1521 struct arm *arm = target_to_arm(target);
1522 struct adiv5_dap *dap = arm->dap;
1523
1524 uint32_t apsel, apid;
1525 int retval;
1526
1527 switch (CMD_ARGC) {
1528 case 0:
1529 apsel = dap->apsel;
1530 break;
1531 case 1:
1532 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1533 /* AP address is in bits 31:24 of DP_SELECT */
1534 if (apsel >= 256)
1535 return ERROR_COMMAND_SYNTAX_ERROR;
1536 break;
1537 default:
1538 return ERROR_COMMAND_SYNTAX_ERROR;
1539 }
1540
1541 dap->apsel = apsel;
1542
1543 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1544 if (retval != ERROR_OK)
1545 return retval;
1546 retval = dap_run(dap);
1547 if (retval != ERROR_OK)
1548 return retval;
1549
1550 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1551 apsel, apid);
1552
1553 return retval;
1554 }
1555
1556 COMMAND_HANDLER(dap_apcsw_command)
1557 {
1558 struct target *target = get_current_target(CMD_CTX);
1559 struct arm *arm = target_to_arm(target);
1560 struct adiv5_dap *dap = arm->dap;
1561
1562 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1563
1564 switch (CMD_ARGC) {
1565 case 0:
1566 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1567 (dap->apsel), apcsw);
1568 break;
1569 case 1:
1570 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1571 /* AP address is in bits 31:24 of DP_SELECT */
1572 if (sprot > 1)
1573 return ERROR_COMMAND_SYNTAX_ERROR;
1574 if (sprot)
1575 apcsw |= CSW_SPROT;
1576 else
1577 apcsw &= ~CSW_SPROT;
1578 break;
1579 default:
1580 return ERROR_COMMAND_SYNTAX_ERROR;
1581 }
1582 dap->ap[dap->apsel].csw_default = apcsw;
1583
1584 return 0;
1585 }
1586
1587
1588
1589 COMMAND_HANDLER(dap_apid_command)
1590 {
1591 struct target *target = get_current_target(CMD_CTX);
1592 struct arm *arm = target_to_arm(target);
1593 struct adiv5_dap *dap = arm->dap;
1594
1595 uint32_t apsel, apid;
1596 int retval;
1597
1598 switch (CMD_ARGC) {
1599 case 0:
1600 apsel = dap->apsel;
1601 break;
1602 case 1:
1603 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1604 /* AP address is in bits 31:24 of DP_SELECT */
1605 if (apsel >= 256)
1606 return ERROR_COMMAND_SYNTAX_ERROR;
1607 break;
1608 default:
1609 return ERROR_COMMAND_SYNTAX_ERROR;
1610 }
1611
1612 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1613 if (retval != ERROR_OK)
1614 return retval;
1615 retval = dap_run(dap);
1616 if (retval != ERROR_OK)
1617 return retval;
1618
1619 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1620
1621 return retval;
1622 }
1623
1624 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1625 {
1626 struct target *target = get_current_target(CMD_CTX);
1627 struct arm *arm = target_to_arm(target);
1628 struct adiv5_dap *dap = arm->dap;
1629
1630 uint32_t enable = dap->ti_be_32_quirks;
1631
1632 switch (CMD_ARGC) {
1633 case 0:
1634 break;
1635 case 1:
1636 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1637 if (enable > 1)
1638 return ERROR_COMMAND_SYNTAX_ERROR;
1639 break;
1640 default:
1641 return ERROR_COMMAND_SYNTAX_ERROR;
1642 }
1643 dap->ti_be_32_quirks = enable;
1644 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1645 enable ? "enabled" : "disabled");
1646
1647 return 0;
1648 }
1649
1650 static const struct command_registration dap_commands[] = {
1651 {
1652 .name = "info",
1653 .handler = handle_dap_info_command,
1654 .mode = COMMAND_EXEC,
1655 .help = "display ROM table for MEM-AP "
1656 "(default currently selected AP)",
1657 .usage = "[ap_num]",
1658 },
1659 {
1660 .name = "apsel",
1661 .handler = dap_apsel_command,
1662 .mode = COMMAND_EXEC,
1663 .help = "Set the currently selected AP (default 0) "
1664 "and display the result",
1665 .usage = "[ap_num]",
1666 },
1667 {
1668 .name = "apcsw",
1669 .handler = dap_apcsw_command,
1670 .mode = COMMAND_EXEC,
1671 .help = "Set csw access bit ",
1672 .usage = "[sprot]",
1673 },
1674
1675 {
1676 .name = "apid",
1677 .handler = dap_apid_command,
1678 .mode = COMMAND_EXEC,
1679 .help = "return ID register from AP "
1680 "(default currently selected AP)",
1681 .usage = "[ap_num]",
1682 },
1683 {
1684 .name = "baseaddr",
1685 .handler = dap_baseaddr_command,
1686 .mode = COMMAND_EXEC,
1687 .help = "return debug base address from MEM-AP "
1688 "(default currently selected AP)",
1689 .usage = "[ap_num]",
1690 },
1691 {
1692 .name = "memaccess",
1693 .handler = dap_memaccess_command,
1694 .mode = COMMAND_EXEC,
1695 .help = "set/get number of extra tck for MEM-AP memory "
1696 "bus access [0-255]",
1697 .usage = "[cycles]",
1698 },
1699 {
1700 .name = "ti_be_32_quirks",
1701 .handler = dap_ti_be_32_quirks_command,
1702 .mode = COMMAND_CONFIG,
1703 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1704 .usage = "[enable]",
1705 },
1706 COMMAND_REGISTRATION_DONE
1707 };
1708
1709 const struct command_registration dap_command_handlers[] = {
1710 {
1711 .name = "dap",
1712 .mode = COMMAND_EXEC,
1713 .help = "DAP command group",
1714 .usage = "",
1715 .chain = dap_commands,
1716 },
1717 COMMAND_REGISTRATION_DONE
1718 };