e2d9b5e66873f2980f8aabbb44e6b15fe2b01555
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
29
30 /**
31 * @file
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
37 *
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 *
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
57 */
58
59 /*
60 * Relevant specifications from ARM include:
61 *
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 *
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 */
68
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
79 #include <helper/jim-nvp.h>
80
81 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
82
83 /*
84 uint32_t tar_block_size(uint32_t address)
85 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 */
87 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 {
89 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
90 }
91
92 /***************************************************************************
93 * *
94 * DP and MEM-AP register access through APACC and DPACC *
95 * *
96 ***************************************************************************/
97
98 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 {
100 csw |= ap->csw_default;
101
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK)
106 return retval;
107 ap->csw_value = csw;
108 }
109 return ERROR_OK;
110 }
111
112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
113 {
114 if (!ap->tar_valid || tar != ap->tar_value) {
115 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
116 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
117 if (retval != ERROR_OK)
118 return retval;
119 ap->tar_value = tar;
120 ap->tar_valid = true;
121 }
122 return ERROR_OK;
123 }
124
125 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
126 {
127 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
128 if (retval != ERROR_OK) {
129 ap->tar_valid = false;
130 return retval;
131 }
132
133 retval = dap_run(ap->dap);
134 if (retval != ERROR_OK) {
135 ap->tar_valid = false;
136 return retval;
137 }
138
139 ap->tar_value = *tar;
140 ap->tar_valid = true;
141 return ERROR_OK;
142 }
143
144 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
145 {
146 switch (ap->csw_value & CSW_ADDRINC_MASK) {
147 case CSW_ADDRINC_SINGLE:
148 switch (ap->csw_value & CSW_SIZE_MASK) {
149 case CSW_8BIT:
150 return 1;
151 case CSW_16BIT:
152 return 2;
153 case CSW_32BIT:
154 return 4;
155 }
156 case CSW_ADDRINC_PACKED:
157 return 4;
158 }
159 return 0;
160 }
161
162 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
163 */
164 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
165 {
166 if (!ap->tar_valid)
167 return;
168
169 uint32_t inc = mem_ap_get_tar_increment(ap);
170 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
171 ap->tar_valid = false;
172 else
173 ap->tar_value += inc;
174 }
175
176 /**
177 * Queue transactions setting up transfer parameters for the
178 * currently selected MEM-AP.
179 *
180 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
181 * initiate data reads or writes using memory or peripheral addresses.
182 * If the CSW is configured for it, the TAR may be automatically
183 * incremented after each transfer.
184 *
185 * @param ap The MEM-AP.
186 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
187 * matches the cached value, the register is not changed.
188 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
189 * matches the cached address, the register is not changed.
190 *
191 * @return ERROR_OK if the transaction was properly queued, else a fault code.
192 */
193 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
194 {
195 int retval;
196 retval = mem_ap_setup_csw(ap, csw);
197 if (retval != ERROR_OK)
198 return retval;
199 retval = mem_ap_setup_tar(ap, tar);
200 if (retval != ERROR_OK)
201 return retval;
202 return ERROR_OK;
203 }
204
205 /**
206 * Asynchronous (queued) read of a word from memory or a system register.
207 *
208 * @param ap The MEM-AP to access.
209 * @param address Address of the 32-bit word to read; it must be
210 * readable by the currently selected MEM-AP.
211 * @param value points to where the word will be stored when the
212 * transaction queue is flushed (assuming no errors).
213 *
214 * @return ERROR_OK for success. Otherwise a fault code.
215 */
216 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
217 uint32_t *value)
218 {
219 int retval;
220
221 /* Use banked addressing (REG_BDx) to avoid some link traffic
222 * (updating TAR) when reading several consecutive addresses.
223 */
224 retval = mem_ap_setup_transfer(ap,
225 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
226 address & 0xFFFFFFF0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
231 }
232
233 /**
234 * Synchronous read of a word from memory or a system register.
235 * As a side effect, this flushes any queued transactions.
236 *
237 * @param ap The MEM-AP to access.
238 * @param address Address of the 32-bit word to read; it must be
239 * readable by the currently selected MEM-AP.
240 * @param value points to where the result will be stored.
241 *
242 * @return ERROR_OK for success; *value holds the result.
243 * Otherwise a fault code.
244 */
245 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
246 uint32_t *value)
247 {
248 int retval;
249
250 retval = mem_ap_read_u32(ap, address, value);
251 if (retval != ERROR_OK)
252 return retval;
253
254 return dap_run(ap->dap);
255 }
256
257 /**
258 * Asynchronous (queued) write of a word to memory or a system register.
259 *
260 * @param ap The MEM-AP to access.
261 * @param address Address to be written; it must be writable by
262 * the currently selected MEM-AP.
263 * @param value Word that will be written to the address when transaction
264 * queue is flushed (assuming no errors).
265 *
266 * @return ERROR_OK for success. Otherwise a fault code.
267 */
268 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
269 uint32_t value)
270 {
271 int retval;
272
273 /* Use banked addressing (REG_BDx) to avoid some link traffic
274 * (updating TAR) when writing several consecutive addresses.
275 */
276 retval = mem_ap_setup_transfer(ap,
277 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
278 address & 0xFFFFFFF0);
279 if (retval != ERROR_OK)
280 return retval;
281
282 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
283 value);
284 }
285
286 /**
287 * Synchronous write of a word to memory or a system register.
288 * As a side effect, this flushes any queued transactions.
289 *
290 * @param ap The MEM-AP to access.
291 * @param address Address to be written; it must be writable by
292 * the currently selected MEM-AP.
293 * @param value Word that will be written.
294 *
295 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
296 */
297 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
298 uint32_t value)
299 {
300 int retval = mem_ap_write_u32(ap, address, value);
301
302 if (retval != ERROR_OK)
303 return retval;
304
305 return dap_run(ap->dap);
306 }
307
308 /**
309 * Synchronous write of a block of memory, using a specific access size.
310 *
311 * @param ap The MEM-AP to access.
312 * @param buffer The data buffer to write. No particular alignment is assumed.
313 * @param size Which access size to use, in bytes. 1, 2 or 4.
314 * @param count The number of writes to do (in size units, not bytes).
315 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
316 * @param addrinc Whether the target address should be increased for each write or not. This
317 * should normally be true, except when writing to e.g. a FIFO.
318 * @return ERROR_OK on success, otherwise an error code.
319 */
320 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
321 uint32_t address, bool addrinc)
322 {
323 struct adiv5_dap *dap = ap->dap;
324 size_t nbytes = size * count;
325 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
326 uint32_t csw_size;
327 uint32_t addr_xor;
328 int retval = ERROR_OK;
329
330 /* TI BE-32 Quirks mode:
331 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
332 * size write address bytes written in order
333 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
334 * 2 TAR ^ 2 (val >> 8), (val)
335 * 1 TAR ^ 3 (val)
336 * For example, if you attempt to write a single byte to address 0, the processor
337 * will actually write a byte to address 3.
338 *
339 * To make writes of size < 4 work as expected, we xor a value with the address before
340 * setting the TAP, and we set the TAP after every transfer rather then relying on
341 * address increment. */
342
343 if (size == 4) {
344 csw_size = CSW_32BIT;
345 addr_xor = 0;
346 } else if (size == 2) {
347 csw_size = CSW_16BIT;
348 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
349 } else if (size == 1) {
350 csw_size = CSW_8BIT;
351 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
352 } else {
353 return ERROR_TARGET_UNALIGNED_ACCESS;
354 }
355
356 if (ap->unaligned_access_bad && (address % size != 0))
357 return ERROR_TARGET_UNALIGNED_ACCESS;
358
359 while (nbytes > 0) {
360 uint32_t this_size = size;
361
362 /* Select packed transfer if possible */
363 if (addrinc && ap->packed_transfers && nbytes >= 4
364 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
365 this_size = 4;
366 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
367 } else {
368 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
369 }
370
371 if (retval != ERROR_OK)
372 break;
373
374 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
375 if (retval != ERROR_OK)
376 return retval;
377
378 /* How many source bytes each transfer will consume, and their location in the DRW,
379 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
380 uint32_t outvalue = 0;
381 uint32_t drw_byte_idx = address;
382 if (dap->ti_be_32_quirks) {
383 switch (this_size) {
384 case 4:
385 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
386 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
387 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
388 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
389 break;
390 case 2:
391 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
392 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
393 break;
394 case 1:
395 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
396 break;
397 }
398 } else {
399 switch (this_size) {
400 case 4:
401 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
402 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
403 /* fallthrough */
404 case 2:
405 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
406 /* fallthrough */
407 case 1:
408 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
409 }
410 }
411
412 nbytes -= this_size;
413
414 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
415 if (retval != ERROR_OK)
416 break;
417
418 mem_ap_update_tar_cache(ap);
419 if (addrinc)
420 address += this_size;
421 }
422
423 /* REVISIT: Might want to have a queued version of this function that does not run. */
424 if (retval == ERROR_OK)
425 retval = dap_run(dap);
426
427 if (retval != ERROR_OK) {
428 uint32_t tar;
429 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
430 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
431 else
432 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
433 }
434
435 return retval;
436 }
437
438 /**
439 * Synchronous read of a block of memory, using a specific access size.
440 *
441 * @param ap The MEM-AP to access.
442 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
443 * @param size Which access size to use, in bytes. 1, 2 or 4.
444 * @param count The number of reads to do (in size units, not bytes).
445 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
446 * @param addrinc Whether the target address should be increased after each read or not. This
447 * should normally be true, except when reading from e.g. a FIFO.
448 * @return ERROR_OK on success, otherwise an error code.
449 */
450 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
451 uint32_t adr, bool addrinc)
452 {
453 struct adiv5_dap *dap = ap->dap;
454 size_t nbytes = size * count;
455 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
456 uint32_t csw_size;
457 uint32_t address = adr;
458 int retval = ERROR_OK;
459
460 /* TI BE-32 Quirks mode:
461 * Reads on big-endian TMS570 behave strangely differently than writes.
462 * They read from the physical address requested, but with DRW byte-reversed.
463 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
464 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
465 * so avoid them. */
466
467 if (size == 4)
468 csw_size = CSW_32BIT;
469 else if (size == 2)
470 csw_size = CSW_16BIT;
471 else if (size == 1)
472 csw_size = CSW_8BIT;
473 else
474 return ERROR_TARGET_UNALIGNED_ACCESS;
475
476 if (ap->unaligned_access_bad && (adr % size != 0))
477 return ERROR_TARGET_UNALIGNED_ACCESS;
478
479 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
480 * over-allocation if packed transfers are going to be used, but determining the real need at
481 * this point would be messy. */
482 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
483 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
484 uint32_t *read_ptr = read_buf;
485 if (read_buf == NULL) {
486 LOG_ERROR("Failed to allocate read buffer");
487 return ERROR_FAIL;
488 }
489
490 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
491 * useful bytes it contains, and their location in the word, depends on the type of transfer
492 * and alignment. */
493 while (nbytes > 0) {
494 uint32_t this_size = size;
495
496 /* Select packed transfer if possible */
497 if (addrinc && ap->packed_transfers && nbytes >= 4
498 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
499 this_size = 4;
500 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
501 } else {
502 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
503 }
504 if (retval != ERROR_OK)
505 break;
506
507 retval = mem_ap_setup_tar(ap, address);
508 if (retval != ERROR_OK)
509 break;
510
511 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
512 if (retval != ERROR_OK)
513 break;
514
515 nbytes -= this_size;
516 if (addrinc)
517 address += this_size;
518
519 mem_ap_update_tar_cache(ap);
520 }
521
522 if (retval == ERROR_OK)
523 retval = dap_run(dap);
524
525 /* Restore state */
526 address = adr;
527 nbytes = size * count;
528 read_ptr = read_buf;
529
530 /* If something failed, read TAR to find out how much data was successfully read, so we can
531 * at least give the caller what we have. */
532 if (retval != ERROR_OK) {
533 uint32_t tar;
534 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
535 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
536 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
537 if (nbytes > tar - address)
538 nbytes = tar - address;
539 } else {
540 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
541 nbytes = 0;
542 }
543 }
544
545 /* Replay loop to populate caller's buffer from the correct word and byte lane */
546 while (nbytes > 0) {
547 uint32_t this_size = size;
548
549 if (addrinc && ap->packed_transfers && nbytes >= 4
550 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
551 this_size = 4;
552 }
553
554 if (dap->ti_be_32_quirks) {
555 switch (this_size) {
556 case 4:
557 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
558 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
559 /* fallthrough */
560 case 2:
561 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
562 /* fallthrough */
563 case 1:
564 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
565 }
566 } else {
567 switch (this_size) {
568 case 4:
569 *buffer++ = *read_ptr >> 8 * (address++ & 3);
570 *buffer++ = *read_ptr >> 8 * (address++ & 3);
571 /* fallthrough */
572 case 2:
573 *buffer++ = *read_ptr >> 8 * (address++ & 3);
574 /* fallthrough */
575 case 1:
576 *buffer++ = *read_ptr >> 8 * (address++ & 3);
577 }
578 }
579
580 read_ptr++;
581 nbytes -= this_size;
582 }
583
584 free(read_buf);
585 return retval;
586 }
587
588 int mem_ap_read_buf(struct adiv5_ap *ap,
589 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
590 {
591 return mem_ap_read(ap, buffer, size, count, address, true);
592 }
593
594 int mem_ap_write_buf(struct adiv5_ap *ap,
595 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
596 {
597 return mem_ap_write(ap, buffer, size, count, address, true);
598 }
599
600 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
601 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
602 {
603 return mem_ap_read(ap, buffer, size, count, address, false);
604 }
605
606 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
607 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
608 {
609 return mem_ap_write(ap, buffer, size, count, address, false);
610 }
611
612 /*--------------------------------------------------------------------------*/
613
614
615 #define DAP_POWER_DOMAIN_TIMEOUT (10)
616
617 /*--------------------------------------------------------------------------*/
618
619 /**
620 * Invalidate cached DP select and cached TAR and CSW of all APs
621 */
622 void dap_invalidate_cache(struct adiv5_dap *dap)
623 {
624 dap->select = DP_SELECT_INVALID;
625 dap->last_read = NULL;
626
627 int i;
628 for (i = 0; i <= 255; i++) {
629 /* force csw and tar write on the next mem-ap access */
630 dap->ap[i].tar_valid = false;
631 dap->ap[i].csw_value = 0;
632 }
633 }
634
635 /**
636 * Initialize a DAP. This sets up the power domains, prepares the DP
637 * for further use and activates overrun checking.
638 *
639 * @param dap The DAP being initialized.
640 */
641 int dap_dp_init(struct adiv5_dap *dap)
642 {
643 int retval;
644
645 LOG_DEBUG("%s", adiv5_dap_name(dap));
646
647 dap_invalidate_cache(dap);
648
649 for (size_t i = 0; i < 30; i++) {
650 /* DP initialization */
651
652 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
653 if (retval == ERROR_OK)
654 break;
655 }
656
657 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
658 if (retval != ERROR_OK)
659 return retval;
660
661 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
662 if (retval != ERROR_OK)
663 return retval;
664
665 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
666 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
667 if (retval != ERROR_OK)
668 return retval;
669
670 /* Check that we have debug power domains activated */
671 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
672 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
673 CDBGPWRUPACK, CDBGPWRUPACK,
674 DAP_POWER_DOMAIN_TIMEOUT);
675 if (retval != ERROR_OK)
676 return retval;
677
678 if (!dap->ignore_syspwrupack) {
679 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
680 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
681 CSYSPWRUPACK, CSYSPWRUPACK,
682 DAP_POWER_DOMAIN_TIMEOUT);
683 if (retval != ERROR_OK)
684 return retval;
685 }
686
687 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
688 if (retval != ERROR_OK)
689 return retval;
690
691 /* With debug power on we can activate OVERRUN checking */
692 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
693 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
694 if (retval != ERROR_OK)
695 return retval;
696 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
697 if (retval != ERROR_OK)
698 return retval;
699
700 retval = dap_run(dap);
701 if (retval != ERROR_OK)
702 return retval;
703
704 return retval;
705 }
706
707 /**
708 * Initialize a DAP. This sets up the power domains, prepares the DP
709 * for further use, and arranges to use AP #0 for all AP operations
710 * until dap_ap-select() changes that policy.
711 *
712 * @param ap The MEM-AP being initialized.
713 */
714 int mem_ap_init(struct adiv5_ap *ap)
715 {
716 /* check that we support packed transfers */
717 uint32_t csw, cfg;
718 int retval;
719 struct adiv5_dap *dap = ap->dap;
720
721 ap->tar_valid = false;
722 ap->csw_value = 0; /* force csw and tar write */
723 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
724 if (retval != ERROR_OK)
725 return retval;
726
727 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
728 if (retval != ERROR_OK)
729 return retval;
730
731 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
732 if (retval != ERROR_OK)
733 return retval;
734
735 retval = dap_run(dap);
736 if (retval != ERROR_OK)
737 return retval;
738
739 if (csw & CSW_ADDRINC_PACKED)
740 ap->packed_transfers = true;
741 else
742 ap->packed_transfers = false;
743
744 /* Packed transfers on TI BE-32 processors do not work correctly in
745 * many cases. */
746 if (dap->ti_be_32_quirks)
747 ap->packed_transfers = false;
748
749 LOG_DEBUG("MEM_AP Packed Transfers: %s",
750 ap->packed_transfers ? "enabled" : "disabled");
751
752 /* The ARM ADI spec leaves implementation-defined whether unaligned
753 * memory accesses work, only work partially, or cause a sticky error.
754 * On TI BE-32 processors, reads seem to return garbage in some bytes
755 * and unaligned writes seem to cause a sticky error.
756 * TODO: it would be nice to have a way to detect whether unaligned
757 * operations are supported on other processors. */
758 ap->unaligned_access_bad = dap->ti_be_32_quirks;
759
760 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
761 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
762
763 return ERROR_OK;
764 }
765
766 /* CID interpretation -- see ARM IHI 0029B section 3
767 * and ARM IHI 0031A table 13-3.
768 */
769 static const char *class_description[16] = {
770 "Reserved", "ROM table", "Reserved", "Reserved",
771 "Reserved", "Reserved", "Reserved", "Reserved",
772 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
773 "Reserved", "OptimoDE DESS",
774 "Generic IP component", "PrimeCell or System component"
775 };
776
777 static bool is_dap_cid_ok(uint32_t cid)
778 {
779 return (cid & 0xffff0fff) == 0xb105000d;
780 }
781
782 /*
783 * This function checks the ID for each access port to find the requested Access Port type
784 */
785 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
786 {
787 int ap_num;
788
789 /* Maximum AP number is 255 since the SELECT register is 8 bits */
790 for (ap_num = 0; ap_num <= 255; ap_num++) {
791
792 /* read the IDR register of the Access Port */
793 uint32_t id_val = 0;
794
795 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
796 if (retval != ERROR_OK)
797 return retval;
798
799 retval = dap_run(dap);
800
801 /* IDR bits:
802 * 31-28 : Revision
803 * 27-24 : JEDEC bank (0x4 for ARM)
804 * 23-17 : JEDEC code (0x3B for ARM)
805 * 16-13 : Class (0b1000=Mem-AP)
806 * 12-8 : Reserved
807 * 7-4 : AP Variant (non-zero for JTAG-AP)
808 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
809 */
810
811 /* Reading register for a non-existant AP should not cause an error,
812 * but just to be sure, try to continue searching if an error does happen.
813 */
814 if ((retval == ERROR_OK) && /* Register read success */
815 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
816 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
817
818 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
819 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
820 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
821 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
822 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
823 ap_num, id_val);
824
825 *ap_out = &dap->ap[ap_num];
826 return ERROR_OK;
827 }
828 }
829
830 LOG_DEBUG("No %s found",
831 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
832 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
833 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
834 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
835 return ERROR_FAIL;
836 }
837
838 int dap_get_debugbase(struct adiv5_ap *ap,
839 uint32_t *dbgbase, uint32_t *apid)
840 {
841 struct adiv5_dap *dap = ap->dap;
842 int retval;
843
844 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
845 if (retval != ERROR_OK)
846 return retval;
847 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
848 if (retval != ERROR_OK)
849 return retval;
850 retval = dap_run(dap);
851 if (retval != ERROR_OK)
852 return retval;
853
854 return ERROR_OK;
855 }
856
857 int dap_lookup_cs_component(struct adiv5_ap *ap,
858 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
859 {
860 uint32_t romentry, entry_offset = 0, component_base, devtype;
861 int retval;
862
863 *addr = 0;
864
865 do {
866 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
867 entry_offset, &romentry);
868 if (retval != ERROR_OK)
869 return retval;
870
871 component_base = (dbgbase & 0xFFFFF000)
872 + (romentry & 0xFFFFF000);
873
874 if (romentry & 0x1) {
875 uint32_t c_cid1;
876 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
877 if (retval != ERROR_OK) {
878 LOG_ERROR("Can't read component with base address 0x%" PRIx32
879 ", the corresponding core might be turned off", component_base);
880 return retval;
881 }
882 if (((c_cid1 >> 4) & 0x0f) == 1) {
883 retval = dap_lookup_cs_component(ap, component_base,
884 type, addr, idx);
885 if (retval == ERROR_OK)
886 break;
887 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
888 return retval;
889 }
890
891 retval = mem_ap_read_atomic_u32(ap,
892 (component_base & 0xfffff000) | 0xfcc,
893 &devtype);
894 if (retval != ERROR_OK)
895 return retval;
896 if ((devtype & 0xff) == type) {
897 if (!*idx) {
898 *addr = component_base;
899 break;
900 } else
901 (*idx)--;
902 }
903 }
904 entry_offset += 4;
905 } while (romentry > 0);
906
907 if (!*addr)
908 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
909
910 return ERROR_OK;
911 }
912
913 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
914 {
915 assert((component_base & 0xFFF) == 0);
916 assert(ap != NULL && cid != NULL && pid != NULL);
917
918 uint32_t cid0, cid1, cid2, cid3;
919 uint32_t pid0, pid1, pid2, pid3, pid4;
920 int retval;
921
922 /* IDs are in last 4K section */
923 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
924 if (retval != ERROR_OK)
925 return retval;
926 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
927 if (retval != ERROR_OK)
928 return retval;
929 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
930 if (retval != ERROR_OK)
931 return retval;
932 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
933 if (retval != ERROR_OK)
934 return retval;
935 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
936 if (retval != ERROR_OK)
937 return retval;
938 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
939 if (retval != ERROR_OK)
940 return retval;
941 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
942 if (retval != ERROR_OK)
943 return retval;
944 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
945 if (retval != ERROR_OK)
946 return retval;
947 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
948 if (retval != ERROR_OK)
949 return retval;
950
951 retval = dap_run(ap->dap);
952 if (retval != ERROR_OK)
953 return retval;
954
955 *cid = (cid3 & 0xff) << 24
956 | (cid2 & 0xff) << 16
957 | (cid1 & 0xff) << 8
958 | (cid0 & 0xff);
959 *pid = (uint64_t)(pid4 & 0xff) << 32
960 | (pid3 & 0xff) << 24
961 | (pid2 & 0xff) << 16
962 | (pid1 & 0xff) << 8
963 | (pid0 & 0xff);
964
965 return ERROR_OK;
966 }
967
968 /* The designer identity code is encoded as:
969 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
970 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
971 * a legacy ASCII Identity Code.
972 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
973 * JEP106 is a standard available from jedec.org
974 */
975
976 /* Part number interpretations are from Cortex
977 * core specs, the CoreSight components TRM
978 * (ARM DDI 0314H), CoreSight System Design
979 * Guide (ARM DGI 0012D) and ETM specs; also
980 * from chip observation (e.g. TI SDTI).
981 */
982
983 /* The legacy code only used the part number field to identify CoreSight peripherals.
984 * This meant that the same part number from two different manufacturers looked the same.
985 * It is desirable for all future additions to identify with both part number and JEP106.
986 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
987 */
988
989 #define ANY_ID 0x1000
990
991 #define ARM_ID 0x4BB
992
993 static const struct {
994 uint16_t designer_id;
995 uint16_t part_num;
996 const char *type;
997 const char *full;
998 } dap_partnums[] = {
999 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1000 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1001 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1002 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1003 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1004 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1005 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1006 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1007 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1008 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1009 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1010 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1011 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1012 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1013 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1014 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1015 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1016 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1017 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1018 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1019 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1020 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1021 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1022 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1023 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1024 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1025 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1026 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1027 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1028 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1029 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1030 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1031 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1032 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1033 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1034 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1035 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1036 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1037 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1038 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1039 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1040 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1041 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1042 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1043 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1044 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1045 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1046 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1047 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1048 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1049 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1050 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1051 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1052 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1053 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1054 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1055 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1056 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1057 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1058 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1059 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1060 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1061 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1062 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1063 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1064 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1065 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1066 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1067 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1068 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1069 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1070 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1071 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1072 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1073 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1074 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1075 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1076 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1077 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1078 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1079 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1080 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1081 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1082 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1083 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1084 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1085 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1086 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1087 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1088 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1089 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1090 /* legacy comment: 0x113: what? */
1091 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1092 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1093 };
1094
1095 static int dap_rom_display(struct command_context *cmd_ctx,
1096 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1097 {
1098 int retval;
1099 uint64_t pid;
1100 uint32_t cid;
1101 char tabs[16] = "";
1102
1103 if (depth > 16) {
1104 command_print(cmd_ctx, "\tTables too deep");
1105 return ERROR_FAIL;
1106 }
1107
1108 if (depth)
1109 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1110
1111 uint32_t base_addr = dbgbase & 0xFFFFF000;
1112 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1113
1114 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1115 if (retval != ERROR_OK) {
1116 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1117 return ERROR_OK; /* Don't abort recursion */
1118 }
1119
1120 if (!is_dap_cid_ok(cid)) {
1121 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1122 return ERROR_OK; /* Don't abort recursion */
1123 }
1124
1125 /* component may take multiple 4K pages */
1126 uint32_t size = (pid >> 36) & 0xf;
1127 if (size > 0)
1128 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1129
1130 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1131
1132 uint8_t class = (cid >> 12) & 0xf;
1133 uint16_t part_num = pid & 0xfff;
1134 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1135
1136 if (designer_id & 0x80) {
1137 /* JEP106 code */
1138 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1139 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1140 } else {
1141 /* Legacy ASCII ID, clear invalid bits */
1142 designer_id &= 0x7f;
1143 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1144 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1145 }
1146
1147 /* default values to be overwritten upon finding a match */
1148 const char *type = "Unrecognized";
1149 const char *full = "";
1150
1151 /* search dap_partnums[] array for a match */
1152 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1153
1154 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1155 continue;
1156
1157 if (dap_partnums[entry].part_num != part_num)
1158 continue;
1159
1160 type = dap_partnums[entry].type;
1161 full = dap_partnums[entry].full;
1162 break;
1163 }
1164
1165 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1166 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1167
1168 if (class == 1) { /* ROM Table */
1169 uint32_t memtype;
1170 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1171 if (retval != ERROR_OK)
1172 return retval;
1173
1174 if (memtype & 0x01)
1175 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1176 else
1177 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1178
1179 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1180 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1181 uint32_t romentry;
1182 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1183 if (retval != ERROR_OK)
1184 return retval;
1185 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1186 tabs, entry_offset, romentry);
1187 if (romentry & 0x01) {
1188 /* Recurse */
1189 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1190 if (retval != ERROR_OK)
1191 return retval;
1192 } else if (romentry != 0) {
1193 command_print(cmd_ctx, "\t\tComponent not present");
1194 } else {
1195 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1196 break;
1197 }
1198 }
1199 } else if (class == 9) { /* CoreSight component */
1200 const char *major = "Reserved", *subtype = "Reserved";
1201
1202 uint32_t devtype;
1203 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1204 if (retval != ERROR_OK)
1205 return retval;
1206 unsigned minor = (devtype >> 4) & 0x0f;
1207 switch (devtype & 0x0f) {
1208 case 0:
1209 major = "Miscellaneous";
1210 switch (minor) {
1211 case 0:
1212 subtype = "other";
1213 break;
1214 case 4:
1215 subtype = "Validation component";
1216 break;
1217 }
1218 break;
1219 case 1:
1220 major = "Trace Sink";
1221 switch (minor) {
1222 case 0:
1223 subtype = "other";
1224 break;
1225 case 1:
1226 subtype = "Port";
1227 break;
1228 case 2:
1229 subtype = "Buffer";
1230 break;
1231 case 3:
1232 subtype = "Router";
1233 break;
1234 }
1235 break;
1236 case 2:
1237 major = "Trace Link";
1238 switch (minor) {
1239 case 0:
1240 subtype = "other";
1241 break;
1242 case 1:
1243 subtype = "Funnel, router";
1244 break;
1245 case 2:
1246 subtype = "Filter";
1247 break;
1248 case 3:
1249 subtype = "FIFO, buffer";
1250 break;
1251 }
1252 break;
1253 case 3:
1254 major = "Trace Source";
1255 switch (minor) {
1256 case 0:
1257 subtype = "other";
1258 break;
1259 case 1:
1260 subtype = "Processor";
1261 break;
1262 case 2:
1263 subtype = "DSP";
1264 break;
1265 case 3:
1266 subtype = "Engine/Coprocessor";
1267 break;
1268 case 4:
1269 subtype = "Bus";
1270 break;
1271 case 6:
1272 subtype = "Software";
1273 break;
1274 }
1275 break;
1276 case 4:
1277 major = "Debug Control";
1278 switch (minor) {
1279 case 0:
1280 subtype = "other";
1281 break;
1282 case 1:
1283 subtype = "Trigger Matrix";
1284 break;
1285 case 2:
1286 subtype = "Debug Auth";
1287 break;
1288 case 3:
1289 subtype = "Power Requestor";
1290 break;
1291 }
1292 break;
1293 case 5:
1294 major = "Debug Logic";
1295 switch (minor) {
1296 case 0:
1297 subtype = "other";
1298 break;
1299 case 1:
1300 subtype = "Processor";
1301 break;
1302 case 2:
1303 subtype = "DSP";
1304 break;
1305 case 3:
1306 subtype = "Engine/Coprocessor";
1307 break;
1308 case 4:
1309 subtype = "Bus";
1310 break;
1311 case 5:
1312 subtype = "Memory";
1313 break;
1314 }
1315 break;
1316 case 6:
1317 major = "Perfomance Monitor";
1318 switch (minor) {
1319 case 0:
1320 subtype = "other";
1321 break;
1322 case 1:
1323 subtype = "Processor";
1324 break;
1325 case 2:
1326 subtype = "DSP";
1327 break;
1328 case 3:
1329 subtype = "Engine/Coprocessor";
1330 break;
1331 case 4:
1332 subtype = "Bus";
1333 break;
1334 case 5:
1335 subtype = "Memory";
1336 break;
1337 }
1338 break;
1339 }
1340 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1341 (uint8_t)(devtype & 0xff),
1342 major, subtype);
1343 /* REVISIT also show 0xfc8 DevId */
1344 }
1345
1346 return ERROR_OK;
1347 }
1348
1349 int dap_info_command(struct command_context *cmd_ctx,
1350 struct adiv5_ap *ap)
1351 {
1352 int retval;
1353 uint32_t dbgbase, apid;
1354 uint8_t mem_ap;
1355
1356 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1357 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1358 if (retval != ERROR_OK)
1359 return retval;
1360
1361 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1362 if (apid == 0) {
1363 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1364 return ERROR_FAIL;
1365 }
1366
1367 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1368 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1369 command_print(cmd_ctx, "\tType is JTAG-AP");
1370 break;
1371 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1372 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1373 break;
1374 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1375 command_print(cmd_ctx, "\tType is MEM-AP APB");
1376 break;
1377 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1378 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1379 break;
1380 default:
1381 command_print(cmd_ctx, "\tUnknown AP type");
1382 break;
1383 }
1384
1385 /* NOTE: a MEM-AP may have a single CoreSight component that's
1386 * not a ROM table ... or have no such components at all.
1387 */
1388 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1389 if (mem_ap) {
1390 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1391
1392 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1393 command_print(cmd_ctx, "\tNo ROM table present");
1394 } else {
1395 if (dbgbase & 0x01)
1396 command_print(cmd_ctx, "\tValid ROM table present");
1397 else
1398 command_print(cmd_ctx, "\tROM table in legacy format");
1399
1400 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1401 }
1402 }
1403
1404 return ERROR_OK;
1405 }
1406
1407 enum adiv5_cfg_param {
1408 CFG_DAP,
1409 CFG_AP_NUM
1410 };
1411
1412 static const Jim_Nvp nvp_config_opts[] = {
1413 { .name = "-dap", .value = CFG_DAP },
1414 { .name = "-ap-num", .value = CFG_AP_NUM },
1415 { .name = NULL, .value = -1 }
1416 };
1417
1418 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1419 {
1420 struct adiv5_private_config *pc;
1421 int e;
1422
1423 pc = (struct adiv5_private_config *)target->private_config;
1424 if (pc == NULL) {
1425 pc = calloc(1, sizeof(struct adiv5_private_config));
1426 pc->ap_num = -1;
1427 target->private_config = pc;
1428 }
1429
1430 target->has_dap = true;
1431
1432 if (goi->argc > 0) {
1433 Jim_Nvp *n;
1434
1435 Jim_SetEmptyResult(goi->interp);
1436
1437 /* check first if topmost item is for us */
1438 e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts,
1439 goi->argv[0], &n);
1440 if (e != JIM_OK)
1441 return JIM_CONTINUE;
1442
1443 e = Jim_GetOpt_Obj(goi, NULL);
1444 if (e != JIM_OK)
1445 return e;
1446
1447 switch (n->value) {
1448 case CFG_DAP:
1449 if (goi->isconfigure) {
1450 Jim_Obj *o_t;
1451 struct adiv5_dap *dap;
1452 e = Jim_GetOpt_Obj(goi, &o_t);
1453 if (e != JIM_OK)
1454 return e;
1455 dap = dap_instance_by_jim_obj(goi->interp, o_t);
1456 if (dap == NULL) {
1457 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
1458 return JIM_ERR;
1459 }
1460 if (pc->dap != NULL && pc->dap != dap) {
1461 Jim_SetResultString(goi->interp,
1462 "DAP assignment cannot be changed after target was created!", -1);
1463 return JIM_ERR;
1464 }
1465 if (target->tap_configured) {
1466 Jim_SetResultString(goi->interp,
1467 "-chain-position and -dap configparams are mutually exclusive!", -1);
1468 return JIM_ERR;
1469 }
1470 pc->dap = dap;
1471 target->tap = dap->tap;
1472 target->dap_configured = true;
1473 } else {
1474 if (goi->argc != 0) {
1475 Jim_WrongNumArgs(goi->interp,
1476 goi->argc, goi->argv,
1477 "NO PARAMS");
1478 return JIM_ERR;
1479 }
1480
1481 if (pc->dap == NULL) {
1482 Jim_SetResultString(goi->interp, "DAP not configured", -1);
1483 return JIM_ERR;
1484 }
1485 Jim_SetResultString(goi->interp, adiv5_dap_name(pc->dap), -1);
1486 }
1487 break;
1488
1489 case CFG_AP_NUM:
1490 if (goi->isconfigure) {
1491 jim_wide ap_num;
1492 e = Jim_GetOpt_Wide(goi, &ap_num);
1493 if (e != JIM_OK)
1494 return e;
1495 pc->ap_num = ap_num;
1496 } else {
1497 if (goi->argc != 0) {
1498 Jim_WrongNumArgs(goi->interp,
1499 goi->argc, goi->argv,
1500 "NO PARAMS");
1501 return JIM_ERR;
1502 }
1503
1504 if (pc->ap_num < 0) {
1505 Jim_SetResultString(goi->interp, "AP number not configured", -1);
1506 return JIM_ERR;
1507 }
1508 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, (int)pc->ap_num));
1509 }
1510 break;
1511 }
1512 }
1513
1514 return JIM_OK;
1515 }
1516
1517 int adiv5_verify_config(struct adiv5_private_config *pc)
1518 {
1519 if (pc == NULL)
1520 return ERROR_FAIL;
1521
1522 if (pc->dap == NULL)
1523 return ERROR_FAIL;
1524
1525 return ERROR_OK;
1526 }
1527
1528
1529 COMMAND_HANDLER(handle_dap_info_command)
1530 {
1531 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1532 uint32_t apsel;
1533
1534 switch (CMD_ARGC) {
1535 case 0:
1536 apsel = dap->apsel;
1537 break;
1538 case 1:
1539 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1540 if (apsel >= 256)
1541 return ERROR_COMMAND_SYNTAX_ERROR;
1542 break;
1543 default:
1544 return ERROR_COMMAND_SYNTAX_ERROR;
1545 }
1546
1547 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1548 }
1549
1550 COMMAND_HANDLER(dap_baseaddr_command)
1551 {
1552 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1553 uint32_t apsel, baseaddr;
1554 int retval;
1555
1556 switch (CMD_ARGC) {
1557 case 0:
1558 apsel = dap->apsel;
1559 break;
1560 case 1:
1561 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1562 /* AP address is in bits 31:24 of DP_SELECT */
1563 if (apsel >= 256)
1564 return ERROR_COMMAND_SYNTAX_ERROR;
1565 break;
1566 default:
1567 return ERROR_COMMAND_SYNTAX_ERROR;
1568 }
1569
1570 /* NOTE: assumes we're talking to a MEM-AP, which
1571 * has a base address. There are other kinds of AP,
1572 * though they're not common for now. This should
1573 * use the ID register to verify it's a MEM-AP.
1574 */
1575 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1576 if (retval != ERROR_OK)
1577 return retval;
1578 retval = dap_run(dap);
1579 if (retval != ERROR_OK)
1580 return retval;
1581
1582 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1583
1584 return retval;
1585 }
1586
1587 COMMAND_HANDLER(dap_memaccess_command)
1588 {
1589 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1590 uint32_t memaccess_tck;
1591
1592 switch (CMD_ARGC) {
1593 case 0:
1594 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1595 break;
1596 case 1:
1597 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1598 break;
1599 default:
1600 return ERROR_COMMAND_SYNTAX_ERROR;
1601 }
1602 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1603
1604 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1605 dap->ap[dap->apsel].memaccess_tck);
1606
1607 return ERROR_OK;
1608 }
1609
1610 COMMAND_HANDLER(dap_apsel_command)
1611 {
1612 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1613 uint32_t apsel, apid;
1614 int retval;
1615
1616 switch (CMD_ARGC) {
1617 case 0:
1618 apsel = dap->apsel;
1619 break;
1620 case 1:
1621 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1622 /* AP address is in bits 31:24 of DP_SELECT */
1623 if (apsel >= 256)
1624 return ERROR_COMMAND_SYNTAX_ERROR;
1625 break;
1626 default:
1627 return ERROR_COMMAND_SYNTAX_ERROR;
1628 }
1629
1630 dap->apsel = apsel;
1631
1632 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1633 if (retval != ERROR_OK)
1634 return retval;
1635 retval = dap_run(dap);
1636 if (retval != ERROR_OK)
1637 return retval;
1638
1639 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1640 apsel, apid);
1641
1642 return retval;
1643 }
1644
1645 COMMAND_HANDLER(dap_apcsw_command)
1646 {
1647 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1648 uint32_t apcsw = dap->ap[dap->apsel].csw_default;
1649 uint32_t csw_val, csw_mask;
1650
1651 switch (CMD_ARGC) {
1652 case 0:
1653 command_print(CMD_CTX, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1654 dap->apsel, apcsw);
1655 return ERROR_OK;
1656 case 1:
1657 if (strcmp(CMD_ARGV[0], "default") == 0)
1658 csw_val = CSW_DEFAULT;
1659 else
1660 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1661
1662 if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1663 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
1664 return ERROR_COMMAND_SYNTAX_ERROR;
1665 }
1666 apcsw = csw_val;
1667 break;
1668 case 2:
1669 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1670 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
1671 if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1672 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
1673 return ERROR_COMMAND_SYNTAX_ERROR;
1674 }
1675 apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
1676 break;
1677 default:
1678 return ERROR_COMMAND_SYNTAX_ERROR;
1679 }
1680 dap->ap[dap->apsel].csw_default = apcsw;
1681
1682 return 0;
1683 }
1684
1685
1686
1687 COMMAND_HANDLER(dap_apid_command)
1688 {
1689 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1690 uint32_t apsel, apid;
1691 int retval;
1692
1693 switch (CMD_ARGC) {
1694 case 0:
1695 apsel = dap->apsel;
1696 break;
1697 case 1:
1698 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1699 /* AP address is in bits 31:24 of DP_SELECT */
1700 if (apsel >= 256)
1701 return ERROR_COMMAND_SYNTAX_ERROR;
1702 break;
1703 default:
1704 return ERROR_COMMAND_SYNTAX_ERROR;
1705 }
1706
1707 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1708 if (retval != ERROR_OK)
1709 return retval;
1710 retval = dap_run(dap);
1711 if (retval != ERROR_OK)
1712 return retval;
1713
1714 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1715
1716 return retval;
1717 }
1718
1719 COMMAND_HANDLER(dap_apreg_command)
1720 {
1721 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1722 uint32_t apsel, reg, value;
1723 int retval;
1724
1725 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1726 return ERROR_COMMAND_SYNTAX_ERROR;
1727
1728 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1729 /* AP address is in bits 31:24 of DP_SELECT */
1730 if (apsel >= 256)
1731 return ERROR_COMMAND_SYNTAX_ERROR;
1732
1733 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1734 if (reg >= 256 || (reg & 3))
1735 return ERROR_COMMAND_SYNTAX_ERROR;
1736
1737 if (CMD_ARGC == 3) {
1738 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1739 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1740 } else {
1741 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1742 }
1743 if (retval == ERROR_OK)
1744 retval = dap_run(dap);
1745
1746 if (retval != ERROR_OK)
1747 return retval;
1748
1749 if (CMD_ARGC == 2)
1750 command_print(CMD_CTX, "0x%08" PRIx32, value);
1751
1752 return retval;
1753 }
1754
1755 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1756 {
1757 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1758 uint32_t enable = dap->ti_be_32_quirks;
1759
1760 switch (CMD_ARGC) {
1761 case 0:
1762 break;
1763 case 1:
1764 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1765 if (enable > 1)
1766 return ERROR_COMMAND_SYNTAX_ERROR;
1767 break;
1768 default:
1769 return ERROR_COMMAND_SYNTAX_ERROR;
1770 }
1771 dap->ti_be_32_quirks = enable;
1772 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1773 enable ? "enabled" : "disabled");
1774
1775 return 0;
1776 }
1777
1778 const struct command_registration dap_instance_commands[] = {
1779 {
1780 .name = "info",
1781 .handler = handle_dap_info_command,
1782 .mode = COMMAND_EXEC,
1783 .help = "display ROM table for MEM-AP "
1784 "(default currently selected AP)",
1785 .usage = "[ap_num]",
1786 },
1787 {
1788 .name = "apsel",
1789 .handler = dap_apsel_command,
1790 .mode = COMMAND_EXEC,
1791 .help = "Set the currently selected AP (default 0) "
1792 "and display the result",
1793 .usage = "[ap_num]",
1794 },
1795 {
1796 .name = "apcsw",
1797 .handler = dap_apcsw_command,
1798 .mode = COMMAND_EXEC,
1799 .help = "Set CSW default bits",
1800 .usage = "[value [mask]]",
1801 },
1802
1803 {
1804 .name = "apid",
1805 .handler = dap_apid_command,
1806 .mode = COMMAND_EXEC,
1807 .help = "return ID register from AP "
1808 "(default currently selected AP)",
1809 .usage = "[ap_num]",
1810 },
1811 {
1812 .name = "apreg",
1813 .handler = dap_apreg_command,
1814 .mode = COMMAND_EXEC,
1815 .help = "read/write a register from AP "
1816 "(reg is byte address of a word register, like 0 4 8...)",
1817 .usage = "ap_num reg [value]",
1818 },
1819 {
1820 .name = "baseaddr",
1821 .handler = dap_baseaddr_command,
1822 .mode = COMMAND_EXEC,
1823 .help = "return debug base address from MEM-AP "
1824 "(default currently selected AP)",
1825 .usage = "[ap_num]",
1826 },
1827 {
1828 .name = "memaccess",
1829 .handler = dap_memaccess_command,
1830 .mode = COMMAND_EXEC,
1831 .help = "set/get number of extra tck for MEM-AP memory "
1832 "bus access [0-255]",
1833 .usage = "[cycles]",
1834 },
1835 {
1836 .name = "ti_be_32_quirks",
1837 .handler = dap_ti_be_32_quirks_command,
1838 .mode = COMMAND_CONFIG,
1839 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1840 .usage = "[enable]",
1841 },
1842 COMMAND_REGISTRATION_DONE
1843 };