Fix warnings exposed by GCC8
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
29
30 /**
31 * @file
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
37 *
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 *
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
57 */
58
59 /*
60 * Relevant specifications from ARM include:
61 *
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 *
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 */
68
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
79 #include <helper/jim-nvp.h>
80
81 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
82
83 /*
84 uint32_t tar_block_size(uint32_t address)
85 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 */
87 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 {
89 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
90 }
91
92 /***************************************************************************
93 * *
94 * DP and MEM-AP register access through APACC and DPACC *
95 * *
96 ***************************************************************************/
97
98 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 {
100 csw |= ap->csw_default;
101
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK)
106 return retval;
107 ap->csw_value = csw;
108 }
109 return ERROR_OK;
110 }
111
112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
113 {
114 if (!ap->tar_valid || tar != ap->tar_value) {
115 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
116 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
117 if (retval != ERROR_OK)
118 return retval;
119 ap->tar_value = tar;
120 ap->tar_valid = true;
121 }
122 return ERROR_OK;
123 }
124
125 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
126 {
127 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
128 if (retval != ERROR_OK) {
129 ap->tar_valid = false;
130 return retval;
131 }
132
133 retval = dap_run(ap->dap);
134 if (retval != ERROR_OK) {
135 ap->tar_valid = false;
136 return retval;
137 }
138
139 ap->tar_value = *tar;
140 ap->tar_valid = true;
141 return ERROR_OK;
142 }
143
144 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
145 {
146 switch (ap->csw_value & CSW_ADDRINC_MASK) {
147 case CSW_ADDRINC_SINGLE:
148 switch (ap->csw_value & CSW_SIZE_MASK) {
149 case CSW_8BIT:
150 return 1;
151 case CSW_16BIT:
152 return 2;
153 case CSW_32BIT:
154 return 4;
155 default:
156 return 0;
157 }
158 case CSW_ADDRINC_PACKED:
159 return 4;
160 }
161 return 0;
162 }
163
164 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
165 */
166 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
167 {
168 if (!ap->tar_valid)
169 return;
170
171 uint32_t inc = mem_ap_get_tar_increment(ap);
172 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
173 ap->tar_valid = false;
174 else
175 ap->tar_value += inc;
176 }
177
178 /**
179 * Queue transactions setting up transfer parameters for the
180 * currently selected MEM-AP.
181 *
182 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
183 * initiate data reads or writes using memory or peripheral addresses.
184 * If the CSW is configured for it, the TAR may be automatically
185 * incremented after each transfer.
186 *
187 * @param ap The MEM-AP.
188 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
189 * matches the cached value, the register is not changed.
190 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
191 * matches the cached address, the register is not changed.
192 *
193 * @return ERROR_OK if the transaction was properly queued, else a fault code.
194 */
195 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
196 {
197 int retval;
198 retval = mem_ap_setup_csw(ap, csw);
199 if (retval != ERROR_OK)
200 return retval;
201 retval = mem_ap_setup_tar(ap, tar);
202 if (retval != ERROR_OK)
203 return retval;
204 return ERROR_OK;
205 }
206
207 /**
208 * Asynchronous (queued) read of a word from memory or a system register.
209 *
210 * @param ap The MEM-AP to access.
211 * @param address Address of the 32-bit word to read; it must be
212 * readable by the currently selected MEM-AP.
213 * @param value points to where the word will be stored when the
214 * transaction queue is flushed (assuming no errors).
215 *
216 * @return ERROR_OK for success. Otherwise a fault code.
217 */
218 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
219 uint32_t *value)
220 {
221 int retval;
222
223 /* Use banked addressing (REG_BDx) to avoid some link traffic
224 * (updating TAR) when reading several consecutive addresses.
225 */
226 retval = mem_ap_setup_transfer(ap,
227 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
228 address & 0xFFFFFFF0);
229 if (retval != ERROR_OK)
230 return retval;
231
232 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
233 }
234
235 /**
236 * Synchronous read of a word from memory or a system register.
237 * As a side effect, this flushes any queued transactions.
238 *
239 * @param ap The MEM-AP to access.
240 * @param address Address of the 32-bit word to read; it must be
241 * readable by the currently selected MEM-AP.
242 * @param value points to where the result will be stored.
243 *
244 * @return ERROR_OK for success; *value holds the result.
245 * Otherwise a fault code.
246 */
247 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
248 uint32_t *value)
249 {
250 int retval;
251
252 retval = mem_ap_read_u32(ap, address, value);
253 if (retval != ERROR_OK)
254 return retval;
255
256 return dap_run(ap->dap);
257 }
258
259 /**
260 * Asynchronous (queued) write of a word to memory or a system register.
261 *
262 * @param ap The MEM-AP to access.
263 * @param address Address to be written; it must be writable by
264 * the currently selected MEM-AP.
265 * @param value Word that will be written to the address when transaction
266 * queue is flushed (assuming no errors).
267 *
268 * @return ERROR_OK for success. Otherwise a fault code.
269 */
270 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
271 uint32_t value)
272 {
273 int retval;
274
275 /* Use banked addressing (REG_BDx) to avoid some link traffic
276 * (updating TAR) when writing several consecutive addresses.
277 */
278 retval = mem_ap_setup_transfer(ap,
279 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
280 address & 0xFFFFFFF0);
281 if (retval != ERROR_OK)
282 return retval;
283
284 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
285 value);
286 }
287
288 /**
289 * Synchronous write of a word to memory or a system register.
290 * As a side effect, this flushes any queued transactions.
291 *
292 * @param ap The MEM-AP to access.
293 * @param address Address to be written; it must be writable by
294 * the currently selected MEM-AP.
295 * @param value Word that will be written.
296 *
297 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
298 */
299 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
300 uint32_t value)
301 {
302 int retval = mem_ap_write_u32(ap, address, value);
303
304 if (retval != ERROR_OK)
305 return retval;
306
307 return dap_run(ap->dap);
308 }
309
310 /**
311 * Synchronous write of a block of memory, using a specific access size.
312 *
313 * @param ap The MEM-AP to access.
314 * @param buffer The data buffer to write. No particular alignment is assumed.
315 * @param size Which access size to use, in bytes. 1, 2 or 4.
316 * @param count The number of writes to do (in size units, not bytes).
317 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
318 * @param addrinc Whether the target address should be increased for each write or not. This
319 * should normally be true, except when writing to e.g. a FIFO.
320 * @return ERROR_OK on success, otherwise an error code.
321 */
322 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
323 uint32_t address, bool addrinc)
324 {
325 struct adiv5_dap *dap = ap->dap;
326 size_t nbytes = size * count;
327 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
328 uint32_t csw_size;
329 uint32_t addr_xor;
330 int retval = ERROR_OK;
331
332 /* TI BE-32 Quirks mode:
333 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
334 * size write address bytes written in order
335 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
336 * 2 TAR ^ 2 (val >> 8), (val)
337 * 1 TAR ^ 3 (val)
338 * For example, if you attempt to write a single byte to address 0, the processor
339 * will actually write a byte to address 3.
340 *
341 * To make writes of size < 4 work as expected, we xor a value with the address before
342 * setting the TAP, and we set the TAP after every transfer rather then relying on
343 * address increment. */
344
345 if (size == 4) {
346 csw_size = CSW_32BIT;
347 addr_xor = 0;
348 } else if (size == 2) {
349 csw_size = CSW_16BIT;
350 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
351 } else if (size == 1) {
352 csw_size = CSW_8BIT;
353 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
354 } else {
355 return ERROR_TARGET_UNALIGNED_ACCESS;
356 }
357
358 if (ap->unaligned_access_bad && (address % size != 0))
359 return ERROR_TARGET_UNALIGNED_ACCESS;
360
361 while (nbytes > 0) {
362 uint32_t this_size = size;
363
364 /* Select packed transfer if possible */
365 if (addrinc && ap->packed_transfers && nbytes >= 4
366 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
367 this_size = 4;
368 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
369 } else {
370 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
371 }
372
373 if (retval != ERROR_OK)
374 break;
375
376 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
377 if (retval != ERROR_OK)
378 return retval;
379
380 /* How many source bytes each transfer will consume, and their location in the DRW,
381 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
382 uint32_t outvalue = 0;
383 uint32_t drw_byte_idx = address;
384 if (dap->ti_be_32_quirks) {
385 switch (this_size) {
386 case 4:
387 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
388 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
389 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
390 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
391 break;
392 case 2:
393 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
394 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
395 break;
396 case 1:
397 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
398 break;
399 }
400 } else {
401 switch (this_size) {
402 case 4:
403 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
404 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
405 /* fallthrough */
406 case 2:
407 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
408 /* fallthrough */
409 case 1:
410 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
411 }
412 }
413
414 nbytes -= this_size;
415
416 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
417 if (retval != ERROR_OK)
418 break;
419
420 mem_ap_update_tar_cache(ap);
421 if (addrinc)
422 address += this_size;
423 }
424
425 /* REVISIT: Might want to have a queued version of this function that does not run. */
426 if (retval == ERROR_OK)
427 retval = dap_run(dap);
428
429 if (retval != ERROR_OK) {
430 uint32_t tar;
431 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
432 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
433 else
434 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
435 }
436
437 return retval;
438 }
439
440 /**
441 * Synchronous read of a block of memory, using a specific access size.
442 *
443 * @param ap The MEM-AP to access.
444 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
445 * @param size Which access size to use, in bytes. 1, 2 or 4.
446 * @param count The number of reads to do (in size units, not bytes).
447 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
448 * @param addrinc Whether the target address should be increased after each read or not. This
449 * should normally be true, except when reading from e.g. a FIFO.
450 * @return ERROR_OK on success, otherwise an error code.
451 */
452 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
453 uint32_t adr, bool addrinc)
454 {
455 struct adiv5_dap *dap = ap->dap;
456 size_t nbytes = size * count;
457 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
458 uint32_t csw_size;
459 uint32_t address = adr;
460 int retval = ERROR_OK;
461
462 /* TI BE-32 Quirks mode:
463 * Reads on big-endian TMS570 behave strangely differently than writes.
464 * They read from the physical address requested, but with DRW byte-reversed.
465 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
466 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
467 * so avoid them. */
468
469 if (size == 4)
470 csw_size = CSW_32BIT;
471 else if (size == 2)
472 csw_size = CSW_16BIT;
473 else if (size == 1)
474 csw_size = CSW_8BIT;
475 else
476 return ERROR_TARGET_UNALIGNED_ACCESS;
477
478 if (ap->unaligned_access_bad && (adr % size != 0))
479 return ERROR_TARGET_UNALIGNED_ACCESS;
480
481 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
482 * over-allocation if packed transfers are going to be used, but determining the real need at
483 * this point would be messy. */
484 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
485 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
486 uint32_t *read_ptr = read_buf;
487 if (read_buf == NULL) {
488 LOG_ERROR("Failed to allocate read buffer");
489 return ERROR_FAIL;
490 }
491
492 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
493 * useful bytes it contains, and their location in the word, depends on the type of transfer
494 * and alignment. */
495 while (nbytes > 0) {
496 uint32_t this_size = size;
497
498 /* Select packed transfer if possible */
499 if (addrinc && ap->packed_transfers && nbytes >= 4
500 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
501 this_size = 4;
502 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
503 } else {
504 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
505 }
506 if (retval != ERROR_OK)
507 break;
508
509 retval = mem_ap_setup_tar(ap, address);
510 if (retval != ERROR_OK)
511 break;
512
513 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
514 if (retval != ERROR_OK)
515 break;
516
517 nbytes -= this_size;
518 if (addrinc)
519 address += this_size;
520
521 mem_ap_update_tar_cache(ap);
522 }
523
524 if (retval == ERROR_OK)
525 retval = dap_run(dap);
526
527 /* Restore state */
528 address = adr;
529 nbytes = size * count;
530 read_ptr = read_buf;
531
532 /* If something failed, read TAR to find out how much data was successfully read, so we can
533 * at least give the caller what we have. */
534 if (retval != ERROR_OK) {
535 uint32_t tar;
536 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
537 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
538 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
539 if (nbytes > tar - address)
540 nbytes = tar - address;
541 } else {
542 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
543 nbytes = 0;
544 }
545 }
546
547 /* Replay loop to populate caller's buffer from the correct word and byte lane */
548 while (nbytes > 0) {
549 uint32_t this_size = size;
550
551 if (addrinc && ap->packed_transfers && nbytes >= 4
552 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
553 this_size = 4;
554 }
555
556 if (dap->ti_be_32_quirks) {
557 switch (this_size) {
558 case 4:
559 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
560 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
561 /* fallthrough */
562 case 2:
563 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
564 /* fallthrough */
565 case 1:
566 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
567 }
568 } else {
569 switch (this_size) {
570 case 4:
571 *buffer++ = *read_ptr >> 8 * (address++ & 3);
572 *buffer++ = *read_ptr >> 8 * (address++ & 3);
573 /* fallthrough */
574 case 2:
575 *buffer++ = *read_ptr >> 8 * (address++ & 3);
576 /* fallthrough */
577 case 1:
578 *buffer++ = *read_ptr >> 8 * (address++ & 3);
579 }
580 }
581
582 read_ptr++;
583 nbytes -= this_size;
584 }
585
586 free(read_buf);
587 return retval;
588 }
589
590 int mem_ap_read_buf(struct adiv5_ap *ap,
591 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
592 {
593 return mem_ap_read(ap, buffer, size, count, address, true);
594 }
595
596 int mem_ap_write_buf(struct adiv5_ap *ap,
597 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
598 {
599 return mem_ap_write(ap, buffer, size, count, address, true);
600 }
601
602 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
603 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
604 {
605 return mem_ap_read(ap, buffer, size, count, address, false);
606 }
607
608 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
609 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
610 {
611 return mem_ap_write(ap, buffer, size, count, address, false);
612 }
613
614 /*--------------------------------------------------------------------------*/
615
616
617 #define DAP_POWER_DOMAIN_TIMEOUT (10)
618
619 /*--------------------------------------------------------------------------*/
620
621 /**
622 * Invalidate cached DP select and cached TAR and CSW of all APs
623 */
624 void dap_invalidate_cache(struct adiv5_dap *dap)
625 {
626 dap->select = DP_SELECT_INVALID;
627 dap->last_read = NULL;
628
629 int i;
630 for (i = 0; i <= 255; i++) {
631 /* force csw and tar write on the next mem-ap access */
632 dap->ap[i].tar_valid = false;
633 dap->ap[i].csw_value = 0;
634 }
635 }
636
637 /**
638 * Initialize a DAP. This sets up the power domains, prepares the DP
639 * for further use and activates overrun checking.
640 *
641 * @param dap The DAP being initialized.
642 */
643 int dap_dp_init(struct adiv5_dap *dap)
644 {
645 int retval;
646
647 LOG_DEBUG("%s", adiv5_dap_name(dap));
648
649 dap_invalidate_cache(dap);
650
651 for (size_t i = 0; i < 30; i++) {
652 /* DP initialization */
653
654 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
655 if (retval == ERROR_OK)
656 break;
657 }
658
659 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
660 if (retval != ERROR_OK)
661 return retval;
662
663 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
664 if (retval != ERROR_OK)
665 return retval;
666
667 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
668 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
669 if (retval != ERROR_OK)
670 return retval;
671
672 /* Check that we have debug power domains activated */
673 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
674 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
675 CDBGPWRUPACK, CDBGPWRUPACK,
676 DAP_POWER_DOMAIN_TIMEOUT);
677 if (retval != ERROR_OK)
678 return retval;
679
680 if (!dap->ignore_syspwrupack) {
681 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
682 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
683 CSYSPWRUPACK, CSYSPWRUPACK,
684 DAP_POWER_DOMAIN_TIMEOUT);
685 if (retval != ERROR_OK)
686 return retval;
687 }
688
689 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
690 if (retval != ERROR_OK)
691 return retval;
692
693 /* With debug power on we can activate OVERRUN checking */
694 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
695 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
696 if (retval != ERROR_OK)
697 return retval;
698 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
699 if (retval != ERROR_OK)
700 return retval;
701
702 retval = dap_run(dap);
703 if (retval != ERROR_OK)
704 return retval;
705
706 return retval;
707 }
708
709 /**
710 * Initialize a DAP. This sets up the power domains, prepares the DP
711 * for further use, and arranges to use AP #0 for all AP operations
712 * until dap_ap-select() changes that policy.
713 *
714 * @param ap The MEM-AP being initialized.
715 */
716 int mem_ap_init(struct adiv5_ap *ap)
717 {
718 /* check that we support packed transfers */
719 uint32_t csw, cfg;
720 int retval;
721 struct adiv5_dap *dap = ap->dap;
722
723 ap->tar_valid = false;
724 ap->csw_value = 0; /* force csw and tar write */
725 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
726 if (retval != ERROR_OK)
727 return retval;
728
729 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
730 if (retval != ERROR_OK)
731 return retval;
732
733 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
734 if (retval != ERROR_OK)
735 return retval;
736
737 retval = dap_run(dap);
738 if (retval != ERROR_OK)
739 return retval;
740
741 if (csw & CSW_ADDRINC_PACKED)
742 ap->packed_transfers = true;
743 else
744 ap->packed_transfers = false;
745
746 /* Packed transfers on TI BE-32 processors do not work correctly in
747 * many cases. */
748 if (dap->ti_be_32_quirks)
749 ap->packed_transfers = false;
750
751 LOG_DEBUG("MEM_AP Packed Transfers: %s",
752 ap->packed_transfers ? "enabled" : "disabled");
753
754 /* The ARM ADI spec leaves implementation-defined whether unaligned
755 * memory accesses work, only work partially, or cause a sticky error.
756 * On TI BE-32 processors, reads seem to return garbage in some bytes
757 * and unaligned writes seem to cause a sticky error.
758 * TODO: it would be nice to have a way to detect whether unaligned
759 * operations are supported on other processors. */
760 ap->unaligned_access_bad = dap->ti_be_32_quirks;
761
762 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
763 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
764
765 return ERROR_OK;
766 }
767
768 /* CID interpretation -- see ARM IHI 0029B section 3
769 * and ARM IHI 0031A table 13-3.
770 */
771 static const char *class_description[16] = {
772 "Reserved", "ROM table", "Reserved", "Reserved",
773 "Reserved", "Reserved", "Reserved", "Reserved",
774 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
775 "Reserved", "OptimoDE DESS",
776 "Generic IP component", "PrimeCell or System component"
777 };
778
779 static bool is_dap_cid_ok(uint32_t cid)
780 {
781 return (cid & 0xffff0fff) == 0xb105000d;
782 }
783
784 /*
785 * This function checks the ID for each access port to find the requested Access Port type
786 */
787 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
788 {
789 int ap_num;
790
791 /* Maximum AP number is 255 since the SELECT register is 8 bits */
792 for (ap_num = 0; ap_num <= 255; ap_num++) {
793
794 /* read the IDR register of the Access Port */
795 uint32_t id_val = 0;
796
797 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
798 if (retval != ERROR_OK)
799 return retval;
800
801 retval = dap_run(dap);
802
803 /* IDR bits:
804 * 31-28 : Revision
805 * 27-24 : JEDEC bank (0x4 for ARM)
806 * 23-17 : JEDEC code (0x3B for ARM)
807 * 16-13 : Class (0b1000=Mem-AP)
808 * 12-8 : Reserved
809 * 7-4 : AP Variant (non-zero for JTAG-AP)
810 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
811 */
812
813 /* Reading register for a non-existant AP should not cause an error,
814 * but just to be sure, try to continue searching if an error does happen.
815 */
816 if ((retval == ERROR_OK) && /* Register read success */
817 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
818 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
819
820 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
821 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
822 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
823 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
824 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
825 ap_num, id_val);
826
827 *ap_out = &dap->ap[ap_num];
828 return ERROR_OK;
829 }
830 }
831
832 LOG_DEBUG("No %s found",
833 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
834 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
835 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
836 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
837 return ERROR_FAIL;
838 }
839
840 int dap_get_debugbase(struct adiv5_ap *ap,
841 uint32_t *dbgbase, uint32_t *apid)
842 {
843 struct adiv5_dap *dap = ap->dap;
844 int retval;
845
846 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
847 if (retval != ERROR_OK)
848 return retval;
849 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
850 if (retval != ERROR_OK)
851 return retval;
852 retval = dap_run(dap);
853 if (retval != ERROR_OK)
854 return retval;
855
856 return ERROR_OK;
857 }
858
859 int dap_lookup_cs_component(struct adiv5_ap *ap,
860 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
861 {
862 uint32_t romentry, entry_offset = 0, component_base, devtype;
863 int retval;
864
865 *addr = 0;
866
867 do {
868 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
869 entry_offset, &romentry);
870 if (retval != ERROR_OK)
871 return retval;
872
873 component_base = (dbgbase & 0xFFFFF000)
874 + (romentry & 0xFFFFF000);
875
876 if (romentry & 0x1) {
877 uint32_t c_cid1;
878 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
879 if (retval != ERROR_OK) {
880 LOG_ERROR("Can't read component with base address 0x%" PRIx32
881 ", the corresponding core might be turned off", component_base);
882 return retval;
883 }
884 if (((c_cid1 >> 4) & 0x0f) == 1) {
885 retval = dap_lookup_cs_component(ap, component_base,
886 type, addr, idx);
887 if (retval == ERROR_OK)
888 break;
889 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
890 return retval;
891 }
892
893 retval = mem_ap_read_atomic_u32(ap,
894 (component_base & 0xfffff000) | 0xfcc,
895 &devtype);
896 if (retval != ERROR_OK)
897 return retval;
898 if ((devtype & 0xff) == type) {
899 if (!*idx) {
900 *addr = component_base;
901 break;
902 } else
903 (*idx)--;
904 }
905 }
906 entry_offset += 4;
907 } while (romentry > 0);
908
909 if (!*addr)
910 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
911
912 return ERROR_OK;
913 }
914
915 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
916 {
917 assert((component_base & 0xFFF) == 0);
918 assert(ap != NULL && cid != NULL && pid != NULL);
919
920 uint32_t cid0, cid1, cid2, cid3;
921 uint32_t pid0, pid1, pid2, pid3, pid4;
922 int retval;
923
924 /* IDs are in last 4K section */
925 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
926 if (retval != ERROR_OK)
927 return retval;
928 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
929 if (retval != ERROR_OK)
930 return retval;
931 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
932 if (retval != ERROR_OK)
933 return retval;
934 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
935 if (retval != ERROR_OK)
936 return retval;
937 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
938 if (retval != ERROR_OK)
939 return retval;
940 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
941 if (retval != ERROR_OK)
942 return retval;
943 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
944 if (retval != ERROR_OK)
945 return retval;
946 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
947 if (retval != ERROR_OK)
948 return retval;
949 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
950 if (retval != ERROR_OK)
951 return retval;
952
953 retval = dap_run(ap->dap);
954 if (retval != ERROR_OK)
955 return retval;
956
957 *cid = (cid3 & 0xff) << 24
958 | (cid2 & 0xff) << 16
959 | (cid1 & 0xff) << 8
960 | (cid0 & 0xff);
961 *pid = (uint64_t)(pid4 & 0xff) << 32
962 | (pid3 & 0xff) << 24
963 | (pid2 & 0xff) << 16
964 | (pid1 & 0xff) << 8
965 | (pid0 & 0xff);
966
967 return ERROR_OK;
968 }
969
970 /* The designer identity code is encoded as:
971 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
972 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
973 * a legacy ASCII Identity Code.
974 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
975 * JEP106 is a standard available from jedec.org
976 */
977
978 /* Part number interpretations are from Cortex
979 * core specs, the CoreSight components TRM
980 * (ARM DDI 0314H), CoreSight System Design
981 * Guide (ARM DGI 0012D) and ETM specs; also
982 * from chip observation (e.g. TI SDTI).
983 */
984
985 /* The legacy code only used the part number field to identify CoreSight peripherals.
986 * This meant that the same part number from two different manufacturers looked the same.
987 * It is desirable for all future additions to identify with both part number and JEP106.
988 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
989 */
990
991 #define ANY_ID 0x1000
992
993 #define ARM_ID 0x4BB
994
995 static const struct {
996 uint16_t designer_id;
997 uint16_t part_num;
998 const char *type;
999 const char *full;
1000 } dap_partnums[] = {
1001 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1002 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1003 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1004 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1005 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1006 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1007 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1008 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1009 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1010 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1011 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1012 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1013 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1014 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1015 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1016 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1017 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1018 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1019 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1020 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1021 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1022 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1023 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1024 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1025 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1026 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1027 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1028 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1029 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1030 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1031 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1032 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1033 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1034 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1035 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1036 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1037 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1038 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1039 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1040 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1041 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1042 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1043 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1044 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1045 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1046 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1047 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1048 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1049 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1050 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1051 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1052 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1053 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1054 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1055 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1056 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1057 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1058 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1059 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1060 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1061 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1062 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1063 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1064 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1065 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1066 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1067 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1068 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1069 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1070 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1071 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1072 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1073 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1074 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1075 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1076 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1077 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1078 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1079 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1080 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1081 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1082 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1083 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1084 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1085 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1086 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1087 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1088 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1089 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1090 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1091 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1092 /* legacy comment: 0x113: what? */
1093 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1094 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1095 };
1096
1097 static int dap_rom_display(struct command_context *cmd_ctx,
1098 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1099 {
1100 int retval;
1101 uint64_t pid;
1102 uint32_t cid;
1103 char tabs[16] = "";
1104
1105 if (depth > 16) {
1106 command_print(cmd_ctx, "\tTables too deep");
1107 return ERROR_FAIL;
1108 }
1109
1110 if (depth)
1111 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1112
1113 uint32_t base_addr = dbgbase & 0xFFFFF000;
1114 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1115
1116 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1117 if (retval != ERROR_OK) {
1118 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1119 return ERROR_OK; /* Don't abort recursion */
1120 }
1121
1122 if (!is_dap_cid_ok(cid)) {
1123 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1124 return ERROR_OK; /* Don't abort recursion */
1125 }
1126
1127 /* component may take multiple 4K pages */
1128 uint32_t size = (pid >> 36) & 0xf;
1129 if (size > 0)
1130 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1131
1132 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1133
1134 uint8_t class = (cid >> 12) & 0xf;
1135 uint16_t part_num = pid & 0xfff;
1136 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1137
1138 if (designer_id & 0x80) {
1139 /* JEP106 code */
1140 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1141 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1142 } else {
1143 /* Legacy ASCII ID, clear invalid bits */
1144 designer_id &= 0x7f;
1145 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1146 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1147 }
1148
1149 /* default values to be overwritten upon finding a match */
1150 const char *type = "Unrecognized";
1151 const char *full = "";
1152
1153 /* search dap_partnums[] array for a match */
1154 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1155
1156 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1157 continue;
1158
1159 if (dap_partnums[entry].part_num != part_num)
1160 continue;
1161
1162 type = dap_partnums[entry].type;
1163 full = dap_partnums[entry].full;
1164 break;
1165 }
1166
1167 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1168 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1169
1170 if (class == 1) { /* ROM Table */
1171 uint32_t memtype;
1172 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1173 if (retval != ERROR_OK)
1174 return retval;
1175
1176 if (memtype & 0x01)
1177 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1178 else
1179 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1180
1181 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1182 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1183 uint32_t romentry;
1184 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1185 if (retval != ERROR_OK)
1186 return retval;
1187 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1188 tabs, entry_offset, romentry);
1189 if (romentry & 0x01) {
1190 /* Recurse */
1191 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1192 if (retval != ERROR_OK)
1193 return retval;
1194 } else if (romentry != 0) {
1195 command_print(cmd_ctx, "\t\tComponent not present");
1196 } else {
1197 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1198 break;
1199 }
1200 }
1201 } else if (class == 9) { /* CoreSight component */
1202 const char *major = "Reserved", *subtype = "Reserved";
1203
1204 uint32_t devtype;
1205 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1206 if (retval != ERROR_OK)
1207 return retval;
1208 unsigned minor = (devtype >> 4) & 0x0f;
1209 switch (devtype & 0x0f) {
1210 case 0:
1211 major = "Miscellaneous";
1212 switch (minor) {
1213 case 0:
1214 subtype = "other";
1215 break;
1216 case 4:
1217 subtype = "Validation component";
1218 break;
1219 }
1220 break;
1221 case 1:
1222 major = "Trace Sink";
1223 switch (minor) {
1224 case 0:
1225 subtype = "other";
1226 break;
1227 case 1:
1228 subtype = "Port";
1229 break;
1230 case 2:
1231 subtype = "Buffer";
1232 break;
1233 case 3:
1234 subtype = "Router";
1235 break;
1236 }
1237 break;
1238 case 2:
1239 major = "Trace Link";
1240 switch (minor) {
1241 case 0:
1242 subtype = "other";
1243 break;
1244 case 1:
1245 subtype = "Funnel, router";
1246 break;
1247 case 2:
1248 subtype = "Filter";
1249 break;
1250 case 3:
1251 subtype = "FIFO, buffer";
1252 break;
1253 }
1254 break;
1255 case 3:
1256 major = "Trace Source";
1257 switch (minor) {
1258 case 0:
1259 subtype = "other";
1260 break;
1261 case 1:
1262 subtype = "Processor";
1263 break;
1264 case 2:
1265 subtype = "DSP";
1266 break;
1267 case 3:
1268 subtype = "Engine/Coprocessor";
1269 break;
1270 case 4:
1271 subtype = "Bus";
1272 break;
1273 case 6:
1274 subtype = "Software";
1275 break;
1276 }
1277 break;
1278 case 4:
1279 major = "Debug Control";
1280 switch (minor) {
1281 case 0:
1282 subtype = "other";
1283 break;
1284 case 1:
1285 subtype = "Trigger Matrix";
1286 break;
1287 case 2:
1288 subtype = "Debug Auth";
1289 break;
1290 case 3:
1291 subtype = "Power Requestor";
1292 break;
1293 }
1294 break;
1295 case 5:
1296 major = "Debug Logic";
1297 switch (minor) {
1298 case 0:
1299 subtype = "other";
1300 break;
1301 case 1:
1302 subtype = "Processor";
1303 break;
1304 case 2:
1305 subtype = "DSP";
1306 break;
1307 case 3:
1308 subtype = "Engine/Coprocessor";
1309 break;
1310 case 4:
1311 subtype = "Bus";
1312 break;
1313 case 5:
1314 subtype = "Memory";
1315 break;
1316 }
1317 break;
1318 case 6:
1319 major = "Perfomance Monitor";
1320 switch (minor) {
1321 case 0:
1322 subtype = "other";
1323 break;
1324 case 1:
1325 subtype = "Processor";
1326 break;
1327 case 2:
1328 subtype = "DSP";
1329 break;
1330 case 3:
1331 subtype = "Engine/Coprocessor";
1332 break;
1333 case 4:
1334 subtype = "Bus";
1335 break;
1336 case 5:
1337 subtype = "Memory";
1338 break;
1339 }
1340 break;
1341 }
1342 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1343 (uint8_t)(devtype & 0xff),
1344 major, subtype);
1345 /* REVISIT also show 0xfc8 DevId */
1346 }
1347
1348 return ERROR_OK;
1349 }
1350
1351 int dap_info_command(struct command_context *cmd_ctx,
1352 struct adiv5_ap *ap)
1353 {
1354 int retval;
1355 uint32_t dbgbase, apid;
1356 uint8_t mem_ap;
1357
1358 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1359 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1360 if (retval != ERROR_OK)
1361 return retval;
1362
1363 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1364 if (apid == 0) {
1365 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1366 return ERROR_FAIL;
1367 }
1368
1369 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1370 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1371 command_print(cmd_ctx, "\tType is JTAG-AP");
1372 break;
1373 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1374 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1375 break;
1376 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1377 command_print(cmd_ctx, "\tType is MEM-AP APB");
1378 break;
1379 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1380 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1381 break;
1382 default:
1383 command_print(cmd_ctx, "\tUnknown AP type");
1384 break;
1385 }
1386
1387 /* NOTE: a MEM-AP may have a single CoreSight component that's
1388 * not a ROM table ... or have no such components at all.
1389 */
1390 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1391 if (mem_ap) {
1392 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1393
1394 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1395 command_print(cmd_ctx, "\tNo ROM table present");
1396 } else {
1397 if (dbgbase & 0x01)
1398 command_print(cmd_ctx, "\tValid ROM table present");
1399 else
1400 command_print(cmd_ctx, "\tROM table in legacy format");
1401
1402 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1403 }
1404 }
1405
1406 return ERROR_OK;
1407 }
1408
1409 enum adiv5_cfg_param {
1410 CFG_DAP,
1411 CFG_AP_NUM
1412 };
1413
1414 static const Jim_Nvp nvp_config_opts[] = {
1415 { .name = "-dap", .value = CFG_DAP },
1416 { .name = "-ap-num", .value = CFG_AP_NUM },
1417 { .name = NULL, .value = -1 }
1418 };
1419
1420 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1421 {
1422 struct adiv5_private_config *pc;
1423 int e;
1424
1425 pc = (struct adiv5_private_config *)target->private_config;
1426 if (pc == NULL) {
1427 pc = calloc(1, sizeof(struct adiv5_private_config));
1428 pc->ap_num = -1;
1429 target->private_config = pc;
1430 }
1431
1432 target->has_dap = true;
1433
1434 if (goi->argc > 0) {
1435 Jim_Nvp *n;
1436
1437 Jim_SetEmptyResult(goi->interp);
1438
1439 /* check first if topmost item is for us */
1440 e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts,
1441 goi->argv[0], &n);
1442 if (e != JIM_OK)
1443 return JIM_CONTINUE;
1444
1445 e = Jim_GetOpt_Obj(goi, NULL);
1446 if (e != JIM_OK)
1447 return e;
1448
1449 switch (n->value) {
1450 case CFG_DAP:
1451 if (goi->isconfigure) {
1452 Jim_Obj *o_t;
1453 struct adiv5_dap *dap;
1454 e = Jim_GetOpt_Obj(goi, &o_t);
1455 if (e != JIM_OK)
1456 return e;
1457 dap = dap_instance_by_jim_obj(goi->interp, o_t);
1458 if (dap == NULL) {
1459 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
1460 return JIM_ERR;
1461 }
1462 if (pc->dap != NULL && pc->dap != dap) {
1463 Jim_SetResultString(goi->interp,
1464 "DAP assignment cannot be changed after target was created!", -1);
1465 return JIM_ERR;
1466 }
1467 if (target->tap_configured) {
1468 Jim_SetResultString(goi->interp,
1469 "-chain-position and -dap configparams are mutually exclusive!", -1);
1470 return JIM_ERR;
1471 }
1472 pc->dap = dap;
1473 target->tap = dap->tap;
1474 target->dap_configured = true;
1475 } else {
1476 if (goi->argc != 0) {
1477 Jim_WrongNumArgs(goi->interp,
1478 goi->argc, goi->argv,
1479 "NO PARAMS");
1480 return JIM_ERR;
1481 }
1482
1483 if (pc->dap == NULL) {
1484 Jim_SetResultString(goi->interp, "DAP not configured", -1);
1485 return JIM_ERR;
1486 }
1487 Jim_SetResultString(goi->interp, adiv5_dap_name(pc->dap), -1);
1488 }
1489 break;
1490
1491 case CFG_AP_NUM:
1492 if (goi->isconfigure) {
1493 jim_wide ap_num;
1494 e = Jim_GetOpt_Wide(goi, &ap_num);
1495 if (e != JIM_OK)
1496 return e;
1497 pc->ap_num = ap_num;
1498 } else {
1499 if (goi->argc != 0) {
1500 Jim_WrongNumArgs(goi->interp,
1501 goi->argc, goi->argv,
1502 "NO PARAMS");
1503 return JIM_ERR;
1504 }
1505
1506 if (pc->ap_num < 0) {
1507 Jim_SetResultString(goi->interp, "AP number not configured", -1);
1508 return JIM_ERR;
1509 }
1510 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, (int)pc->ap_num));
1511 }
1512 break;
1513 }
1514 }
1515
1516 return JIM_OK;
1517 }
1518
1519 int adiv5_verify_config(struct adiv5_private_config *pc)
1520 {
1521 if (pc == NULL)
1522 return ERROR_FAIL;
1523
1524 if (pc->dap == NULL)
1525 return ERROR_FAIL;
1526
1527 return ERROR_OK;
1528 }
1529
1530
1531 COMMAND_HANDLER(handle_dap_info_command)
1532 {
1533 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1534 uint32_t apsel;
1535
1536 switch (CMD_ARGC) {
1537 case 0:
1538 apsel = dap->apsel;
1539 break;
1540 case 1:
1541 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1542 if (apsel >= 256)
1543 return ERROR_COMMAND_SYNTAX_ERROR;
1544 break;
1545 default:
1546 return ERROR_COMMAND_SYNTAX_ERROR;
1547 }
1548
1549 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1550 }
1551
1552 COMMAND_HANDLER(dap_baseaddr_command)
1553 {
1554 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1555 uint32_t apsel, baseaddr;
1556 int retval;
1557
1558 switch (CMD_ARGC) {
1559 case 0:
1560 apsel = dap->apsel;
1561 break;
1562 case 1:
1563 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1564 /* AP address is in bits 31:24 of DP_SELECT */
1565 if (apsel >= 256)
1566 return ERROR_COMMAND_SYNTAX_ERROR;
1567 break;
1568 default:
1569 return ERROR_COMMAND_SYNTAX_ERROR;
1570 }
1571
1572 /* NOTE: assumes we're talking to a MEM-AP, which
1573 * has a base address. There are other kinds of AP,
1574 * though they're not common for now. This should
1575 * use the ID register to verify it's a MEM-AP.
1576 */
1577 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1578 if (retval != ERROR_OK)
1579 return retval;
1580 retval = dap_run(dap);
1581 if (retval != ERROR_OK)
1582 return retval;
1583
1584 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1585
1586 return retval;
1587 }
1588
1589 COMMAND_HANDLER(dap_memaccess_command)
1590 {
1591 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1592 uint32_t memaccess_tck;
1593
1594 switch (CMD_ARGC) {
1595 case 0:
1596 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1597 break;
1598 case 1:
1599 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1600 break;
1601 default:
1602 return ERROR_COMMAND_SYNTAX_ERROR;
1603 }
1604 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1605
1606 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1607 dap->ap[dap->apsel].memaccess_tck);
1608
1609 return ERROR_OK;
1610 }
1611
1612 COMMAND_HANDLER(dap_apsel_command)
1613 {
1614 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1615 uint32_t apsel, apid;
1616 int retval;
1617
1618 switch (CMD_ARGC) {
1619 case 0:
1620 apsel = dap->apsel;
1621 break;
1622 case 1:
1623 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1624 /* AP address is in bits 31:24 of DP_SELECT */
1625 if (apsel >= 256)
1626 return ERROR_COMMAND_SYNTAX_ERROR;
1627 break;
1628 default:
1629 return ERROR_COMMAND_SYNTAX_ERROR;
1630 }
1631
1632 dap->apsel = apsel;
1633
1634 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1635 if (retval != ERROR_OK)
1636 return retval;
1637 retval = dap_run(dap);
1638 if (retval != ERROR_OK)
1639 return retval;
1640
1641 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1642 apsel, apid);
1643
1644 return retval;
1645 }
1646
1647 COMMAND_HANDLER(dap_apcsw_command)
1648 {
1649 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1650 uint32_t apcsw = dap->ap[dap->apsel].csw_default;
1651 uint32_t csw_val, csw_mask;
1652
1653 switch (CMD_ARGC) {
1654 case 0:
1655 command_print(CMD_CTX, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1656 dap->apsel, apcsw);
1657 return ERROR_OK;
1658 case 1:
1659 if (strcmp(CMD_ARGV[0], "default") == 0)
1660 csw_val = CSW_DEFAULT;
1661 else
1662 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1663
1664 if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1665 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
1666 return ERROR_COMMAND_SYNTAX_ERROR;
1667 }
1668 apcsw = csw_val;
1669 break;
1670 case 2:
1671 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1672 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
1673 if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1674 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
1675 return ERROR_COMMAND_SYNTAX_ERROR;
1676 }
1677 apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
1678 break;
1679 default:
1680 return ERROR_COMMAND_SYNTAX_ERROR;
1681 }
1682 dap->ap[dap->apsel].csw_default = apcsw;
1683
1684 return 0;
1685 }
1686
1687
1688
1689 COMMAND_HANDLER(dap_apid_command)
1690 {
1691 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1692 uint32_t apsel, apid;
1693 int retval;
1694
1695 switch (CMD_ARGC) {
1696 case 0:
1697 apsel = dap->apsel;
1698 break;
1699 case 1:
1700 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1701 /* AP address is in bits 31:24 of DP_SELECT */
1702 if (apsel >= 256)
1703 return ERROR_COMMAND_SYNTAX_ERROR;
1704 break;
1705 default:
1706 return ERROR_COMMAND_SYNTAX_ERROR;
1707 }
1708
1709 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1710 if (retval != ERROR_OK)
1711 return retval;
1712 retval = dap_run(dap);
1713 if (retval != ERROR_OK)
1714 return retval;
1715
1716 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1717
1718 return retval;
1719 }
1720
1721 COMMAND_HANDLER(dap_apreg_command)
1722 {
1723 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1724 uint32_t apsel, reg, value;
1725 int retval;
1726
1727 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1728 return ERROR_COMMAND_SYNTAX_ERROR;
1729
1730 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1731 /* AP address is in bits 31:24 of DP_SELECT */
1732 if (apsel >= 256)
1733 return ERROR_COMMAND_SYNTAX_ERROR;
1734
1735 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1736 if (reg >= 256 || (reg & 3))
1737 return ERROR_COMMAND_SYNTAX_ERROR;
1738
1739 if (CMD_ARGC == 3) {
1740 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1741 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1742 } else {
1743 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1744 }
1745 if (retval == ERROR_OK)
1746 retval = dap_run(dap);
1747
1748 if (retval != ERROR_OK)
1749 return retval;
1750
1751 if (CMD_ARGC == 2)
1752 command_print(CMD_CTX, "0x%08" PRIx32, value);
1753
1754 return retval;
1755 }
1756
1757 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1758 {
1759 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1760 uint32_t enable = dap->ti_be_32_quirks;
1761
1762 switch (CMD_ARGC) {
1763 case 0:
1764 break;
1765 case 1:
1766 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1767 if (enable > 1)
1768 return ERROR_COMMAND_SYNTAX_ERROR;
1769 break;
1770 default:
1771 return ERROR_COMMAND_SYNTAX_ERROR;
1772 }
1773 dap->ti_be_32_quirks = enable;
1774 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1775 enable ? "enabled" : "disabled");
1776
1777 return 0;
1778 }
1779
1780 const struct command_registration dap_instance_commands[] = {
1781 {
1782 .name = "info",
1783 .handler = handle_dap_info_command,
1784 .mode = COMMAND_EXEC,
1785 .help = "display ROM table for MEM-AP "
1786 "(default currently selected AP)",
1787 .usage = "[ap_num]",
1788 },
1789 {
1790 .name = "apsel",
1791 .handler = dap_apsel_command,
1792 .mode = COMMAND_EXEC,
1793 .help = "Set the currently selected AP (default 0) "
1794 "and display the result",
1795 .usage = "[ap_num]",
1796 },
1797 {
1798 .name = "apcsw",
1799 .handler = dap_apcsw_command,
1800 .mode = COMMAND_EXEC,
1801 .help = "Set CSW default bits",
1802 .usage = "[value [mask]]",
1803 },
1804
1805 {
1806 .name = "apid",
1807 .handler = dap_apid_command,
1808 .mode = COMMAND_EXEC,
1809 .help = "return ID register from AP "
1810 "(default currently selected AP)",
1811 .usage = "[ap_num]",
1812 },
1813 {
1814 .name = "apreg",
1815 .handler = dap_apreg_command,
1816 .mode = COMMAND_EXEC,
1817 .help = "read/write a register from AP "
1818 "(reg is byte address of a word register, like 0 4 8...)",
1819 .usage = "ap_num reg [value]",
1820 },
1821 {
1822 .name = "baseaddr",
1823 .handler = dap_baseaddr_command,
1824 .mode = COMMAND_EXEC,
1825 .help = "return debug base address from MEM-AP "
1826 "(default currently selected AP)",
1827 .usage = "[ap_num]",
1828 },
1829 {
1830 .name = "memaccess",
1831 .handler = dap_memaccess_command,
1832 .mode = COMMAND_EXEC,
1833 .help = "set/get number of extra tck for MEM-AP memory "
1834 "bus access [0-255]",
1835 .usage = "[cycles]",
1836 },
1837 {
1838 .name = "ti_be_32_quirks",
1839 .handler = dap_ti_be_32_quirks_command,
1840 .mode = COMMAND_CONFIG,
1841 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1842 .usage = "[enable]",
1843 },
1844 COMMAND_REGISTRATION_DONE
1845 };