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initial SWD transport (SWD infrastructure #2)
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
17 * *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
22 * *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
36 *
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45 *
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
56 */
57
58 /*
59 * Relevant specifications from ARM include:
60 *
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
63 *
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
66 */
67
68 #ifdef HAVE_CONFIG_H
69 #include "config.h"
70 #endif
71
72 #include "arm.h"
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
75
76
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
78
79 /*
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 */
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
84 {
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
86 }
87
88 /***************************************************************************
89 * *
90 * DP and MEM-AP register access through APACC and DPACC *
91 * *
92 ***************************************************************************/
93
94 /**
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
98 *
99 * @param dap The DAP
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
102 */
103 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
104 {
105 uint32_t select_apsel = (apsel << 24) & 0xFF000000;
106
107 if (select_apsel != dap->apsel)
108 {
109 dap->apsel = select_apsel;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
112 */
113 dap->ap_bank_value = -1;
114 dap->ap_csw_value = -1;
115 dap->ap_tar_value = -1;
116 }
117 }
118
119 /**
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
122 *
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
127 *
128 * @todo Rename to reflect it being specifically a MEM-AP function.
129 *
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
135 *
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
137 */
138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
139 {
140 int retval;
141
142 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
143 if (csw != dap->ap_csw_value)
144 {
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
147 if (retval != ERROR_OK)
148 return retval;
149 dap->ap_csw_value = csw;
150 }
151 if (tar != dap->ap_tar_value)
152 {
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
155 if (retval != ERROR_OK)
156 return retval;
157 dap->ap_tar_value = tar;
158 }
159 /* Disable TAR cache when autoincrementing */
160 if (csw & CSW_ADDRINC_MASK)
161 dap->ap_tar_value = -1;
162 return ERROR_OK;
163 }
164
165 /**
166 * Asynchronous (queued) read of a word from memory or a system register.
167 *
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
173 *
174 * @return ERROR_OK for success. Otherwise a fault code.
175 */
176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
177 uint32_t *value)
178 {
179 int retval;
180
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
183 */
184 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
185 address & 0xFFFFFFF0);
186 if (retval != ERROR_OK)
187 return retval;
188
189 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
190 }
191
192 /**
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
195 *
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
200 *
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
203 */
204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
205 uint32_t *value)
206 {
207 int retval;
208
209 retval = mem_ap_read_u32(dap, address, value);
210 if (retval != ERROR_OK)
211 return retval;
212
213 return dap_run(dap);
214 }
215
216 /**
217 * Asynchronous (queued) write of a word to memory or a system register.
218 *
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
224 *
225 * @return ERROR_OK for success. Otherwise a fault code.
226 */
227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
228 uint32_t value)
229 {
230 int retval;
231
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
234 */
235 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
236 address & 0xFFFFFFF0);
237 if (retval != ERROR_OK)
238 return retval;
239
240 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
241 value);
242 }
243
244 /**
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
247 *
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
252 *
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
254 */
255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
256 uint32_t value)
257 {
258 int retval = mem_ap_write_u32(dap, address, value);
259
260 if (retval != ERROR_OK)
261 return retval;
262
263 return dap_run(dap);
264 }
265
266 /*****************************************************************************
267 * *
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
269 * *
270 * Write a buffer in target order (little endian) *
271 * *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
274 {
275 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
276 uint32_t adr = address;
277 uint8_t* pBuffer = buffer;
278
279 count >>= 2;
280 wcount = count;
281
282 /* if we have an unaligned access - reorder data */
283 if (adr & 0x3u)
284 {
285 for (writecount = 0; writecount < count; writecount++)
286 {
287 int i;
288 uint32_t outvalue;
289 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
290
291 for (i = 0; i < 4; i++)
292 {
293 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
294 outvalue >>= 8;
295 adr++;
296 }
297 pBuffer += sizeof(uint32_t);
298 }
299 }
300
301 while (wcount > 0)
302 {
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
305 if (wcount < blocksize)
306 blocksize = wcount;
307
308 /* handle unaligned data at 4k boundary */
309 if (blocksize == 0)
310 blocksize = 1;
311
312 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
313 if (retval != ERROR_OK)
314 return retval;
315
316 for (writecount = 0; writecount < blocksize; writecount++)
317 {
318 retval = dap_queue_ap_write(dap, AP_REG_DRW,
319 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
320 if (retval != ERROR_OK)
321 break;
322 }
323
324 if ((retval = dap_run(dap)) == ERROR_OK)
325 {
326 wcount = wcount - blocksize;
327 address = address + 4 * blocksize;
328 buffer = buffer + 4 * blocksize;
329 }
330 else
331 {
332 errorcount++;
333 }
334
335 if (errorcount > 1)
336 {
337 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
338 return retval;
339 }
340 }
341
342 return retval;
343 }
344
345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
346 uint8_t *buffer, int count, uint32_t address)
347 {
348 int retval = ERROR_OK;
349 int wcount, blocksize, writecount, i;
350
351 wcount = count >> 1;
352
353 while (wcount > 0)
354 {
355 int nbytes;
356
357 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
358 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
359
360 if (wcount < blocksize)
361 blocksize = wcount;
362
363 /* handle unaligned data at 4k boundary */
364 if (blocksize == 0)
365 blocksize = 1;
366
367 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
368 if (retval != ERROR_OK)
369 return retval;
370 writecount = blocksize;
371
372 do
373 {
374 nbytes = MIN((writecount << 1), 4);
375
376 if (nbytes < 4)
377 {
378 retval = mem_ap_write_buf_u16(dap, buffer,
379 nbytes, address);
380 if (retval != ERROR_OK)
381 {
382 LOG_WARNING("Block write error address "
383 "0x%" PRIx32 ", count 0x%x",
384 address, count);
385 return retval;
386 }
387
388 address += nbytes >> 1;
389 }
390 else
391 {
392 uint32_t outvalue;
393 memcpy(&outvalue, buffer, sizeof(uint32_t));
394
395 for (i = 0; i < nbytes; i++)
396 {
397 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
398 outvalue >>= 8;
399 address++;
400 }
401
402 memcpy(&outvalue, buffer, sizeof(uint32_t));
403 retval = dap_queue_ap_write(dap,
404 AP_REG_DRW, outvalue);
405 if (retval != ERROR_OK)
406 break;
407
408 if ((retval = dap_run(dap)) != ERROR_OK)
409 {
410 LOG_WARNING("Block write error address "
411 "0x%" PRIx32 ", count 0x%x",
412 address, count);
413 return retval;
414 }
415 }
416
417 buffer += nbytes >> 1;
418 writecount -= nbytes >> 1;
419
420 } while (writecount);
421 wcount -= blocksize;
422 }
423
424 return retval;
425 }
426
427 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
428 {
429 int retval = ERROR_OK;
430
431 if (count >= 4)
432 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
433
434 while (count > 0)
435 {
436 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
437 if (retval != ERROR_OK)
438 return retval;
439 uint16_t svalue;
440 memcpy(&svalue, buffer, sizeof(uint16_t));
441 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
442 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
443 if (retval != ERROR_OK)
444 break;
445
446 retval = dap_run(dap);
447 if (retval != ERROR_OK)
448 break;
449
450 count -= 2;
451 address += 2;
452 buffer += 2;
453 }
454
455 return retval;
456 }
457
458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
459 uint8_t *buffer, int count, uint32_t address)
460 {
461 int retval = ERROR_OK;
462 int wcount, blocksize, writecount, i;
463
464 wcount = count;
465
466 while (wcount > 0)
467 {
468 int nbytes;
469
470 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
471 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
472
473 if (wcount < blocksize)
474 blocksize = wcount;
475
476 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
477 if (retval != ERROR_OK)
478 return retval;
479 writecount = blocksize;
480
481 do
482 {
483 nbytes = MIN(writecount, 4);
484
485 if (nbytes < 4)
486 {
487 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
488 if (retval != ERROR_OK)
489 {
490 LOG_WARNING("Block write error address "
491 "0x%" PRIx32 ", count 0x%x",
492 address, count);
493 return retval;
494 }
495
496 address += nbytes;
497 }
498 else
499 {
500 uint32_t outvalue;
501 memcpy(&outvalue, buffer, sizeof(uint32_t));
502
503 for (i = 0; i < nbytes; i++)
504 {
505 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
506 outvalue >>= 8;
507 address++;
508 }
509
510 memcpy(&outvalue, buffer, sizeof(uint32_t));
511 retval = dap_queue_ap_write(dap,
512 AP_REG_DRW, outvalue);
513 if (retval != ERROR_OK)
514 break;
515
516 if ((retval = dap_run(dap)) != ERROR_OK)
517 {
518 LOG_WARNING("Block write error address "
519 "0x%" PRIx32 ", count 0x%x",
520 address, count);
521 return retval;
522 }
523 }
524
525 buffer += nbytes;
526 writecount -= nbytes;
527
528 } while (writecount);
529 wcount -= blocksize;
530 }
531
532 return retval;
533 }
534
535 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
536 {
537 int retval = ERROR_OK;
538
539 if (count >= 4)
540 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
541
542 while (count > 0)
543 {
544 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
545 if (retval != ERROR_OK)
546 return retval;
547 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
548 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
549 if (retval != ERROR_OK)
550 break;
551
552 retval = dap_run(dap);
553 if (retval != ERROR_OK)
554 break;
555
556 count--;
557 address++;
558 buffer++;
559 }
560
561 return retval;
562 }
563
564 /* FIXME don't import ... this is a temporary workaround for the
565 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
566 */
567 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
568 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
569 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
570
571 /**
572 * Synchronously read a block of 32-bit words into a buffer
573 * @param dap The DAP connected to the MEM-AP.
574 * @param buffer where the words will be stored (in host byte order).
575 * @param count How many words to read.
576 * @param address Memory address from which to read words; all the
577 * words must be readable by the currently selected MEM-AP.
578 */
579 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
580 int count, uint32_t address)
581 {
582 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
583 uint32_t adr = address;
584 uint8_t* pBuffer = buffer;
585
586 count >>= 2;
587 wcount = count;
588
589 while (wcount > 0)
590 {
591 /* Adjust to read blocks within boundaries aligned to the
592 * TAR autoincrement size (at least 2^10). Autoincrement
593 * mode avoids an extra per-word roundtrip to update TAR.
594 */
595 blocksize = max_tar_block_size(dap->tar_autoincr_block,
596 address);
597 if (wcount < blocksize)
598 blocksize = wcount;
599
600 /* handle unaligned data at 4k boundary */
601 if (blocksize == 0)
602 blocksize = 1;
603
604 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
605 address);
606 if (retval != ERROR_OK)
607 return retval;
608
609 /* FIXME remove these three calls to adi_jtag_dp_scan(),
610 * so this routine becomes transport-neutral. Be careful
611 * not to cause performance problems with JTAG; would it
612 * suffice to loop over dap_queue_ap_read(), or would that
613 * be slower when JTAG is the chosen transport?
614 */
615
616 /* Scan out first read */
617 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
618 DPAP_READ, 0, NULL, NULL);
619 if (retval != ERROR_OK)
620 return retval;
621 for (readcount = 0; readcount < blocksize - 1; readcount++)
622 {
623 /* Scan out next read; scan in posted value for the
624 * previous one. Assumes read is acked "OK/FAULT",
625 * and CTRL_STAT says that meant "OK".
626 */
627 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
628 DPAP_READ, 0, buffer + 4 * readcount,
629 &dap->ack);
630 if (retval != ERROR_OK)
631 return retval;
632 }
633
634 /* Scan in last posted value; RDBUFF has no other effect,
635 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
636 */
637 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
638 DPAP_READ, 0, buffer + 4 * readcount,
639 &dap->ack);
640 if (retval != ERROR_OK)
641 return retval;
642
643 retval = dap_run(dap);
644 if (retval != ERROR_OK)
645 {
646 errorcount++;
647 if (errorcount <= 1)
648 {
649 /* try again */
650 continue;
651 }
652 LOG_WARNING("Block read error address 0x%" PRIx32, address);
653 return retval;
654 }
655 wcount = wcount - blocksize;
656 address += 4 * blocksize;
657 buffer += 4 * blocksize;
658 }
659
660 /* if we have an unaligned access - reorder data */
661 if (adr & 0x3u)
662 {
663 for (readcount = 0; readcount < count; readcount++)
664 {
665 int i;
666 uint32_t data;
667 memcpy(&data, pBuffer, sizeof(uint32_t));
668
669 for (i = 0; i < 4; i++)
670 {
671 *((uint8_t*)pBuffer) =
672 (data >> 8 * (adr & 0x3));
673 pBuffer++;
674 adr++;
675 }
676 }
677 }
678
679 return retval;
680 }
681
682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
683 uint8_t *buffer, int count, uint32_t address)
684 {
685 uint32_t invalue;
686 int retval = ERROR_OK;
687 int wcount, blocksize, readcount, i;
688
689 wcount = count >> 1;
690
691 while (wcount > 0)
692 {
693 int nbytes;
694
695 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
696 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
697 if (wcount < blocksize)
698 blocksize = wcount;
699
700 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
701 if (retval != ERROR_OK)
702 return retval;
703
704 /* handle unaligned data at 4k boundary */
705 if (blocksize == 0)
706 blocksize = 1;
707 readcount = blocksize;
708
709 do
710 {
711 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
712 if (retval != ERROR_OK)
713 return retval;
714 if ((retval = dap_run(dap)) != ERROR_OK)
715 {
716 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
717 return retval;
718 }
719
720 nbytes = MIN((readcount << 1), 4);
721
722 for (i = 0; i < nbytes; i++)
723 {
724 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
725 buffer++;
726 address++;
727 }
728
729 readcount -= (nbytes >> 1);
730 } while (readcount);
731 wcount -= blocksize;
732 }
733
734 return retval;
735 }
736
737 /**
738 * Synchronously read a block of 16-bit halfwords into a buffer
739 * @param dap The DAP connected to the MEM-AP.
740 * @param buffer where the halfwords will be stored (in host byte order).
741 * @param count How many halfwords to read.
742 * @param address Memory address from which to read words; all the
743 * words must be readable by the currently selected MEM-AP.
744 */
745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
746 int count, uint32_t address)
747 {
748 uint32_t invalue, i;
749 int retval = ERROR_OK;
750
751 if (count >= 4)
752 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
753
754 while (count > 0)
755 {
756 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
757 if (retval != ERROR_OK)
758 return retval;
759 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
760 if (retval != ERROR_OK)
761 break;
762
763 retval = dap_run(dap);
764 if (retval != ERROR_OK)
765 break;
766
767 if (address & 0x1)
768 {
769 for (i = 0; i < 2; i++)
770 {
771 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
772 buffer++;
773 address++;
774 }
775 }
776 else
777 {
778 uint16_t svalue = (invalue >> 8 * (address & 0x3));
779 memcpy(buffer, &svalue, sizeof(uint16_t));
780 address += 2;
781 buffer += 2;
782 }
783 count -= 2;
784 }
785
786 return retval;
787 }
788
789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
790 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
791 *
792 * The solution is to arrange for a large out/in scan in this loop and
793 * and convert data afterwards.
794 */
795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
796 uint8_t *buffer, int count, uint32_t address)
797 {
798 uint32_t invalue;
799 int retval = ERROR_OK;
800 int wcount, blocksize, readcount, i;
801
802 wcount = count;
803
804 while (wcount > 0)
805 {
806 int nbytes;
807
808 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
809 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
810
811 if (wcount < blocksize)
812 blocksize = wcount;
813
814 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
815 if (retval != ERROR_OK)
816 return retval;
817 readcount = blocksize;
818
819 do
820 {
821 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
822 if (retval != ERROR_OK)
823 return retval;
824 if ((retval = dap_run(dap)) != ERROR_OK)
825 {
826 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
827 return retval;
828 }
829
830 nbytes = MIN(readcount, 4);
831
832 for (i = 0; i < nbytes; i++)
833 {
834 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
835 buffer++;
836 address++;
837 }
838
839 readcount -= nbytes;
840 } while (readcount);
841 wcount -= blocksize;
842 }
843
844 return retval;
845 }
846
847 /**
848 * Synchronously read a block of bytes into a buffer
849 * @param dap The DAP connected to the MEM-AP.
850 * @param buffer where the bytes will be stored.
851 * @param count How many bytes to read.
852 * @param address Memory address from which to read data; all the
853 * data must be readable by the currently selected MEM-AP.
854 */
855 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
856 int count, uint32_t address)
857 {
858 uint32_t invalue;
859 int retval = ERROR_OK;
860
861 if (count >= 4)
862 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
863
864 while (count > 0)
865 {
866 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
867 if (retval != ERROR_OK)
868 return retval;
869 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
870 if (retval != ERROR_OK)
871 return retval;
872 retval = dap_run(dap);
873 if (retval != ERROR_OK)
874 break;
875
876 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
877 count--;
878 address++;
879 buffer++;
880 }
881
882 return retval;
883 }
884
885 /*--------------------------------------------------------------------------*/
886
887
888 /* FIXME don't import ... just initialize as
889 * part of DAP transport setup
890 */
891 extern const struct dap_ops jtag_dp_ops;
892
893 /*--------------------------------------------------------------------------*/
894
895 /**
896 * Initialize a DAP. This sets up the power domains, prepares the DP
897 * for further use, and arranges to use AP #0 for all AP operations
898 * until dap_ap-select() changes that policy.
899 *
900 * @param dap The DAP being initialized.
901 *
902 * @todo Rename this. We also need an initialization scheme which account
903 * for SWD transports not just JTAG; that will need to address differences
904 * in layering. (JTAG is useful without any debug target; but not SWD.)
905 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
906 */
907 int ahbap_debugport_init(struct adiv5_dap *dap)
908 {
909 uint32_t dummy;
910 uint32_t ctrlstat;
911 int cnt = 0;
912 int retval;
913
914 LOG_DEBUG(" ");
915
916 /* JTAG-DP or SWJ-DP, in JTAG mode
917 * ... for SWD mode this is patched as part
918 * of link switchover
919 */
920 if (!dap->ops)
921 dap->ops = &jtag_dp_ops;
922
923 /* Default MEM-AP setup.
924 *
925 * REVISIT AP #0 may be an inappropriate default for this.
926 * Should we probe, or take a hint from the caller?
927 * Presumably we can ignore the possibility of multiple APs.
928 */
929 dap->apsel = !0;
930 dap_ap_select(dap, 0);
931
932 /* DP initialization */
933
934 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
935 if (retval != ERROR_OK)
936 return retval;
937
938 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
939 if (retval != ERROR_OK)
940 return retval;
941
942 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
943 if (retval != ERROR_OK)
944 return retval;
945
946 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
947 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
948 if (retval != ERROR_OK)
949 return retval;
950
951 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
952 if (retval != ERROR_OK)
953 return retval;
954 if ((retval = dap_run(dap)) != ERROR_OK)
955 return retval;
956
957 /* Check that we have debug power domains activated */
958 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
959 {
960 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
961 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
962 if (retval != ERROR_OK)
963 return retval;
964 if ((retval = dap_run(dap)) != ERROR_OK)
965 return retval;
966 alive_sleep(10);
967 }
968
969 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
970 {
971 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
972 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
973 if (retval != ERROR_OK)
974 return retval;
975 if ((retval = dap_run(dap)) != ERROR_OK)
976 return retval;
977 alive_sleep(10);
978 }
979
980 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
981 if (retval != ERROR_OK)
982 return retval;
983 /* With debug power on we can activate OVERRUN checking */
984 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
985 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
986 if (retval != ERROR_OK)
987 return retval;
988 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
989 if (retval != ERROR_OK)
990 return retval;
991
992 return ERROR_OK;
993 }
994
995 /* CID interpretation -- see ARM IHI 0029B section 3
996 * and ARM IHI 0031A table 13-3.
997 */
998 static const char *class_description[16] ={
999 "Reserved", "ROM table", "Reserved", "Reserved",
1000 "Reserved", "Reserved", "Reserved", "Reserved",
1001 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1002 "Reserved", "OptimoDE DESS",
1003 "Generic IP component", "PrimeCell or System component"
1004 };
1005
1006 static bool
1007 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1008 {
1009 return cid3 == 0xb1 && cid2 == 0x05
1010 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1011 }
1012
1013 struct broken_cpu {
1014 uint32_t dbgbase;
1015 uint32_t apid;
1016 uint32_t correct_dbgbase;
1017 char *model;
1018 } broken_cpus[] = {
1019 { 0x80000000, 0x04770002, 0x60000000, "imx51" },
1020 };
1021
1022 int dap_get_debugbase(struct adiv5_dap *dap, int apsel,
1023 uint32_t *out_dbgbase, uint32_t *out_apid)
1024 {
1025 uint32_t apselold;
1026 int retval;
1027 unsigned int i;
1028 uint32_t dbgbase, apid;
1029
1030 /* AP address is in bits 31:24 of DP_SELECT */
1031 if (apsel >= 256)
1032 return ERROR_INVALID_ARGUMENTS;
1033
1034 apselold = dap->apsel;
1035 dap_ap_select(dap, apsel);
1036
1037 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1038 if (retval != ERROR_OK)
1039 return retval;
1040 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1041 if (retval != ERROR_OK)
1042 return retval;
1043 retval = dap_run(dap);
1044 if (retval != ERROR_OK)
1045 return retval;
1046
1047 /* Some CPUs are messed up, so fixup if needed. */
1048 for (i = 0; i < sizeof(broken_cpus)/sizeof(struct broken_cpu); i++)
1049 if (broken_cpus[i].dbgbase == dbgbase &&
1050 broken_cpus[i].apid == apid) {
1051 LOG_WARNING("Found broken CPU (%s), trying to fixup "
1052 "ROM Table location from 0x%08x to 0x%08x",
1053 broken_cpus[i].model, dbgbase,
1054 broken_cpus[i].correct_dbgbase);
1055 dbgbase = broken_cpus[i].correct_dbgbase;
1056 break;
1057 }
1058
1059 dap_ap_select(dap, apselold);
1060
1061 /* The asignment happens only here to prevent modification of these
1062 * values before they are certain. */
1063 *out_dbgbase = dbgbase;
1064 *out_apid = apid;
1065
1066 return ERROR_OK;
1067 }
1068
1069 int dap_lookup_cs_component(struct adiv5_dap *dap, int apsel,
1070 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1071 {
1072 uint32_t apselold;
1073 uint32_t romentry, entry_offset = 0, component_base, devtype;
1074 int retval = ERROR_FAIL;
1075
1076 if (apsel >= 256)
1077 return ERROR_INVALID_ARGUMENTS;
1078
1079 apselold = dap->apsel;
1080 dap_ap_select(dap, apsel);
1081
1082 do
1083 {
1084 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1085 entry_offset, &romentry);
1086 if (retval != ERROR_OK)
1087 return retval;
1088
1089 component_base = (dbgbase & 0xFFFFF000)
1090 + (romentry & 0xFFFFF000);
1091
1092 if (romentry & 0x1) {
1093 retval = mem_ap_read_atomic_u32(dap,
1094 (component_base & 0xfffff000) | 0xfcc,
1095 &devtype);
1096 if ((devtype & 0xff) == type) {
1097 *addr = component_base;
1098 retval = ERROR_OK;
1099 break;
1100 }
1101 }
1102 entry_offset += 4;
1103 } while (romentry > 0);
1104
1105 dap_ap_select(dap, apselold);
1106
1107 return retval;
1108 }
1109
1110 static int dap_info_command(struct command_context *cmd_ctx,
1111 struct adiv5_dap *dap, int apsel)
1112 {
1113 int retval;
1114 uint32_t dbgbase, apid;
1115 int romtable_present = 0;
1116 uint8_t mem_ap;
1117 uint32_t apselold;
1118
1119 retval = dap_get_debugbase(dap, apsel, &dbgbase, &apid);
1120 if (retval != ERROR_OK)
1121 return retval;
1122
1123 apselold = dap->apsel;
1124 dap_ap_select(dap, apsel);
1125
1126 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1127 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1128 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1129 if (apid)
1130 {
1131 switch (apid&0x0F)
1132 {
1133 case 0:
1134 command_print(cmd_ctx, "\tType is JTAG-AP");
1135 break;
1136 case 1:
1137 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1138 break;
1139 case 2:
1140 command_print(cmd_ctx, "\tType is MEM-AP APB");
1141 break;
1142 default:
1143 command_print(cmd_ctx, "\tUnknown AP type");
1144 break;
1145 }
1146
1147 /* NOTE: a MEM-AP may have a single CoreSight component that's
1148 * not a ROM table ... or have no such components at all.
1149 */
1150 if (mem_ap)
1151 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1152 dbgbase);
1153 }
1154 else
1155 {
1156 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1157 }
1158
1159 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1160 if (romtable_present)
1161 {
1162 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1163 uint16_t entry_offset;
1164
1165 /* bit 16 of apid indicates a memory access port */
1166 if (dbgbase & 0x02)
1167 command_print(cmd_ctx, "\tValid ROM table present");
1168 else
1169 command_print(cmd_ctx, "\tROM table in legacy format");
1170
1171 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1172 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1173 if (retval != ERROR_OK)
1174 return retval;
1175 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1176 if (retval != ERROR_OK)
1177 return retval;
1178 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1179 if (retval != ERROR_OK)
1180 return retval;
1181 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1182 if (retval != ERROR_OK)
1183 return retval;
1184 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1185 if (retval != ERROR_OK)
1186 return retval;
1187 retval = dap_run(dap);
1188 if (retval != ERROR_OK)
1189 return retval;
1190
1191 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1192 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1193 ", CID2 0x%2.2x"
1194 ", CID1 0x%2.2x"
1195 ", CID0 0x%2.2x",
1196 (unsigned) cid3, (unsigned)cid2,
1197 (unsigned) cid1, (unsigned) cid0);
1198 if (memtype & 0x01)
1199 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1200 else
1201 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1202 "Dedicated debug bus.");
1203
1204 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1205 entry_offset = 0;
1206 do
1207 {
1208 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1209 if (retval != ERROR_OK)
1210 return retval;
1211 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1212 if (romentry&0x01)
1213 {
1214 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1215 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1216 uint32_t component_base;
1217 unsigned part_num;
1218 char *type, *full;
1219
1220 component_base = (dbgbase & 0xFFFFF000)
1221 + (romentry & 0xFFFFF000);
1222
1223 /* IDs are in last 4K section */
1224
1225
1226 retval = mem_ap_read_atomic_u32(dap,
1227 component_base + 0xFE0, &c_pid0);
1228 if (retval != ERROR_OK)
1229 return retval;
1230 c_pid0 &= 0xff;
1231 retval = mem_ap_read_atomic_u32(dap,
1232 component_base + 0xFE4, &c_pid1);
1233 if (retval != ERROR_OK)
1234 return retval;
1235 c_pid1 &= 0xff;
1236 retval = mem_ap_read_atomic_u32(dap,
1237 component_base + 0xFE8, &c_pid2);
1238 if (retval != ERROR_OK)
1239 return retval;
1240 c_pid2 &= 0xff;
1241 retval = mem_ap_read_atomic_u32(dap,
1242 component_base + 0xFEC, &c_pid3);
1243 if (retval != ERROR_OK)
1244 return retval;
1245 c_pid3 &= 0xff;
1246 retval = mem_ap_read_atomic_u32(dap,
1247 component_base + 0xFD0, &c_pid4);
1248 if (retval != ERROR_OK)
1249 return retval;
1250 c_pid4 &= 0xff;
1251
1252 retval = mem_ap_read_atomic_u32(dap,
1253 component_base + 0xFF0, &c_cid0);
1254 if (retval != ERROR_OK)
1255 return retval;
1256 c_cid0 &= 0xff;
1257 retval = mem_ap_read_atomic_u32(dap,
1258 component_base + 0xFF4, &c_cid1);
1259 if (retval != ERROR_OK)
1260 return retval;
1261 c_cid1 &= 0xff;
1262 retval = mem_ap_read_atomic_u32(dap,
1263 component_base + 0xFF8, &c_cid2);
1264 if (retval != ERROR_OK)
1265 return retval;
1266 c_cid2 &= 0xff;
1267 retval = mem_ap_read_atomic_u32(dap,
1268 component_base + 0xFFC, &c_cid3);
1269 if (retval != ERROR_OK)
1270 return retval;
1271 c_cid3 &= 0xff;
1272
1273
1274 command_print(cmd_ctx,
1275 "\t\tComponent base address 0x%" PRIx32
1276 ", start address 0x%" PRIx32,
1277 component_base,
1278 /* component may take multiple 4K pages */
1279 component_base - 0x1000*(c_pid4 >> 4));
1280 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1281 (int) (c_cid1 >> 4) & 0xf,
1282 /* See ARM IHI 0029B Table 3-3 */
1283 class_description[(c_cid1 >> 4) & 0xf]);
1284
1285 /* CoreSight component? */
1286 if (((c_cid1 >> 4) & 0x0f) == 9) {
1287 uint32_t devtype;
1288 unsigned minor;
1289 char *major = "Reserved", *subtype = "Reserved";
1290
1291 retval = mem_ap_read_atomic_u32(dap,
1292 (component_base & 0xfffff000) | 0xfcc,
1293 &devtype);
1294 if (retval != ERROR_OK)
1295 return retval;
1296 minor = (devtype >> 4) & 0x0f;
1297 switch (devtype & 0x0f) {
1298 case 0:
1299 major = "Miscellaneous";
1300 switch (minor) {
1301 case 0:
1302 subtype = "other";
1303 break;
1304 case 4:
1305 subtype = "Validation component";
1306 break;
1307 }
1308 break;
1309 case 1:
1310 major = "Trace Sink";
1311 switch (minor) {
1312 case 0:
1313 subtype = "other";
1314 break;
1315 case 1:
1316 subtype = "Port";
1317 break;
1318 case 2:
1319 subtype = "Buffer";
1320 break;
1321 }
1322 break;
1323 case 2:
1324 major = "Trace Link";
1325 switch (minor) {
1326 case 0:
1327 subtype = "other";
1328 break;
1329 case 1:
1330 subtype = "Funnel, router";
1331 break;
1332 case 2:
1333 subtype = "Filter";
1334 break;
1335 case 3:
1336 subtype = "FIFO, buffer";
1337 break;
1338 }
1339 break;
1340 case 3:
1341 major = "Trace Source";
1342 switch (minor) {
1343 case 0:
1344 subtype = "other";
1345 break;
1346 case 1:
1347 subtype = "Processor";
1348 break;
1349 case 2:
1350 subtype = "DSP";
1351 break;
1352 case 3:
1353 subtype = "Engine/Coprocessor";
1354 break;
1355 case 4:
1356 subtype = "Bus";
1357 break;
1358 }
1359 break;
1360 case 4:
1361 major = "Debug Control";
1362 switch (minor) {
1363 case 0:
1364 subtype = "other";
1365 break;
1366 case 1:
1367 subtype = "Trigger Matrix";
1368 break;
1369 case 2:
1370 subtype = "Debug Auth";
1371 break;
1372 }
1373 break;
1374 case 5:
1375 major = "Debug Logic";
1376 switch (minor) {
1377 case 0:
1378 subtype = "other";
1379 break;
1380 case 1:
1381 subtype = "Processor";
1382 break;
1383 case 2:
1384 subtype = "DSP";
1385 break;
1386 case 3:
1387 subtype = "Engine/Coprocessor";
1388 break;
1389 }
1390 break;
1391 }
1392 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1393 (unsigned) (devtype & 0xff),
1394 major, subtype);
1395 /* REVISIT also show 0xfc8 DevId */
1396 }
1397
1398 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1399 command_print(cmd_ctx,
1400 "\t\tCID3 0%2.2x"
1401 ", CID2 0%2.2x"
1402 ", CID1 0%2.2x"
1403 ", CID0 0%2.2x",
1404 (int) c_cid3,
1405 (int) c_cid2,
1406 (int)c_cid1,
1407 (int)c_cid0);
1408 command_print(cmd_ctx,
1409 "\t\tPeripheral ID[4..0] = hex "
1410 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1411 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1412 (int) c_pid1, (int) c_pid0);
1413
1414 /* Part number interpretations are from Cortex
1415 * core specs, the CoreSight components TRM
1416 * (ARM DDI 0314H), and ETM specs; also from
1417 * chip observation (e.g. TI SDTI).
1418 */
1419 part_num = (c_pid0 & 0xff);
1420 part_num |= (c_pid1 & 0x0f) << 8;
1421 switch (part_num) {
1422 case 0x000:
1423 type = "Cortex-M3 NVIC";
1424 full = "(Interrupt Controller)";
1425 break;
1426 case 0x001:
1427 type = "Cortex-M3 ITM";
1428 full = "(Instrumentation Trace Module)";
1429 break;
1430 case 0x002:
1431 type = "Cortex-M3 DWT";
1432 full = "(Data Watchpoint and Trace)";
1433 break;
1434 case 0x003:
1435 type = "Cortex-M3 FBP";
1436 full = "(Flash Patch and Breakpoint)";
1437 break;
1438 case 0x00d:
1439 type = "CoreSight ETM11";
1440 full = "(Embedded Trace)";
1441 break;
1442 // case 0x113: what?
1443 case 0x120: /* from OMAP3 memmap */
1444 type = "TI SDTI";
1445 full = "(System Debug Trace Interface)";
1446 break;
1447 case 0x343: /* from OMAP3 memmap */
1448 type = "TI DAPCTL";
1449 full = "";
1450 break;
1451 case 0x906:
1452 type = "Coresight CTI";
1453 full = "(Cross Trigger)";
1454 break;
1455 case 0x907:
1456 type = "Coresight ETB";
1457 full = "(Trace Buffer)";
1458 break;
1459 case 0x908:
1460 type = "Coresight CSTF";
1461 full = "(Trace Funnel)";
1462 break;
1463 case 0x910:
1464 type = "CoreSight ETM9";
1465 full = "(Embedded Trace)";
1466 break;
1467 case 0x912:
1468 type = "Coresight TPIU";
1469 full = "(Trace Port Interface Unit)";
1470 break;
1471 case 0x921:
1472 type = "Cortex-A8 ETM";
1473 full = "(Embedded Trace)";
1474 break;
1475 case 0x922:
1476 type = "Cortex-A8 CTI";
1477 full = "(Cross Trigger)";
1478 break;
1479 case 0x923:
1480 type = "Cortex-M3 TPIU";
1481 full = "(Trace Port Interface Unit)";
1482 break;
1483 case 0x924:
1484 type = "Cortex-M3 ETM";
1485 full = "(Embedded Trace)";
1486 break;
1487 case 0xc08:
1488 type = "Cortex-A8 Debug";
1489 full = "(Debug Unit)";
1490 break;
1491 default:
1492 type = "-*- unrecognized -*-";
1493 full = "";
1494 break;
1495 }
1496 command_print(cmd_ctx, "\t\tPart is %s %s",
1497 type, full);
1498 }
1499 else
1500 {
1501 if (romentry)
1502 command_print(cmd_ctx, "\t\tComponent not present");
1503 else
1504 command_print(cmd_ctx, "\t\tEnd of ROM table");
1505 }
1506 entry_offset += 4;
1507 } while (romentry > 0);
1508 }
1509 else
1510 {
1511 command_print(cmd_ctx, "\tNo ROM table present");
1512 }
1513 dap_ap_select(dap, apselold);
1514
1515 return ERROR_OK;
1516 }
1517
1518 COMMAND_HANDLER(handle_dap_info_command)
1519 {
1520 struct target *target = get_current_target(CMD_CTX);
1521 struct arm *arm = target_to_arm(target);
1522 struct adiv5_dap *dap = arm->dap;
1523 uint32_t apsel;
1524
1525 switch (CMD_ARGC) {
1526 case 0:
1527 apsel = dap->apsel;
1528 break;
1529 case 1:
1530 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1531 break;
1532 default:
1533 return ERROR_COMMAND_SYNTAX_ERROR;
1534 }
1535
1536 return dap_info_command(CMD_CTX, dap, apsel);
1537 }
1538
1539 COMMAND_HANDLER(dap_baseaddr_command)
1540 {
1541 struct target *target = get_current_target(CMD_CTX);
1542 struct arm *arm = target_to_arm(target);
1543 struct adiv5_dap *dap = arm->dap;
1544
1545 uint32_t apsel, apselsave, baseaddr;
1546 int retval;
1547
1548 apselsave = dap->apsel;
1549 switch (CMD_ARGC) {
1550 case 0:
1551 apsel = dap->apsel;
1552 break;
1553 case 1:
1554 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1555 /* AP address is in bits 31:24 of DP_SELECT */
1556 if (apsel >= 256)
1557 return ERROR_INVALID_ARGUMENTS;
1558 break;
1559 default:
1560 return ERROR_COMMAND_SYNTAX_ERROR;
1561 }
1562
1563 if (apselsave != apsel)
1564 dap_ap_select(dap, apsel);
1565
1566 /* NOTE: assumes we're talking to a MEM-AP, which
1567 * has a base address. There are other kinds of AP,
1568 * though they're not common for now. This should
1569 * use the ID register to verify it's a MEM-AP.
1570 */
1571 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1572 if (retval != ERROR_OK)
1573 return retval;
1574 retval = dap_run(dap);
1575 if (retval != ERROR_OK)
1576 return retval;
1577
1578 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1579
1580 if (apselsave != apsel)
1581 dap_ap_select(dap, apselsave);
1582
1583 return retval;
1584 }
1585
1586 COMMAND_HANDLER(dap_memaccess_command)
1587 {
1588 struct target *target = get_current_target(CMD_CTX);
1589 struct arm *arm = target_to_arm(target);
1590 struct adiv5_dap *dap = arm->dap;
1591
1592 uint32_t memaccess_tck;
1593
1594 switch (CMD_ARGC) {
1595 case 0:
1596 memaccess_tck = dap->memaccess_tck;
1597 break;
1598 case 1:
1599 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1600 break;
1601 default:
1602 return ERROR_COMMAND_SYNTAX_ERROR;
1603 }
1604 dap->memaccess_tck = memaccess_tck;
1605
1606 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1607 dap->memaccess_tck);
1608
1609 return ERROR_OK;
1610 }
1611
1612 COMMAND_HANDLER(dap_apsel_command)
1613 {
1614 struct target *target = get_current_target(CMD_CTX);
1615 struct arm *arm = target_to_arm(target);
1616 struct adiv5_dap *dap = arm->dap;
1617
1618 uint32_t apsel, apid;
1619 int retval;
1620
1621 switch (CMD_ARGC) {
1622 case 0:
1623 apsel = 0;
1624 break;
1625 case 1:
1626 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1627 /* AP address is in bits 31:24 of DP_SELECT */
1628 if (apsel >= 256)
1629 return ERROR_INVALID_ARGUMENTS;
1630 break;
1631 default:
1632 return ERROR_COMMAND_SYNTAX_ERROR;
1633 }
1634
1635 dap_ap_select(dap, apsel);
1636 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1637 if (retval != ERROR_OK)
1638 return retval;
1639 retval = dap_run(dap);
1640 if (retval != ERROR_OK)
1641 return retval;
1642
1643 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1644 apsel, apid);
1645
1646 return retval;
1647 }
1648
1649 COMMAND_HANDLER(dap_apid_command)
1650 {
1651 struct target *target = get_current_target(CMD_CTX);
1652 struct arm *arm = target_to_arm(target);
1653 struct adiv5_dap *dap = arm->dap;
1654
1655 uint32_t apsel, apselsave, apid;
1656 int retval;
1657
1658 apselsave = dap->apsel;
1659 switch (CMD_ARGC) {
1660 case 0:
1661 apsel = dap->apsel;
1662 break;
1663 case 1:
1664 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1665 /* AP address is in bits 31:24 of DP_SELECT */
1666 if (apsel >= 256)
1667 return ERROR_INVALID_ARGUMENTS;
1668 break;
1669 default:
1670 return ERROR_COMMAND_SYNTAX_ERROR;
1671 }
1672
1673 if (apselsave != apsel)
1674 dap_ap_select(dap, apsel);
1675
1676 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1677 if (retval != ERROR_OK)
1678 return retval;
1679 retval = dap_run(dap);
1680 if (retval != ERROR_OK)
1681 return retval;
1682
1683 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1684 if (apselsave != apsel)
1685 dap_ap_select(dap, apselsave);
1686
1687 return retval;
1688 }
1689
1690 static const struct command_registration dap_commands[] = {
1691 {
1692 .name = "info",
1693 .handler = handle_dap_info_command,
1694 .mode = COMMAND_EXEC,
1695 .help = "display ROM table for MEM-AP "
1696 "(default currently selected AP)",
1697 .usage = "[ap_num]",
1698 },
1699 {
1700 .name = "apsel",
1701 .handler = dap_apsel_command,
1702 .mode = COMMAND_EXEC,
1703 .help = "Set the currently selected AP (default 0) "
1704 "and display the result",
1705 .usage = "[ap_num]",
1706 },
1707 {
1708 .name = "apid",
1709 .handler = dap_apid_command,
1710 .mode = COMMAND_EXEC,
1711 .help = "return ID register from AP "
1712 "(default currently selected AP)",
1713 .usage = "[ap_num]",
1714 },
1715 {
1716 .name = "baseaddr",
1717 .handler = dap_baseaddr_command,
1718 .mode = COMMAND_EXEC,
1719 .help = "return debug base address from MEM-AP "
1720 "(default currently selected AP)",
1721 .usage = "[ap_num]",
1722 },
1723 {
1724 .name = "memaccess",
1725 .handler = dap_memaccess_command,
1726 .mode = COMMAND_EXEC,
1727 .help = "set/get number of extra tck for MEM-AP memory "
1728 "bus access [0-255]",
1729 .usage = "[cycles]",
1730 },
1731 COMMAND_REGISTRATION_DONE
1732 };
1733
1734 const struct command_registration dap_command_handlers[] = {
1735 {
1736 .name = "dap",
1737 .mode = COMMAND_EXEC,
1738 .help = "DAP command group",
1739 .chain = dap_commands,
1740 },
1741 COMMAND_REGISTRATION_DONE
1742 };
1743
1744
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