target/arm_adi_v5: allow commands apsel and apcsw during init phase
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
29
30 /**
31 * @file
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
37 *
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 *
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
57 */
58
59 /*
60 * Relevant specifications from ARM include:
61 *
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 *
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 */
68
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
79 #include <helper/jim-nvp.h>
80
81 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
82
83 /*
84 uint32_t tar_block_size(uint32_t address)
85 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 */
87 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 {
89 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
90 }
91
92 /***************************************************************************
93 * *
94 * DP and MEM-AP register access through APACC and DPACC *
95 * *
96 ***************************************************************************/
97
98 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 {
100 csw |= ap->csw_default;
101
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK) {
106 ap->csw_value = 0;
107 return retval;
108 }
109 ap->csw_value = csw;
110 }
111 return ERROR_OK;
112 }
113
114 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
115 {
116 if (!ap->tar_valid || tar != ap->tar_value) {
117 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
118 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
119 if (retval != ERROR_OK) {
120 ap->tar_valid = false;
121 return retval;
122 }
123 ap->tar_value = tar;
124 ap->tar_valid = true;
125 }
126 return ERROR_OK;
127 }
128
129 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
130 {
131 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
132 if (retval != ERROR_OK) {
133 ap->tar_valid = false;
134 return retval;
135 }
136
137 retval = dap_run(ap->dap);
138 if (retval != ERROR_OK) {
139 ap->tar_valid = false;
140 return retval;
141 }
142
143 ap->tar_value = *tar;
144 ap->tar_valid = true;
145 return ERROR_OK;
146 }
147
148 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
149 {
150 switch (ap->csw_value & CSW_ADDRINC_MASK) {
151 case CSW_ADDRINC_SINGLE:
152 switch (ap->csw_value & CSW_SIZE_MASK) {
153 case CSW_8BIT:
154 return 1;
155 case CSW_16BIT:
156 return 2;
157 case CSW_32BIT:
158 return 4;
159 default:
160 return 0;
161 }
162 case CSW_ADDRINC_PACKED:
163 return 4;
164 }
165 return 0;
166 }
167
168 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
169 */
170 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
171 {
172 if (!ap->tar_valid)
173 return;
174
175 uint32_t inc = mem_ap_get_tar_increment(ap);
176 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
177 ap->tar_valid = false;
178 else
179 ap->tar_value += inc;
180 }
181
182 /**
183 * Queue transactions setting up transfer parameters for the
184 * currently selected MEM-AP.
185 *
186 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
187 * initiate data reads or writes using memory or peripheral addresses.
188 * If the CSW is configured for it, the TAR may be automatically
189 * incremented after each transfer.
190 *
191 * @param ap The MEM-AP.
192 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
193 * matches the cached value, the register is not changed.
194 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
195 * matches the cached address, the register is not changed.
196 *
197 * @return ERROR_OK if the transaction was properly queued, else a fault code.
198 */
199 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
200 {
201 int retval;
202 retval = mem_ap_setup_csw(ap, csw);
203 if (retval != ERROR_OK)
204 return retval;
205 retval = mem_ap_setup_tar(ap, tar);
206 if (retval != ERROR_OK)
207 return retval;
208 return ERROR_OK;
209 }
210
211 /**
212 * Asynchronous (queued) read of a word from memory or a system register.
213 *
214 * @param ap The MEM-AP to access.
215 * @param address Address of the 32-bit word to read; it must be
216 * readable by the currently selected MEM-AP.
217 * @param value points to where the word will be stored when the
218 * transaction queue is flushed (assuming no errors).
219 *
220 * @return ERROR_OK for success. Otherwise a fault code.
221 */
222 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
223 uint32_t *value)
224 {
225 int retval;
226
227 /* Use banked addressing (REG_BDx) to avoid some link traffic
228 * (updating TAR) when reading several consecutive addresses.
229 */
230 retval = mem_ap_setup_transfer(ap,
231 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
232 address & 0xFFFFFFF0);
233 if (retval != ERROR_OK)
234 return retval;
235
236 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
237 }
238
239 /**
240 * Synchronous read of a word from memory or a system register.
241 * As a side effect, this flushes any queued transactions.
242 *
243 * @param ap The MEM-AP to access.
244 * @param address Address of the 32-bit word to read; it must be
245 * readable by the currently selected MEM-AP.
246 * @param value points to where the result will be stored.
247 *
248 * @return ERROR_OK for success; *value holds the result.
249 * Otherwise a fault code.
250 */
251 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
252 uint32_t *value)
253 {
254 int retval;
255
256 retval = mem_ap_read_u32(ap, address, value);
257 if (retval != ERROR_OK)
258 return retval;
259
260 return dap_run(ap->dap);
261 }
262
263 /**
264 * Asynchronous (queued) write of a word to memory or a system register.
265 *
266 * @param ap The MEM-AP to access.
267 * @param address Address to be written; it must be writable by
268 * the currently selected MEM-AP.
269 * @param value Word that will be written to the address when transaction
270 * queue is flushed (assuming no errors).
271 *
272 * @return ERROR_OK for success. Otherwise a fault code.
273 */
274 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
275 uint32_t value)
276 {
277 int retval;
278
279 /* Use banked addressing (REG_BDx) to avoid some link traffic
280 * (updating TAR) when writing several consecutive addresses.
281 */
282 retval = mem_ap_setup_transfer(ap,
283 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
284 address & 0xFFFFFFF0);
285 if (retval != ERROR_OK)
286 return retval;
287
288 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
289 value);
290 }
291
292 /**
293 * Synchronous write of a word to memory or a system register.
294 * As a side effect, this flushes any queued transactions.
295 *
296 * @param ap The MEM-AP to access.
297 * @param address Address to be written; it must be writable by
298 * the currently selected MEM-AP.
299 * @param value Word that will be written.
300 *
301 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
302 */
303 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
304 uint32_t value)
305 {
306 int retval = mem_ap_write_u32(ap, address, value);
307
308 if (retval != ERROR_OK)
309 return retval;
310
311 return dap_run(ap->dap);
312 }
313
314 /**
315 * Synchronous write of a block of memory, using a specific access size.
316 *
317 * @param ap The MEM-AP to access.
318 * @param buffer The data buffer to write. No particular alignment is assumed.
319 * @param size Which access size to use, in bytes. 1, 2 or 4.
320 * @param count The number of writes to do (in size units, not bytes).
321 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
322 * @param addrinc Whether the target address should be increased for each write or not. This
323 * should normally be true, except when writing to e.g. a FIFO.
324 * @return ERROR_OK on success, otherwise an error code.
325 */
326 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
327 uint32_t address, bool addrinc)
328 {
329 struct adiv5_dap *dap = ap->dap;
330 size_t nbytes = size * count;
331 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
332 uint32_t csw_size;
333 uint32_t addr_xor;
334 int retval = ERROR_OK;
335
336 /* TI BE-32 Quirks mode:
337 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
338 * size write address bytes written in order
339 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
340 * 2 TAR ^ 2 (val >> 8), (val)
341 * 1 TAR ^ 3 (val)
342 * For example, if you attempt to write a single byte to address 0, the processor
343 * will actually write a byte to address 3.
344 *
345 * To make writes of size < 4 work as expected, we xor a value with the address before
346 * setting the TAP, and we set the TAP after every transfer rather then relying on
347 * address increment. */
348
349 if (size == 4) {
350 csw_size = CSW_32BIT;
351 addr_xor = 0;
352 } else if (size == 2) {
353 csw_size = CSW_16BIT;
354 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
355 } else if (size == 1) {
356 csw_size = CSW_8BIT;
357 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
358 } else {
359 return ERROR_TARGET_UNALIGNED_ACCESS;
360 }
361
362 if (ap->unaligned_access_bad && (address % size != 0))
363 return ERROR_TARGET_UNALIGNED_ACCESS;
364
365 while (nbytes > 0) {
366 uint32_t this_size = size;
367
368 /* Select packed transfer if possible */
369 if (addrinc && ap->packed_transfers && nbytes >= 4
370 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
371 this_size = 4;
372 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
373 } else {
374 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
375 }
376
377 if (retval != ERROR_OK)
378 break;
379
380 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
381 if (retval != ERROR_OK)
382 return retval;
383
384 /* How many source bytes each transfer will consume, and their location in the DRW,
385 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
386 uint32_t outvalue = 0;
387 uint32_t drw_byte_idx = address;
388 if (dap->ti_be_32_quirks) {
389 switch (this_size) {
390 case 4:
391 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
392 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
393 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
394 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
395 break;
396 case 2:
397 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
398 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
399 break;
400 case 1:
401 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
402 break;
403 }
404 } else {
405 switch (this_size) {
406 case 4:
407 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
408 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
409 /* fallthrough */
410 case 2:
411 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
412 /* fallthrough */
413 case 1:
414 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
415 }
416 }
417
418 nbytes -= this_size;
419
420 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
421 if (retval != ERROR_OK)
422 break;
423
424 mem_ap_update_tar_cache(ap);
425 if (addrinc)
426 address += this_size;
427 }
428
429 /* REVISIT: Might want to have a queued version of this function that does not run. */
430 if (retval == ERROR_OK)
431 retval = dap_run(dap);
432
433 if (retval != ERROR_OK) {
434 uint32_t tar;
435 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
436 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
437 else
438 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
439 }
440
441 return retval;
442 }
443
444 /**
445 * Synchronous read of a block of memory, using a specific access size.
446 *
447 * @param ap The MEM-AP to access.
448 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
449 * @param size Which access size to use, in bytes. 1, 2 or 4.
450 * @param count The number of reads to do (in size units, not bytes).
451 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
452 * @param addrinc Whether the target address should be increased after each read or not. This
453 * should normally be true, except when reading from e.g. a FIFO.
454 * @return ERROR_OK on success, otherwise an error code.
455 */
456 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
457 uint32_t adr, bool addrinc)
458 {
459 struct adiv5_dap *dap = ap->dap;
460 size_t nbytes = size * count;
461 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
462 uint32_t csw_size;
463 uint32_t address = adr;
464 int retval = ERROR_OK;
465
466 /* TI BE-32 Quirks mode:
467 * Reads on big-endian TMS570 behave strangely differently than writes.
468 * They read from the physical address requested, but with DRW byte-reversed.
469 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
470 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
471 * so avoid them. */
472
473 if (size == 4)
474 csw_size = CSW_32BIT;
475 else if (size == 2)
476 csw_size = CSW_16BIT;
477 else if (size == 1)
478 csw_size = CSW_8BIT;
479 else
480 return ERROR_TARGET_UNALIGNED_ACCESS;
481
482 if (ap->unaligned_access_bad && (adr % size != 0))
483 return ERROR_TARGET_UNALIGNED_ACCESS;
484
485 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
486 * over-allocation if packed transfers are going to be used, but determining the real need at
487 * this point would be messy. */
488 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
489 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
490 uint32_t *read_ptr = read_buf;
491 if (read_buf == NULL) {
492 LOG_ERROR("Failed to allocate read buffer");
493 return ERROR_FAIL;
494 }
495
496 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
497 * useful bytes it contains, and their location in the word, depends on the type of transfer
498 * and alignment. */
499 while (nbytes > 0) {
500 uint32_t this_size = size;
501
502 /* Select packed transfer if possible */
503 if (addrinc && ap->packed_transfers && nbytes >= 4
504 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
505 this_size = 4;
506 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
507 } else {
508 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
509 }
510 if (retval != ERROR_OK)
511 break;
512
513 retval = mem_ap_setup_tar(ap, address);
514 if (retval != ERROR_OK)
515 break;
516
517 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
518 if (retval != ERROR_OK)
519 break;
520
521 nbytes -= this_size;
522 if (addrinc)
523 address += this_size;
524
525 mem_ap_update_tar_cache(ap);
526 }
527
528 if (retval == ERROR_OK)
529 retval = dap_run(dap);
530
531 /* Restore state */
532 address = adr;
533 nbytes = size * count;
534 read_ptr = read_buf;
535
536 /* If something failed, read TAR to find out how much data was successfully read, so we can
537 * at least give the caller what we have. */
538 if (retval != ERROR_OK) {
539 uint32_t tar;
540 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
541 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
542 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
543 if (nbytes > tar - address)
544 nbytes = tar - address;
545 } else {
546 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
547 nbytes = 0;
548 }
549 }
550
551 /* Replay loop to populate caller's buffer from the correct word and byte lane */
552 while (nbytes > 0) {
553 uint32_t this_size = size;
554
555 if (addrinc && ap->packed_transfers && nbytes >= 4
556 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
557 this_size = 4;
558 }
559
560 if (dap->ti_be_32_quirks) {
561 switch (this_size) {
562 case 4:
563 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
564 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
565 /* fallthrough */
566 case 2:
567 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
568 /* fallthrough */
569 case 1:
570 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
571 }
572 } else {
573 switch (this_size) {
574 case 4:
575 *buffer++ = *read_ptr >> 8 * (address++ & 3);
576 *buffer++ = *read_ptr >> 8 * (address++ & 3);
577 /* fallthrough */
578 case 2:
579 *buffer++ = *read_ptr >> 8 * (address++ & 3);
580 /* fallthrough */
581 case 1:
582 *buffer++ = *read_ptr >> 8 * (address++ & 3);
583 }
584 }
585
586 read_ptr++;
587 nbytes -= this_size;
588 }
589
590 free(read_buf);
591 return retval;
592 }
593
594 int mem_ap_read_buf(struct adiv5_ap *ap,
595 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
596 {
597 return mem_ap_read(ap, buffer, size, count, address, true);
598 }
599
600 int mem_ap_write_buf(struct adiv5_ap *ap,
601 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
602 {
603 return mem_ap_write(ap, buffer, size, count, address, true);
604 }
605
606 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
607 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
608 {
609 return mem_ap_read(ap, buffer, size, count, address, false);
610 }
611
612 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
613 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
614 {
615 return mem_ap_write(ap, buffer, size, count, address, false);
616 }
617
618 /*--------------------------------------------------------------------------*/
619
620
621 #define DAP_POWER_DOMAIN_TIMEOUT (10)
622
623 /*--------------------------------------------------------------------------*/
624
625 /**
626 * Invalidate cached DP select and cached TAR and CSW of all APs
627 */
628 void dap_invalidate_cache(struct adiv5_dap *dap)
629 {
630 dap->select = DP_SELECT_INVALID;
631 dap->last_read = NULL;
632
633 int i;
634 for (i = 0; i <= 255; i++) {
635 /* force csw and tar write on the next mem-ap access */
636 dap->ap[i].tar_valid = false;
637 dap->ap[i].csw_value = 0;
638 }
639 }
640
641 /**
642 * Initialize a DAP. This sets up the power domains, prepares the DP
643 * for further use and activates overrun checking.
644 *
645 * @param dap The DAP being initialized.
646 */
647 int dap_dp_init(struct adiv5_dap *dap)
648 {
649 int retval;
650
651 LOG_DEBUG("%s", adiv5_dap_name(dap));
652
653 dap_invalidate_cache(dap);
654
655 for (size_t i = 0; i < 30; i++) {
656 /* DP initialization */
657
658 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
659 if (retval == ERROR_OK)
660 break;
661 }
662
663 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
664 if (retval != ERROR_OK)
665 return retval;
666
667 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
668 if (retval != ERROR_OK)
669 return retval;
670
671 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
672 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
673 if (retval != ERROR_OK)
674 return retval;
675
676 /* Check that we have debug power domains activated */
677 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
678 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
679 CDBGPWRUPACK, CDBGPWRUPACK,
680 DAP_POWER_DOMAIN_TIMEOUT);
681 if (retval != ERROR_OK)
682 return retval;
683
684 if (!dap->ignore_syspwrupack) {
685 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
686 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
687 CSYSPWRUPACK, CSYSPWRUPACK,
688 DAP_POWER_DOMAIN_TIMEOUT);
689 if (retval != ERROR_OK)
690 return retval;
691 }
692
693 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
694 if (retval != ERROR_OK)
695 return retval;
696
697 /* With debug power on we can activate OVERRUN checking */
698 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
699 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
700 if (retval != ERROR_OK)
701 return retval;
702 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
703 if (retval != ERROR_OK)
704 return retval;
705
706 retval = dap_run(dap);
707 if (retval != ERROR_OK)
708 return retval;
709
710 return retval;
711 }
712
713 /**
714 * Initialize a DAP. This sets up the power domains, prepares the DP
715 * for further use, and arranges to use AP #0 for all AP operations
716 * until dap_ap-select() changes that policy.
717 *
718 * @param ap The MEM-AP being initialized.
719 */
720 int mem_ap_init(struct adiv5_ap *ap)
721 {
722 /* check that we support packed transfers */
723 uint32_t csw, cfg;
724 int retval;
725 struct adiv5_dap *dap = ap->dap;
726
727 ap->tar_valid = false;
728 ap->csw_value = 0; /* force csw and tar write */
729 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
730 if (retval != ERROR_OK)
731 return retval;
732
733 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
734 if (retval != ERROR_OK)
735 return retval;
736
737 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
738 if (retval != ERROR_OK)
739 return retval;
740
741 retval = dap_run(dap);
742 if (retval != ERROR_OK)
743 return retval;
744
745 if (csw & CSW_ADDRINC_PACKED)
746 ap->packed_transfers = true;
747 else
748 ap->packed_transfers = false;
749
750 /* Packed transfers on TI BE-32 processors do not work correctly in
751 * many cases. */
752 if (dap->ti_be_32_quirks)
753 ap->packed_transfers = false;
754
755 LOG_DEBUG("MEM_AP Packed Transfers: %s",
756 ap->packed_transfers ? "enabled" : "disabled");
757
758 /* The ARM ADI spec leaves implementation-defined whether unaligned
759 * memory accesses work, only work partially, or cause a sticky error.
760 * On TI BE-32 processors, reads seem to return garbage in some bytes
761 * and unaligned writes seem to cause a sticky error.
762 * TODO: it would be nice to have a way to detect whether unaligned
763 * operations are supported on other processors. */
764 ap->unaligned_access_bad = dap->ti_be_32_quirks;
765
766 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
767 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
768
769 return ERROR_OK;
770 }
771
772 /* CID interpretation -- see ARM IHI 0029B section 3
773 * and ARM IHI 0031A table 13-3.
774 */
775 static const char *class_description[16] = {
776 "Reserved", "ROM table", "Reserved", "Reserved",
777 "Reserved", "Reserved", "Reserved", "Reserved",
778 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
779 "Reserved", "OptimoDE DESS",
780 "Generic IP component", "PrimeCell or System component"
781 };
782
783 static bool is_dap_cid_ok(uint32_t cid)
784 {
785 return (cid & 0xffff0fff) == 0xb105000d;
786 }
787
788 /*
789 * This function checks the ID for each access port to find the requested Access Port type
790 */
791 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
792 {
793 int ap_num;
794
795 /* Maximum AP number is 255 since the SELECT register is 8 bits */
796 for (ap_num = 0; ap_num <= 255; ap_num++) {
797
798 /* read the IDR register of the Access Port */
799 uint32_t id_val = 0;
800
801 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
802 if (retval != ERROR_OK)
803 return retval;
804
805 retval = dap_run(dap);
806
807 /* IDR bits:
808 * 31-28 : Revision
809 * 27-24 : JEDEC bank (0x4 for ARM)
810 * 23-17 : JEDEC code (0x3B for ARM)
811 * 16-13 : Class (0b1000=Mem-AP)
812 * 12-8 : Reserved
813 * 7-4 : AP Variant (non-zero for JTAG-AP)
814 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
815 */
816
817 /* Reading register for a non-existant AP should not cause an error,
818 * but just to be sure, try to continue searching if an error does happen.
819 */
820 if ((retval == ERROR_OK) && /* Register read success */
821 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
822 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
823
824 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
825 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
826 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
827 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
828 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
829 ap_num, id_val);
830
831 *ap_out = &dap->ap[ap_num];
832 return ERROR_OK;
833 }
834 }
835
836 LOG_DEBUG("No %s found",
837 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
838 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
839 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
840 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
841 return ERROR_FAIL;
842 }
843
844 int dap_get_debugbase(struct adiv5_ap *ap,
845 uint32_t *dbgbase, uint32_t *apid)
846 {
847 struct adiv5_dap *dap = ap->dap;
848 int retval;
849
850 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
851 if (retval != ERROR_OK)
852 return retval;
853 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
854 if (retval != ERROR_OK)
855 return retval;
856 retval = dap_run(dap);
857 if (retval != ERROR_OK)
858 return retval;
859
860 return ERROR_OK;
861 }
862
863 int dap_lookup_cs_component(struct adiv5_ap *ap,
864 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
865 {
866 uint32_t romentry, entry_offset = 0, component_base, devtype;
867 int retval;
868
869 *addr = 0;
870
871 do {
872 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
873 entry_offset, &romentry);
874 if (retval != ERROR_OK)
875 return retval;
876
877 component_base = (dbgbase & 0xFFFFF000)
878 + (romentry & 0xFFFFF000);
879
880 if (romentry & 0x1) {
881 uint32_t c_cid1;
882 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
883 if (retval != ERROR_OK) {
884 LOG_ERROR("Can't read component with base address 0x%" PRIx32
885 ", the corresponding core might be turned off", component_base);
886 return retval;
887 }
888 if (((c_cid1 >> 4) & 0x0f) == 1) {
889 retval = dap_lookup_cs_component(ap, component_base,
890 type, addr, idx);
891 if (retval == ERROR_OK)
892 break;
893 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
894 return retval;
895 }
896
897 retval = mem_ap_read_atomic_u32(ap,
898 (component_base & 0xfffff000) | 0xfcc,
899 &devtype);
900 if (retval != ERROR_OK)
901 return retval;
902 if ((devtype & 0xff) == type) {
903 if (!*idx) {
904 *addr = component_base;
905 break;
906 } else
907 (*idx)--;
908 }
909 }
910 entry_offset += 4;
911 } while (romentry > 0);
912
913 if (!*addr)
914 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
915
916 return ERROR_OK;
917 }
918
919 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
920 {
921 assert((component_base & 0xFFF) == 0);
922 assert(ap != NULL && cid != NULL && pid != NULL);
923
924 uint32_t cid0, cid1, cid2, cid3;
925 uint32_t pid0, pid1, pid2, pid3, pid4;
926 int retval;
927
928 /* IDs are in last 4K section */
929 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
930 if (retval != ERROR_OK)
931 return retval;
932 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
933 if (retval != ERROR_OK)
934 return retval;
935 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
936 if (retval != ERROR_OK)
937 return retval;
938 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
939 if (retval != ERROR_OK)
940 return retval;
941 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
942 if (retval != ERROR_OK)
943 return retval;
944 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
945 if (retval != ERROR_OK)
946 return retval;
947 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
948 if (retval != ERROR_OK)
949 return retval;
950 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
951 if (retval != ERROR_OK)
952 return retval;
953 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
954 if (retval != ERROR_OK)
955 return retval;
956
957 retval = dap_run(ap->dap);
958 if (retval != ERROR_OK)
959 return retval;
960
961 *cid = (cid3 & 0xff) << 24
962 | (cid2 & 0xff) << 16
963 | (cid1 & 0xff) << 8
964 | (cid0 & 0xff);
965 *pid = (uint64_t)(pid4 & 0xff) << 32
966 | (pid3 & 0xff) << 24
967 | (pid2 & 0xff) << 16
968 | (pid1 & 0xff) << 8
969 | (pid0 & 0xff);
970
971 return ERROR_OK;
972 }
973
974 /* The designer identity code is encoded as:
975 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
976 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
977 * a legacy ASCII Identity Code.
978 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
979 * JEP106 is a standard available from jedec.org
980 */
981
982 /* Part number interpretations are from Cortex
983 * core specs, the CoreSight components TRM
984 * (ARM DDI 0314H), CoreSight System Design
985 * Guide (ARM DGI 0012D) and ETM specs; also
986 * from chip observation (e.g. TI SDTI).
987 */
988
989 /* The legacy code only used the part number field to identify CoreSight peripherals.
990 * This meant that the same part number from two different manufacturers looked the same.
991 * It is desirable for all future additions to identify with both part number and JEP106.
992 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
993 */
994
995 #define ANY_ID 0x1000
996
997 #define ARM_ID 0x4BB
998
999 static const struct {
1000 uint16_t designer_id;
1001 uint16_t part_num;
1002 const char *type;
1003 const char *full;
1004 } dap_partnums[] = {
1005 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1006 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1007 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1008 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1009 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1010 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1011 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1012 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1013 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1014 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1015 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1016 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1017 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1018 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1019 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1020 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1021 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1022 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1023 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1024 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1025 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1026 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1027 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1028 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1029 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1030 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1031 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1032 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1033 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1034 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1035 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1036 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1037 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1038 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1039 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1040 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1041 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1042 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1043 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1044 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1045 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1046 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1047 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1048 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1049 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1050 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1051 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1052 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1053 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1054 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1055 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1056 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1057 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1058 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1059 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1060 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1061 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1062 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1063 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1064 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1065 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1066 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1067 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1068 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1069 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1070 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1071 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1072 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1073 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1074 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1075 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1076 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1077 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1078 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1079 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1080 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1081 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1082 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1083 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1084 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1085 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1086 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1087 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1088 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1089 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1090 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1091 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1092 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1093 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1094 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1095 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1096 /* legacy comment: 0x113: what? */
1097 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1098 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1099 };
1100
1101 static int dap_rom_display(struct command_context *cmd_ctx,
1102 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1103 {
1104 int retval;
1105 uint64_t pid;
1106 uint32_t cid;
1107 char tabs[16] = "";
1108
1109 if (depth > 16) {
1110 command_print(cmd_ctx, "\tTables too deep");
1111 return ERROR_FAIL;
1112 }
1113
1114 if (depth)
1115 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1116
1117 uint32_t base_addr = dbgbase & 0xFFFFF000;
1118 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1119
1120 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1121 if (retval != ERROR_OK) {
1122 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1123 return ERROR_OK; /* Don't abort recursion */
1124 }
1125
1126 if (!is_dap_cid_ok(cid)) {
1127 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1128 return ERROR_OK; /* Don't abort recursion */
1129 }
1130
1131 /* component may take multiple 4K pages */
1132 uint32_t size = (pid >> 36) & 0xf;
1133 if (size > 0)
1134 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1135
1136 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1137
1138 uint8_t class = (cid >> 12) & 0xf;
1139 uint16_t part_num = pid & 0xfff;
1140 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1141
1142 if (designer_id & 0x80) {
1143 /* JEP106 code */
1144 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1145 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1146 } else {
1147 /* Legacy ASCII ID, clear invalid bits */
1148 designer_id &= 0x7f;
1149 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1150 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1151 }
1152
1153 /* default values to be overwritten upon finding a match */
1154 const char *type = "Unrecognized";
1155 const char *full = "";
1156
1157 /* search dap_partnums[] array for a match */
1158 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1159
1160 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1161 continue;
1162
1163 if (dap_partnums[entry].part_num != part_num)
1164 continue;
1165
1166 type = dap_partnums[entry].type;
1167 full = dap_partnums[entry].full;
1168 break;
1169 }
1170
1171 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1172 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1173
1174 if (class == 1) { /* ROM Table */
1175 uint32_t memtype;
1176 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1177 if (retval != ERROR_OK)
1178 return retval;
1179
1180 if (memtype & 0x01)
1181 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1182 else
1183 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1184
1185 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1186 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1187 uint32_t romentry;
1188 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1189 if (retval != ERROR_OK)
1190 return retval;
1191 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1192 tabs, entry_offset, romentry);
1193 if (romentry & 0x01) {
1194 /* Recurse */
1195 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1196 if (retval != ERROR_OK)
1197 return retval;
1198 } else if (romentry != 0) {
1199 command_print(cmd_ctx, "\t\tComponent not present");
1200 } else {
1201 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1202 break;
1203 }
1204 }
1205 } else if (class == 9) { /* CoreSight component */
1206 const char *major = "Reserved", *subtype = "Reserved";
1207
1208 uint32_t devtype;
1209 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1210 if (retval != ERROR_OK)
1211 return retval;
1212 unsigned minor = (devtype >> 4) & 0x0f;
1213 switch (devtype & 0x0f) {
1214 case 0:
1215 major = "Miscellaneous";
1216 switch (minor) {
1217 case 0:
1218 subtype = "other";
1219 break;
1220 case 4:
1221 subtype = "Validation component";
1222 break;
1223 }
1224 break;
1225 case 1:
1226 major = "Trace Sink";
1227 switch (minor) {
1228 case 0:
1229 subtype = "other";
1230 break;
1231 case 1:
1232 subtype = "Port";
1233 break;
1234 case 2:
1235 subtype = "Buffer";
1236 break;
1237 case 3:
1238 subtype = "Router";
1239 break;
1240 }
1241 break;
1242 case 2:
1243 major = "Trace Link";
1244 switch (minor) {
1245 case 0:
1246 subtype = "other";
1247 break;
1248 case 1:
1249 subtype = "Funnel, router";
1250 break;
1251 case 2:
1252 subtype = "Filter";
1253 break;
1254 case 3:
1255 subtype = "FIFO, buffer";
1256 break;
1257 }
1258 break;
1259 case 3:
1260 major = "Trace Source";
1261 switch (minor) {
1262 case 0:
1263 subtype = "other";
1264 break;
1265 case 1:
1266 subtype = "Processor";
1267 break;
1268 case 2:
1269 subtype = "DSP";
1270 break;
1271 case 3:
1272 subtype = "Engine/Coprocessor";
1273 break;
1274 case 4:
1275 subtype = "Bus";
1276 break;
1277 case 6:
1278 subtype = "Software";
1279 break;
1280 }
1281 break;
1282 case 4:
1283 major = "Debug Control";
1284 switch (minor) {
1285 case 0:
1286 subtype = "other";
1287 break;
1288 case 1:
1289 subtype = "Trigger Matrix";
1290 break;
1291 case 2:
1292 subtype = "Debug Auth";
1293 break;
1294 case 3:
1295 subtype = "Power Requestor";
1296 break;
1297 }
1298 break;
1299 case 5:
1300 major = "Debug Logic";
1301 switch (minor) {
1302 case 0:
1303 subtype = "other";
1304 break;
1305 case 1:
1306 subtype = "Processor";
1307 break;
1308 case 2:
1309 subtype = "DSP";
1310 break;
1311 case 3:
1312 subtype = "Engine/Coprocessor";
1313 break;
1314 case 4:
1315 subtype = "Bus";
1316 break;
1317 case 5:
1318 subtype = "Memory";
1319 break;
1320 }
1321 break;
1322 case 6:
1323 major = "Perfomance Monitor";
1324 switch (minor) {
1325 case 0:
1326 subtype = "other";
1327 break;
1328 case 1:
1329 subtype = "Processor";
1330 break;
1331 case 2:
1332 subtype = "DSP";
1333 break;
1334 case 3:
1335 subtype = "Engine/Coprocessor";
1336 break;
1337 case 4:
1338 subtype = "Bus";
1339 break;
1340 case 5:
1341 subtype = "Memory";
1342 break;
1343 }
1344 break;
1345 }
1346 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1347 (uint8_t)(devtype & 0xff),
1348 major, subtype);
1349 /* REVISIT also show 0xfc8 DevId */
1350 }
1351
1352 return ERROR_OK;
1353 }
1354
1355 int dap_info_command(struct command_context *cmd_ctx,
1356 struct adiv5_ap *ap)
1357 {
1358 int retval;
1359 uint32_t dbgbase, apid;
1360 uint8_t mem_ap;
1361
1362 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1363 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1364 if (retval != ERROR_OK)
1365 return retval;
1366
1367 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1368 if (apid == 0) {
1369 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1370 return ERROR_FAIL;
1371 }
1372
1373 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1374 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1375 command_print(cmd_ctx, "\tType is JTAG-AP");
1376 break;
1377 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1378 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1379 break;
1380 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1381 command_print(cmd_ctx, "\tType is MEM-AP APB");
1382 break;
1383 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1384 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1385 break;
1386 default:
1387 command_print(cmd_ctx, "\tUnknown AP type");
1388 break;
1389 }
1390
1391 /* NOTE: a MEM-AP may have a single CoreSight component that's
1392 * not a ROM table ... or have no such components at all.
1393 */
1394 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1395 if (mem_ap) {
1396 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1397
1398 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1399 command_print(cmd_ctx, "\tNo ROM table present");
1400 } else {
1401 if (dbgbase & 0x01)
1402 command_print(cmd_ctx, "\tValid ROM table present");
1403 else
1404 command_print(cmd_ctx, "\tROM table in legacy format");
1405
1406 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1407 }
1408 }
1409
1410 return ERROR_OK;
1411 }
1412
1413 enum adiv5_cfg_param {
1414 CFG_DAP,
1415 CFG_AP_NUM
1416 };
1417
1418 static const Jim_Nvp nvp_config_opts[] = {
1419 { .name = "-dap", .value = CFG_DAP },
1420 { .name = "-ap-num", .value = CFG_AP_NUM },
1421 { .name = NULL, .value = -1 }
1422 };
1423
1424 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1425 {
1426 struct adiv5_private_config *pc;
1427 int e;
1428
1429 pc = (struct adiv5_private_config *)target->private_config;
1430 if (pc == NULL) {
1431 pc = calloc(1, sizeof(struct adiv5_private_config));
1432 pc->ap_num = -1;
1433 target->private_config = pc;
1434 }
1435
1436 target->has_dap = true;
1437
1438 if (goi->argc > 0) {
1439 Jim_Nvp *n;
1440
1441 Jim_SetEmptyResult(goi->interp);
1442
1443 /* check first if topmost item is for us */
1444 e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts,
1445 goi->argv[0], &n);
1446 if (e != JIM_OK)
1447 return JIM_CONTINUE;
1448
1449 e = Jim_GetOpt_Obj(goi, NULL);
1450 if (e != JIM_OK)
1451 return e;
1452
1453 switch (n->value) {
1454 case CFG_DAP:
1455 if (goi->isconfigure) {
1456 Jim_Obj *o_t;
1457 struct adiv5_dap *dap;
1458 e = Jim_GetOpt_Obj(goi, &o_t);
1459 if (e != JIM_OK)
1460 return e;
1461 dap = dap_instance_by_jim_obj(goi->interp, o_t);
1462 if (dap == NULL) {
1463 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
1464 return JIM_ERR;
1465 }
1466 if (pc->dap != NULL && pc->dap != dap) {
1467 Jim_SetResultString(goi->interp,
1468 "DAP assignment cannot be changed after target was created!", -1);
1469 return JIM_ERR;
1470 }
1471 if (target->tap_configured) {
1472 Jim_SetResultString(goi->interp,
1473 "-chain-position and -dap configparams are mutually exclusive!", -1);
1474 return JIM_ERR;
1475 }
1476 pc->dap = dap;
1477 target->tap = dap->tap;
1478 target->dap_configured = true;
1479 } else {
1480 if (goi->argc != 0) {
1481 Jim_WrongNumArgs(goi->interp,
1482 goi->argc, goi->argv,
1483 "NO PARAMS");
1484 return JIM_ERR;
1485 }
1486
1487 if (pc->dap == NULL) {
1488 Jim_SetResultString(goi->interp, "DAP not configured", -1);
1489 return JIM_ERR;
1490 }
1491 Jim_SetResultString(goi->interp, adiv5_dap_name(pc->dap), -1);
1492 }
1493 break;
1494
1495 case CFG_AP_NUM:
1496 if (goi->isconfigure) {
1497 jim_wide ap_num;
1498 e = Jim_GetOpt_Wide(goi, &ap_num);
1499 if (e != JIM_OK)
1500 return e;
1501 pc->ap_num = ap_num;
1502 } else {
1503 if (goi->argc != 0) {
1504 Jim_WrongNumArgs(goi->interp,
1505 goi->argc, goi->argv,
1506 "NO PARAMS");
1507 return JIM_ERR;
1508 }
1509
1510 if (pc->ap_num < 0) {
1511 Jim_SetResultString(goi->interp, "AP number not configured", -1);
1512 return JIM_ERR;
1513 }
1514 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, (int)pc->ap_num));
1515 }
1516 break;
1517 }
1518 }
1519
1520 return JIM_OK;
1521 }
1522
1523 int adiv5_verify_config(struct adiv5_private_config *pc)
1524 {
1525 if (pc == NULL)
1526 return ERROR_FAIL;
1527
1528 if (pc->dap == NULL)
1529 return ERROR_FAIL;
1530
1531 return ERROR_OK;
1532 }
1533
1534
1535 COMMAND_HANDLER(handle_dap_info_command)
1536 {
1537 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1538 uint32_t apsel;
1539
1540 switch (CMD_ARGC) {
1541 case 0:
1542 apsel = dap->apsel;
1543 break;
1544 case 1:
1545 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1546 if (apsel >= 256)
1547 return ERROR_COMMAND_SYNTAX_ERROR;
1548 break;
1549 default:
1550 return ERROR_COMMAND_SYNTAX_ERROR;
1551 }
1552
1553 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1554 }
1555
1556 COMMAND_HANDLER(dap_baseaddr_command)
1557 {
1558 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1559 uint32_t apsel, baseaddr;
1560 int retval;
1561
1562 switch (CMD_ARGC) {
1563 case 0:
1564 apsel = dap->apsel;
1565 break;
1566 case 1:
1567 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1568 /* AP address is in bits 31:24 of DP_SELECT */
1569 if (apsel >= 256)
1570 return ERROR_COMMAND_SYNTAX_ERROR;
1571 break;
1572 default:
1573 return ERROR_COMMAND_SYNTAX_ERROR;
1574 }
1575
1576 /* NOTE: assumes we're talking to a MEM-AP, which
1577 * has a base address. There are other kinds of AP,
1578 * though they're not common for now. This should
1579 * use the ID register to verify it's a MEM-AP.
1580 */
1581 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1582 if (retval != ERROR_OK)
1583 return retval;
1584 retval = dap_run(dap);
1585 if (retval != ERROR_OK)
1586 return retval;
1587
1588 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1589
1590 return retval;
1591 }
1592
1593 COMMAND_HANDLER(dap_memaccess_command)
1594 {
1595 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1596 uint32_t memaccess_tck;
1597
1598 switch (CMD_ARGC) {
1599 case 0:
1600 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1601 break;
1602 case 1:
1603 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1604 break;
1605 default:
1606 return ERROR_COMMAND_SYNTAX_ERROR;
1607 }
1608 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1609
1610 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1611 dap->ap[dap->apsel].memaccess_tck);
1612
1613 return ERROR_OK;
1614 }
1615
1616 COMMAND_HANDLER(dap_apsel_command)
1617 {
1618 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1619 uint32_t apsel;
1620
1621 switch (CMD_ARGC) {
1622 case 0:
1623 command_print(CMD_CTX, "%" PRIi32, dap->apsel);
1624 return ERROR_OK;
1625 case 1:
1626 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1627 /* AP address is in bits 31:24 of DP_SELECT */
1628 if (apsel >= 256)
1629 return ERROR_COMMAND_SYNTAX_ERROR;
1630 break;
1631 default:
1632 return ERROR_COMMAND_SYNTAX_ERROR;
1633 }
1634
1635 dap->apsel = apsel;
1636 return ERROR_OK;
1637 }
1638
1639 COMMAND_HANDLER(dap_apcsw_command)
1640 {
1641 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1642 uint32_t apcsw = dap->ap[dap->apsel].csw_default;
1643 uint32_t csw_val, csw_mask;
1644
1645 switch (CMD_ARGC) {
1646 case 0:
1647 command_print(CMD_CTX, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1648 dap->apsel, apcsw);
1649 return ERROR_OK;
1650 case 1:
1651 if (strcmp(CMD_ARGV[0], "default") == 0)
1652 csw_val = CSW_DEFAULT;
1653 else
1654 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1655
1656 if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1657 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
1658 return ERROR_COMMAND_SYNTAX_ERROR;
1659 }
1660 apcsw = csw_val;
1661 break;
1662 case 2:
1663 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1664 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
1665 if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1666 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
1667 return ERROR_COMMAND_SYNTAX_ERROR;
1668 }
1669 apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
1670 break;
1671 default:
1672 return ERROR_COMMAND_SYNTAX_ERROR;
1673 }
1674 dap->ap[dap->apsel].csw_default = apcsw;
1675
1676 return 0;
1677 }
1678
1679
1680
1681 COMMAND_HANDLER(dap_apid_command)
1682 {
1683 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1684 uint32_t apsel, apid;
1685 int retval;
1686
1687 switch (CMD_ARGC) {
1688 case 0:
1689 apsel = dap->apsel;
1690 break;
1691 case 1:
1692 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1693 /* AP address is in bits 31:24 of DP_SELECT */
1694 if (apsel >= 256)
1695 return ERROR_COMMAND_SYNTAX_ERROR;
1696 break;
1697 default:
1698 return ERROR_COMMAND_SYNTAX_ERROR;
1699 }
1700
1701 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1702 if (retval != ERROR_OK)
1703 return retval;
1704 retval = dap_run(dap);
1705 if (retval != ERROR_OK)
1706 return retval;
1707
1708 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1709
1710 return retval;
1711 }
1712
1713 COMMAND_HANDLER(dap_apreg_command)
1714 {
1715 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1716 uint32_t apsel, reg, value;
1717 struct adiv5_ap *ap;
1718 int retval;
1719
1720 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1721 return ERROR_COMMAND_SYNTAX_ERROR;
1722
1723 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1724 /* AP address is in bits 31:24 of DP_SELECT */
1725 if (apsel >= 256)
1726 return ERROR_COMMAND_SYNTAX_ERROR;
1727 ap = dap_ap(dap, apsel);
1728
1729 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1730 if (reg >= 256 || (reg & 3))
1731 return ERROR_COMMAND_SYNTAX_ERROR;
1732
1733 if (CMD_ARGC == 3) {
1734 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1735 switch (reg) {
1736 case MEM_AP_REG_CSW:
1737 ap->csw_default = 0; /* invalid, force write */
1738 retval = mem_ap_setup_csw(ap, value);
1739 break;
1740 case MEM_AP_REG_TAR:
1741 ap->tar_valid = false; /* invalid, force write */
1742 retval = mem_ap_setup_tar(ap, value);
1743 break;
1744 default:
1745 retval = dap_queue_ap_write(ap, reg, value);
1746 break;
1747 }
1748 } else {
1749 retval = dap_queue_ap_read(ap, reg, &value);
1750 }
1751 if (retval == ERROR_OK)
1752 retval = dap_run(dap);
1753
1754 if (retval != ERROR_OK)
1755 return retval;
1756
1757 if (CMD_ARGC == 2)
1758 command_print(CMD_CTX, "0x%08" PRIx32, value);
1759
1760 return retval;
1761 }
1762
1763 COMMAND_HANDLER(dap_dpreg_command)
1764 {
1765 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1766 uint32_t reg, value;
1767 int retval;
1768
1769 if (CMD_ARGC < 1 || CMD_ARGC > 2)
1770 return ERROR_COMMAND_SYNTAX_ERROR;
1771
1772 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
1773 if (reg >= 256 || (reg & 3))
1774 return ERROR_COMMAND_SYNTAX_ERROR;
1775
1776 if (CMD_ARGC == 2) {
1777 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1778 retval = dap_queue_dp_write(dap, reg, value);
1779 } else {
1780 retval = dap_queue_dp_read(dap, reg, &value);
1781 }
1782 if (retval == ERROR_OK)
1783 retval = dap_run(dap);
1784
1785 if (retval != ERROR_OK)
1786 return retval;
1787
1788 if (CMD_ARGC == 1)
1789 command_print(CMD_CTX, "0x%08" PRIx32, value);
1790
1791 return retval;
1792 }
1793
1794 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1795 {
1796 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1797 uint32_t enable = dap->ti_be_32_quirks;
1798
1799 switch (CMD_ARGC) {
1800 case 0:
1801 break;
1802 case 1:
1803 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1804 if (enable > 1)
1805 return ERROR_COMMAND_SYNTAX_ERROR;
1806 break;
1807 default:
1808 return ERROR_COMMAND_SYNTAX_ERROR;
1809 }
1810 dap->ti_be_32_quirks = enable;
1811 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1812 enable ? "enabled" : "disabled");
1813
1814 return 0;
1815 }
1816
1817 const struct command_registration dap_instance_commands[] = {
1818 {
1819 .name = "info",
1820 .handler = handle_dap_info_command,
1821 .mode = COMMAND_EXEC,
1822 .help = "display ROM table for MEM-AP "
1823 "(default currently selected AP)",
1824 .usage = "[ap_num]",
1825 },
1826 {
1827 .name = "apsel",
1828 .handler = dap_apsel_command,
1829 .mode = COMMAND_ANY,
1830 .help = "Set the currently selected AP (default 0) "
1831 "and display the result",
1832 .usage = "[ap_num]",
1833 },
1834 {
1835 .name = "apcsw",
1836 .handler = dap_apcsw_command,
1837 .mode = COMMAND_ANY,
1838 .help = "Set CSW default bits",
1839 .usage = "[value [mask]]",
1840 },
1841
1842 {
1843 .name = "apid",
1844 .handler = dap_apid_command,
1845 .mode = COMMAND_EXEC,
1846 .help = "return ID register from AP "
1847 "(default currently selected AP)",
1848 .usage = "[ap_num]",
1849 },
1850 {
1851 .name = "apreg",
1852 .handler = dap_apreg_command,
1853 .mode = COMMAND_EXEC,
1854 .help = "read/write a register from AP "
1855 "(reg is byte address of a word register, like 0 4 8...)",
1856 .usage = "ap_num reg [value]",
1857 },
1858 {
1859 .name = "dpreg",
1860 .handler = dap_dpreg_command,
1861 .mode = COMMAND_EXEC,
1862 .help = "read/write a register from DP "
1863 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
1864 .usage = "reg [value]",
1865 },
1866 {
1867 .name = "baseaddr",
1868 .handler = dap_baseaddr_command,
1869 .mode = COMMAND_EXEC,
1870 .help = "return debug base address from MEM-AP "
1871 "(default currently selected AP)",
1872 .usage = "[ap_num]",
1873 },
1874 {
1875 .name = "memaccess",
1876 .handler = dap_memaccess_command,
1877 .mode = COMMAND_EXEC,
1878 .help = "set/get number of extra tck for MEM-AP memory "
1879 "bus access [0-255]",
1880 .usage = "[cycles]",
1881 },
1882 {
1883 .name = "ti_be_32_quirks",
1884 .handler = dap_ti_be_32_quirks_command,
1885 .mode = COMMAND_CONFIG,
1886 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1887 .usage = "[enable]",
1888 },
1889 COMMAND_REGISTRATION_DONE
1890 };