target: restructure dap support
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
29
30 /**
31 * @file
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
37 *
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 *
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
57 */
58
59 /*
60 * Relevant specifications from ARM include:
61 *
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 *
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 */
68
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
79 #include <helper/jim-nvp.h>
80
81 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
82
83 /*
84 uint32_t tar_block_size(uint32_t address)
85 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 */
87 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 {
89 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
90 }
91
92 /***************************************************************************
93 * *
94 * DP and MEM-AP register access through APACC and DPACC *
95 * *
96 ***************************************************************************/
97
98 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 {
100 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
101 ap->csw_default;
102
103 if (csw != ap->csw_value) {
104 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
105 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
106 if (retval != ERROR_OK)
107 return retval;
108 ap->csw_value = csw;
109 }
110 return ERROR_OK;
111 }
112
113 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
114 {
115 if (!ap->tar_valid || tar != ap->tar_value) {
116 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
117 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
118 if (retval != ERROR_OK)
119 return retval;
120 ap->tar_value = tar;
121 ap->tar_valid = true;
122 }
123 return ERROR_OK;
124 }
125
126 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
127 {
128 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
129 if (retval != ERROR_OK) {
130 ap->tar_valid = false;
131 return retval;
132 }
133
134 retval = dap_run(ap->dap);
135 if (retval != ERROR_OK) {
136 ap->tar_valid = false;
137 return retval;
138 }
139
140 ap->tar_value = *tar;
141 ap->tar_valid = true;
142 return ERROR_OK;
143 }
144
145 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
146 {
147 switch (ap->csw_value & CSW_ADDRINC_MASK) {
148 case CSW_ADDRINC_SINGLE:
149 switch (ap->csw_value & CSW_SIZE_MASK) {
150 case CSW_8BIT:
151 return 1;
152 case CSW_16BIT:
153 return 2;
154 case CSW_32BIT:
155 return 4;
156 }
157 case CSW_ADDRINC_PACKED:
158 return 4;
159 }
160 return 0;
161 }
162
163 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
164 */
165 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
166 {
167 if (!ap->tar_valid)
168 return;
169
170 uint32_t inc = mem_ap_get_tar_increment(ap);
171 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
172 ap->tar_valid = false;
173 else
174 ap->tar_value += inc;
175 }
176
177 /**
178 * Queue transactions setting up transfer parameters for the
179 * currently selected MEM-AP.
180 *
181 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
182 * initiate data reads or writes using memory or peripheral addresses.
183 * If the CSW is configured for it, the TAR may be automatically
184 * incremented after each transfer.
185 *
186 * @param ap The MEM-AP.
187 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
188 * matches the cached value, the register is not changed.
189 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
190 * matches the cached address, the register is not changed.
191 *
192 * @return ERROR_OK if the transaction was properly queued, else a fault code.
193 */
194 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
195 {
196 int retval;
197 retval = mem_ap_setup_csw(ap, csw);
198 if (retval != ERROR_OK)
199 return retval;
200 retval = mem_ap_setup_tar(ap, tar);
201 if (retval != ERROR_OK)
202 return retval;
203 return ERROR_OK;
204 }
205
206 /**
207 * Asynchronous (queued) read of a word from memory or a system register.
208 *
209 * @param ap The MEM-AP to access.
210 * @param address Address of the 32-bit word to read; it must be
211 * readable by the currently selected MEM-AP.
212 * @param value points to where the word will be stored when the
213 * transaction queue is flushed (assuming no errors).
214 *
215 * @return ERROR_OK for success. Otherwise a fault code.
216 */
217 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
218 uint32_t *value)
219 {
220 int retval;
221
222 /* Use banked addressing (REG_BDx) to avoid some link traffic
223 * (updating TAR) when reading several consecutive addresses.
224 */
225 retval = mem_ap_setup_transfer(ap,
226 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
227 address & 0xFFFFFFF0);
228 if (retval != ERROR_OK)
229 return retval;
230
231 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
232 }
233
234 /**
235 * Synchronous read of a word from memory or a system register.
236 * As a side effect, this flushes any queued transactions.
237 *
238 * @param ap The MEM-AP to access.
239 * @param address Address of the 32-bit word to read; it must be
240 * readable by the currently selected MEM-AP.
241 * @param value points to where the result will be stored.
242 *
243 * @return ERROR_OK for success; *value holds the result.
244 * Otherwise a fault code.
245 */
246 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
247 uint32_t *value)
248 {
249 int retval;
250
251 retval = mem_ap_read_u32(ap, address, value);
252 if (retval != ERROR_OK)
253 return retval;
254
255 return dap_run(ap->dap);
256 }
257
258 /**
259 * Asynchronous (queued) write of a word to memory or a system register.
260 *
261 * @param ap The MEM-AP to access.
262 * @param address Address to be written; it must be writable by
263 * the currently selected MEM-AP.
264 * @param value Word that will be written to the address when transaction
265 * queue is flushed (assuming no errors).
266 *
267 * @return ERROR_OK for success. Otherwise a fault code.
268 */
269 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
270 uint32_t value)
271 {
272 int retval;
273
274 /* Use banked addressing (REG_BDx) to avoid some link traffic
275 * (updating TAR) when writing several consecutive addresses.
276 */
277 retval = mem_ap_setup_transfer(ap,
278 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
279 address & 0xFFFFFFF0);
280 if (retval != ERROR_OK)
281 return retval;
282
283 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
284 value);
285 }
286
287 /**
288 * Synchronous write of a word to memory or a system register.
289 * As a side effect, this flushes any queued transactions.
290 *
291 * @param ap The MEM-AP to access.
292 * @param address Address to be written; it must be writable by
293 * the currently selected MEM-AP.
294 * @param value Word that will be written.
295 *
296 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
297 */
298 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
299 uint32_t value)
300 {
301 int retval = mem_ap_write_u32(ap, address, value);
302
303 if (retval != ERROR_OK)
304 return retval;
305
306 return dap_run(ap->dap);
307 }
308
309 /**
310 * Synchronous write of a block of memory, using a specific access size.
311 *
312 * @param ap The MEM-AP to access.
313 * @param buffer The data buffer to write. No particular alignment is assumed.
314 * @param size Which access size to use, in bytes. 1, 2 or 4.
315 * @param count The number of writes to do (in size units, not bytes).
316 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
317 * @param addrinc Whether the target address should be increased for each write or not. This
318 * should normally be true, except when writing to e.g. a FIFO.
319 * @return ERROR_OK on success, otherwise an error code.
320 */
321 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
322 uint32_t address, bool addrinc)
323 {
324 struct adiv5_dap *dap = ap->dap;
325 size_t nbytes = size * count;
326 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
327 uint32_t csw_size;
328 uint32_t addr_xor;
329 int retval = ERROR_OK;
330
331 /* TI BE-32 Quirks mode:
332 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
333 * size write address bytes written in order
334 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
335 * 2 TAR ^ 2 (val >> 8), (val)
336 * 1 TAR ^ 3 (val)
337 * For example, if you attempt to write a single byte to address 0, the processor
338 * will actually write a byte to address 3.
339 *
340 * To make writes of size < 4 work as expected, we xor a value with the address before
341 * setting the TAP, and we set the TAP after every transfer rather then relying on
342 * address increment. */
343
344 if (size == 4) {
345 csw_size = CSW_32BIT;
346 addr_xor = 0;
347 } else if (size == 2) {
348 csw_size = CSW_16BIT;
349 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
350 } else if (size == 1) {
351 csw_size = CSW_8BIT;
352 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
353 } else {
354 return ERROR_TARGET_UNALIGNED_ACCESS;
355 }
356
357 if (ap->unaligned_access_bad && (address % size != 0))
358 return ERROR_TARGET_UNALIGNED_ACCESS;
359
360 while (nbytes > 0) {
361 uint32_t this_size = size;
362
363 /* Select packed transfer if possible */
364 if (addrinc && ap->packed_transfers && nbytes >= 4
365 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
366 this_size = 4;
367 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
368 } else {
369 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
370 }
371
372 if (retval != ERROR_OK)
373 break;
374
375 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
376 if (retval != ERROR_OK)
377 return retval;
378
379 /* How many source bytes each transfer will consume, and their location in the DRW,
380 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
381 uint32_t outvalue = 0;
382 uint32_t drw_byte_idx = address;
383 if (dap->ti_be_32_quirks) {
384 switch (this_size) {
385 case 4:
386 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
387 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
388 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
389 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
390 break;
391 case 2:
392 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
393 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
394 break;
395 case 1:
396 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
397 break;
398 }
399 } else {
400 switch (this_size) {
401 case 4:
402 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
403 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
404 /* fallthrough */
405 case 2:
406 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
407 /* fallthrough */
408 case 1:
409 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
410 }
411 }
412
413 nbytes -= this_size;
414
415 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
416 if (retval != ERROR_OK)
417 break;
418
419 mem_ap_update_tar_cache(ap);
420 if (addrinc)
421 address += this_size;
422 }
423
424 /* REVISIT: Might want to have a queued version of this function that does not run. */
425 if (retval == ERROR_OK)
426 retval = dap_run(dap);
427
428 if (retval != ERROR_OK) {
429 uint32_t tar;
430 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
431 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
432 else
433 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
434 }
435
436 return retval;
437 }
438
439 /**
440 * Synchronous read of a block of memory, using a specific access size.
441 *
442 * @param ap The MEM-AP to access.
443 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
444 * @param size Which access size to use, in bytes. 1, 2 or 4.
445 * @param count The number of reads to do (in size units, not bytes).
446 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
447 * @param addrinc Whether the target address should be increased after each read or not. This
448 * should normally be true, except when reading from e.g. a FIFO.
449 * @return ERROR_OK on success, otherwise an error code.
450 */
451 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
452 uint32_t adr, bool addrinc)
453 {
454 struct adiv5_dap *dap = ap->dap;
455 size_t nbytes = size * count;
456 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
457 uint32_t csw_size;
458 uint32_t address = adr;
459 int retval = ERROR_OK;
460
461 /* TI BE-32 Quirks mode:
462 * Reads on big-endian TMS570 behave strangely differently than writes.
463 * They read from the physical address requested, but with DRW byte-reversed.
464 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
465 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
466 * so avoid them. */
467
468 if (size == 4)
469 csw_size = CSW_32BIT;
470 else if (size == 2)
471 csw_size = CSW_16BIT;
472 else if (size == 1)
473 csw_size = CSW_8BIT;
474 else
475 return ERROR_TARGET_UNALIGNED_ACCESS;
476
477 if (ap->unaligned_access_bad && (adr % size != 0))
478 return ERROR_TARGET_UNALIGNED_ACCESS;
479
480 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
481 * over-allocation if packed transfers are going to be used, but determining the real need at
482 * this point would be messy. */
483 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
484 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
485 uint32_t *read_ptr = read_buf;
486 if (read_buf == NULL) {
487 LOG_ERROR("Failed to allocate read buffer");
488 return ERROR_FAIL;
489 }
490
491 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
492 * useful bytes it contains, and their location in the word, depends on the type of transfer
493 * and alignment. */
494 while (nbytes > 0) {
495 uint32_t this_size = size;
496
497 /* Select packed transfer if possible */
498 if (addrinc && ap->packed_transfers && nbytes >= 4
499 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
500 this_size = 4;
501 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
502 } else {
503 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
504 }
505 if (retval != ERROR_OK)
506 break;
507
508 retval = mem_ap_setup_tar(ap, address);
509 if (retval != ERROR_OK)
510 break;
511
512 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
513 if (retval != ERROR_OK)
514 break;
515
516 nbytes -= this_size;
517 if (addrinc)
518 address += this_size;
519
520 mem_ap_update_tar_cache(ap);
521 }
522
523 if (retval == ERROR_OK)
524 retval = dap_run(dap);
525
526 /* Restore state */
527 address = adr;
528 nbytes = size * count;
529 read_ptr = read_buf;
530
531 /* If something failed, read TAR to find out how much data was successfully read, so we can
532 * at least give the caller what we have. */
533 if (retval != ERROR_OK) {
534 uint32_t tar;
535 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
536 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
537 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
538 if (nbytes > tar - address)
539 nbytes = tar - address;
540 } else {
541 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
542 nbytes = 0;
543 }
544 }
545
546 /* Replay loop to populate caller's buffer from the correct word and byte lane */
547 while (nbytes > 0) {
548 uint32_t this_size = size;
549
550 if (addrinc && ap->packed_transfers && nbytes >= 4
551 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
552 this_size = 4;
553 }
554
555 if (dap->ti_be_32_quirks) {
556 switch (this_size) {
557 case 4:
558 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
559 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
560 /* fallthrough */
561 case 2:
562 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
563 /* fallthrough */
564 case 1:
565 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
566 }
567 } else {
568 switch (this_size) {
569 case 4:
570 *buffer++ = *read_ptr >> 8 * (address++ & 3);
571 *buffer++ = *read_ptr >> 8 * (address++ & 3);
572 /* fallthrough */
573 case 2:
574 *buffer++ = *read_ptr >> 8 * (address++ & 3);
575 /* fallthrough */
576 case 1:
577 *buffer++ = *read_ptr >> 8 * (address++ & 3);
578 }
579 }
580
581 read_ptr++;
582 nbytes -= this_size;
583 }
584
585 free(read_buf);
586 return retval;
587 }
588
589 int mem_ap_read_buf(struct adiv5_ap *ap,
590 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
591 {
592 return mem_ap_read(ap, buffer, size, count, address, true);
593 }
594
595 int mem_ap_write_buf(struct adiv5_ap *ap,
596 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
597 {
598 return mem_ap_write(ap, buffer, size, count, address, true);
599 }
600
601 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
602 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
603 {
604 return mem_ap_read(ap, buffer, size, count, address, false);
605 }
606
607 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
608 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
609 {
610 return mem_ap_write(ap, buffer, size, count, address, false);
611 }
612
613 /*--------------------------------------------------------------------------*/
614
615
616 #define DAP_POWER_DOMAIN_TIMEOUT (10)
617
618 /*--------------------------------------------------------------------------*/
619
620 /**
621 * Invalidate cached DP select and cached TAR and CSW of all APs
622 */
623 void dap_invalidate_cache(struct adiv5_dap *dap)
624 {
625 dap->select = DP_SELECT_INVALID;
626 dap->last_read = NULL;
627
628 int i;
629 for (i = 0; i <= 255; i++) {
630 /* force csw and tar write on the next mem-ap access */
631 dap->ap[i].tar_valid = false;
632 dap->ap[i].csw_value = 0;
633 }
634 }
635
636 /**
637 * Initialize a DAP. This sets up the power domains, prepares the DP
638 * for further use and activates overrun checking.
639 *
640 * @param dap The DAP being initialized.
641 */
642 int dap_dp_init(struct adiv5_dap *dap)
643 {
644 int retval;
645
646 LOG_DEBUG("%s", adiv5_dap_name(dap));
647
648 dap_invalidate_cache(dap);
649
650 for (size_t i = 0; i < 30; i++) {
651 /* DP initialization */
652
653 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
654 if (retval == ERROR_OK)
655 break;
656 }
657
658 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
659 if (retval != ERROR_OK)
660 return retval;
661
662 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
663 if (retval != ERROR_OK)
664 return retval;
665
666 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
667 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
668 if (retval != ERROR_OK)
669 return retval;
670
671 /* Check that we have debug power domains activated */
672 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
673 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
674 CDBGPWRUPACK, CDBGPWRUPACK,
675 DAP_POWER_DOMAIN_TIMEOUT);
676 if (retval != ERROR_OK)
677 return retval;
678
679 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
680 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
681 CSYSPWRUPACK, CSYSPWRUPACK,
682 DAP_POWER_DOMAIN_TIMEOUT);
683 if (retval != ERROR_OK)
684 return retval;
685
686 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
687 if (retval != ERROR_OK)
688 return retval;
689
690 /* With debug power on we can activate OVERRUN checking */
691 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
692 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
693 if (retval != ERROR_OK)
694 return retval;
695 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
696 if (retval != ERROR_OK)
697 return retval;
698
699 retval = dap_run(dap);
700 if (retval != ERROR_OK)
701 return retval;
702
703 return retval;
704 }
705
706 /**
707 * Initialize a DAP. This sets up the power domains, prepares the DP
708 * for further use, and arranges to use AP #0 for all AP operations
709 * until dap_ap-select() changes that policy.
710 *
711 * @param ap The MEM-AP being initialized.
712 */
713 int mem_ap_init(struct adiv5_ap *ap)
714 {
715 /* check that we support packed transfers */
716 uint32_t csw, cfg;
717 int retval;
718 struct adiv5_dap *dap = ap->dap;
719
720 ap->tar_valid = false;
721 ap->csw_value = 0; /* force csw and tar write */
722 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
723 if (retval != ERROR_OK)
724 return retval;
725
726 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
727 if (retval != ERROR_OK)
728 return retval;
729
730 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
731 if (retval != ERROR_OK)
732 return retval;
733
734 retval = dap_run(dap);
735 if (retval != ERROR_OK)
736 return retval;
737
738 if (csw & CSW_ADDRINC_PACKED)
739 ap->packed_transfers = true;
740 else
741 ap->packed_transfers = false;
742
743 /* Packed transfers on TI BE-32 processors do not work correctly in
744 * many cases. */
745 if (dap->ti_be_32_quirks)
746 ap->packed_transfers = false;
747
748 LOG_DEBUG("MEM_AP Packed Transfers: %s",
749 ap->packed_transfers ? "enabled" : "disabled");
750
751 /* The ARM ADI spec leaves implementation-defined whether unaligned
752 * memory accesses work, only work partially, or cause a sticky error.
753 * On TI BE-32 processors, reads seem to return garbage in some bytes
754 * and unaligned writes seem to cause a sticky error.
755 * TODO: it would be nice to have a way to detect whether unaligned
756 * operations are supported on other processors. */
757 ap->unaligned_access_bad = dap->ti_be_32_quirks;
758
759 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
760 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
761
762 return ERROR_OK;
763 }
764
765 /* CID interpretation -- see ARM IHI 0029B section 3
766 * and ARM IHI 0031A table 13-3.
767 */
768 static const char *class_description[16] = {
769 "Reserved", "ROM table", "Reserved", "Reserved",
770 "Reserved", "Reserved", "Reserved", "Reserved",
771 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
772 "Reserved", "OptimoDE DESS",
773 "Generic IP component", "PrimeCell or System component"
774 };
775
776 static bool is_dap_cid_ok(uint32_t cid)
777 {
778 return (cid & 0xffff0fff) == 0xb105000d;
779 }
780
781 /*
782 * This function checks the ID for each access port to find the requested Access Port type
783 */
784 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
785 {
786 int ap_num;
787
788 /* Maximum AP number is 255 since the SELECT register is 8 bits */
789 for (ap_num = 0; ap_num <= 255; ap_num++) {
790
791 /* read the IDR register of the Access Port */
792 uint32_t id_val = 0;
793
794 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
795 if (retval != ERROR_OK)
796 return retval;
797
798 retval = dap_run(dap);
799
800 /* IDR bits:
801 * 31-28 : Revision
802 * 27-24 : JEDEC bank (0x4 for ARM)
803 * 23-17 : JEDEC code (0x3B for ARM)
804 * 16-13 : Class (0b1000=Mem-AP)
805 * 12-8 : Reserved
806 * 7-4 : AP Variant (non-zero for JTAG-AP)
807 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
808 */
809
810 /* Reading register for a non-existant AP should not cause an error,
811 * but just to be sure, try to continue searching if an error does happen.
812 */
813 if ((retval == ERROR_OK) && /* Register read success */
814 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
815 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
816
817 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
818 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
819 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
820 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
821 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
822 ap_num, id_val);
823
824 *ap_out = &dap->ap[ap_num];
825 return ERROR_OK;
826 }
827 }
828
829 LOG_DEBUG("No %s found",
830 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
831 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
832 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
833 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
834 return ERROR_FAIL;
835 }
836
837 int dap_get_debugbase(struct adiv5_ap *ap,
838 uint32_t *dbgbase, uint32_t *apid)
839 {
840 struct adiv5_dap *dap = ap->dap;
841 int retval;
842
843 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
844 if (retval != ERROR_OK)
845 return retval;
846 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
847 if (retval != ERROR_OK)
848 return retval;
849 retval = dap_run(dap);
850 if (retval != ERROR_OK)
851 return retval;
852
853 return ERROR_OK;
854 }
855
856 int dap_lookup_cs_component(struct adiv5_ap *ap,
857 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
858 {
859 uint32_t romentry, entry_offset = 0, component_base, devtype;
860 int retval;
861
862 *addr = 0;
863
864 do {
865 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
866 entry_offset, &romentry);
867 if (retval != ERROR_OK)
868 return retval;
869
870 component_base = (dbgbase & 0xFFFFF000)
871 + (romentry & 0xFFFFF000);
872
873 if (romentry & 0x1) {
874 uint32_t c_cid1;
875 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
876 if (retval != ERROR_OK) {
877 LOG_ERROR("Can't read component with base address 0x%" PRIx32
878 ", the corresponding core might be turned off", component_base);
879 return retval;
880 }
881 if (((c_cid1 >> 4) & 0x0f) == 1) {
882 retval = dap_lookup_cs_component(ap, component_base,
883 type, addr, idx);
884 if (retval == ERROR_OK)
885 break;
886 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
887 return retval;
888 }
889
890 retval = mem_ap_read_atomic_u32(ap,
891 (component_base & 0xfffff000) | 0xfcc,
892 &devtype);
893 if (retval != ERROR_OK)
894 return retval;
895 if ((devtype & 0xff) == type) {
896 if (!*idx) {
897 *addr = component_base;
898 break;
899 } else
900 (*idx)--;
901 }
902 }
903 entry_offset += 4;
904 } while (romentry > 0);
905
906 if (!*addr)
907 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
908
909 return ERROR_OK;
910 }
911
912 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
913 {
914 assert((component_base & 0xFFF) == 0);
915 assert(ap != NULL && cid != NULL && pid != NULL);
916
917 uint32_t cid0, cid1, cid2, cid3;
918 uint32_t pid0, pid1, pid2, pid3, pid4;
919 int retval;
920
921 /* IDs are in last 4K section */
922 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
923 if (retval != ERROR_OK)
924 return retval;
925 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
926 if (retval != ERROR_OK)
927 return retval;
928 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
929 if (retval != ERROR_OK)
930 return retval;
931 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
932 if (retval != ERROR_OK)
933 return retval;
934 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
935 if (retval != ERROR_OK)
936 return retval;
937 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
938 if (retval != ERROR_OK)
939 return retval;
940 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
941 if (retval != ERROR_OK)
942 return retval;
943 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
944 if (retval != ERROR_OK)
945 return retval;
946 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
947 if (retval != ERROR_OK)
948 return retval;
949
950 retval = dap_run(ap->dap);
951 if (retval != ERROR_OK)
952 return retval;
953
954 *cid = (cid3 & 0xff) << 24
955 | (cid2 & 0xff) << 16
956 | (cid1 & 0xff) << 8
957 | (cid0 & 0xff);
958 *pid = (uint64_t)(pid4 & 0xff) << 32
959 | (pid3 & 0xff) << 24
960 | (pid2 & 0xff) << 16
961 | (pid1 & 0xff) << 8
962 | (pid0 & 0xff);
963
964 return ERROR_OK;
965 }
966
967 /* The designer identity code is encoded as:
968 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
969 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
970 * a legacy ASCII Identity Code.
971 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
972 * JEP106 is a standard available from jedec.org
973 */
974
975 /* Part number interpretations are from Cortex
976 * core specs, the CoreSight components TRM
977 * (ARM DDI 0314H), CoreSight System Design
978 * Guide (ARM DGI 0012D) and ETM specs; also
979 * from chip observation (e.g. TI SDTI).
980 */
981
982 /* The legacy code only used the part number field to identify CoreSight peripherals.
983 * This meant that the same part number from two different manufacturers looked the same.
984 * It is desirable for all future additions to identify with both part number and JEP106.
985 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
986 */
987
988 #define ANY_ID 0x1000
989
990 #define ARM_ID 0x4BB
991
992 static const struct {
993 uint16_t designer_id;
994 uint16_t part_num;
995 const char *type;
996 const char *full;
997 } dap_partnums[] = {
998 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
999 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1000 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1001 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1002 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1003 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1004 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1005 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1006 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1007 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1008 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1009 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1010 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1011 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1012 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1013 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1014 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1015 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1016 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1017 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1018 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1019 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1020 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1021 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1022 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1023 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1024 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1025 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1026 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1027 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1028 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1029 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1030 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1031 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1032 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1033 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1034 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1035 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1036 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1037 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1038 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1039 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1040 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1041 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1042 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1043 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1044 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1045 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1046 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1047 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1048 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1049 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1050 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1051 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1052 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1053 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1054 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1055 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1056 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1057 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1058 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1059 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1060 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1061 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1062 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1063 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1064 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1065 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1066 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1067 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1068 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1069 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1070 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1071 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1072 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1073 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1074 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1075 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1076 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1077 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1078 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1079 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1080 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1081 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1082 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1083 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1084 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1085 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1086 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1087 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1088 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1089 /* legacy comment: 0x113: what? */
1090 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1091 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1092 };
1093
1094 static int dap_rom_display(struct command_context *cmd_ctx,
1095 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1096 {
1097 int retval;
1098 uint64_t pid;
1099 uint32_t cid;
1100 char tabs[16] = "";
1101
1102 if (depth > 16) {
1103 command_print(cmd_ctx, "\tTables too deep");
1104 return ERROR_FAIL;
1105 }
1106
1107 if (depth)
1108 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1109
1110 uint32_t base_addr = dbgbase & 0xFFFFF000;
1111 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1112
1113 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1114 if (retval != ERROR_OK) {
1115 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1116 return ERROR_OK; /* Don't abort recursion */
1117 }
1118
1119 if (!is_dap_cid_ok(cid)) {
1120 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1121 return ERROR_OK; /* Don't abort recursion */
1122 }
1123
1124 /* component may take multiple 4K pages */
1125 uint32_t size = (pid >> 36) & 0xf;
1126 if (size > 0)
1127 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1128
1129 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1130
1131 uint8_t class = (cid >> 12) & 0xf;
1132 uint16_t part_num = pid & 0xfff;
1133 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1134
1135 if (designer_id & 0x80) {
1136 /* JEP106 code */
1137 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1138 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1139 } else {
1140 /* Legacy ASCII ID, clear invalid bits */
1141 designer_id &= 0x7f;
1142 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1143 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1144 }
1145
1146 /* default values to be overwritten upon finding a match */
1147 const char *type = "Unrecognized";
1148 const char *full = "";
1149
1150 /* search dap_partnums[] array for a match */
1151 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1152
1153 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1154 continue;
1155
1156 if (dap_partnums[entry].part_num != part_num)
1157 continue;
1158
1159 type = dap_partnums[entry].type;
1160 full = dap_partnums[entry].full;
1161 break;
1162 }
1163
1164 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1165 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1166
1167 if (class == 1) { /* ROM Table */
1168 uint32_t memtype;
1169 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1170 if (retval != ERROR_OK)
1171 return retval;
1172
1173 if (memtype & 0x01)
1174 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1175 else
1176 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1177
1178 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1179 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1180 uint32_t romentry;
1181 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1182 if (retval != ERROR_OK)
1183 return retval;
1184 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1185 tabs, entry_offset, romentry);
1186 if (romentry & 0x01) {
1187 /* Recurse */
1188 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1189 if (retval != ERROR_OK)
1190 return retval;
1191 } else if (romentry != 0) {
1192 command_print(cmd_ctx, "\t\tComponent not present");
1193 } else {
1194 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1195 break;
1196 }
1197 }
1198 } else if (class == 9) { /* CoreSight component */
1199 const char *major = "Reserved", *subtype = "Reserved";
1200
1201 uint32_t devtype;
1202 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1203 if (retval != ERROR_OK)
1204 return retval;
1205 unsigned minor = (devtype >> 4) & 0x0f;
1206 switch (devtype & 0x0f) {
1207 case 0:
1208 major = "Miscellaneous";
1209 switch (minor) {
1210 case 0:
1211 subtype = "other";
1212 break;
1213 case 4:
1214 subtype = "Validation component";
1215 break;
1216 }
1217 break;
1218 case 1:
1219 major = "Trace Sink";
1220 switch (minor) {
1221 case 0:
1222 subtype = "other";
1223 break;
1224 case 1:
1225 subtype = "Port";
1226 break;
1227 case 2:
1228 subtype = "Buffer";
1229 break;
1230 case 3:
1231 subtype = "Router";
1232 break;
1233 }
1234 break;
1235 case 2:
1236 major = "Trace Link";
1237 switch (minor) {
1238 case 0:
1239 subtype = "other";
1240 break;
1241 case 1:
1242 subtype = "Funnel, router";
1243 break;
1244 case 2:
1245 subtype = "Filter";
1246 break;
1247 case 3:
1248 subtype = "FIFO, buffer";
1249 break;
1250 }
1251 break;
1252 case 3:
1253 major = "Trace Source";
1254 switch (minor) {
1255 case 0:
1256 subtype = "other";
1257 break;
1258 case 1:
1259 subtype = "Processor";
1260 break;
1261 case 2:
1262 subtype = "DSP";
1263 break;
1264 case 3:
1265 subtype = "Engine/Coprocessor";
1266 break;
1267 case 4:
1268 subtype = "Bus";
1269 break;
1270 case 6:
1271 subtype = "Software";
1272 break;
1273 }
1274 break;
1275 case 4:
1276 major = "Debug Control";
1277 switch (minor) {
1278 case 0:
1279 subtype = "other";
1280 break;
1281 case 1:
1282 subtype = "Trigger Matrix";
1283 break;
1284 case 2:
1285 subtype = "Debug Auth";
1286 break;
1287 case 3:
1288 subtype = "Power Requestor";
1289 break;
1290 }
1291 break;
1292 case 5:
1293 major = "Debug Logic";
1294 switch (minor) {
1295 case 0:
1296 subtype = "other";
1297 break;
1298 case 1:
1299 subtype = "Processor";
1300 break;
1301 case 2:
1302 subtype = "DSP";
1303 break;
1304 case 3:
1305 subtype = "Engine/Coprocessor";
1306 break;
1307 case 4:
1308 subtype = "Bus";
1309 break;
1310 case 5:
1311 subtype = "Memory";
1312 break;
1313 }
1314 break;
1315 case 6:
1316 major = "Perfomance Monitor";
1317 switch (minor) {
1318 case 0:
1319 subtype = "other";
1320 break;
1321 case 1:
1322 subtype = "Processor";
1323 break;
1324 case 2:
1325 subtype = "DSP";
1326 break;
1327 case 3:
1328 subtype = "Engine/Coprocessor";
1329 break;
1330 case 4:
1331 subtype = "Bus";
1332 break;
1333 case 5:
1334 subtype = "Memory";
1335 break;
1336 }
1337 break;
1338 }
1339 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1340 (uint8_t)(devtype & 0xff),
1341 major, subtype);
1342 /* REVISIT also show 0xfc8 DevId */
1343 }
1344
1345 return ERROR_OK;
1346 }
1347
1348 int dap_info_command(struct command_context *cmd_ctx,
1349 struct adiv5_ap *ap)
1350 {
1351 int retval;
1352 uint32_t dbgbase, apid;
1353 uint8_t mem_ap;
1354
1355 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1356 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1357 if (retval != ERROR_OK)
1358 return retval;
1359
1360 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1361 if (apid == 0) {
1362 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1363 return ERROR_FAIL;
1364 }
1365
1366 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1367 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1368 command_print(cmd_ctx, "\tType is JTAG-AP");
1369 break;
1370 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1371 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1372 break;
1373 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1374 command_print(cmd_ctx, "\tType is MEM-AP APB");
1375 break;
1376 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1377 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1378 break;
1379 default:
1380 command_print(cmd_ctx, "\tUnknown AP type");
1381 break;
1382 }
1383
1384 /* NOTE: a MEM-AP may have a single CoreSight component that's
1385 * not a ROM table ... or have no such components at all.
1386 */
1387 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1388 if (mem_ap) {
1389 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1390
1391 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1392 command_print(cmd_ctx, "\tNo ROM table present");
1393 } else {
1394 if (dbgbase & 0x01)
1395 command_print(cmd_ctx, "\tValid ROM table present");
1396 else
1397 command_print(cmd_ctx, "\tROM table in legacy format");
1398
1399 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1400 }
1401 }
1402
1403 return ERROR_OK;
1404 }
1405
1406 enum adiv5_cfg_param {
1407 CFG_DAP,
1408 CFG_AP_NUM
1409 };
1410
1411 static const Jim_Nvp nvp_config_opts[] = {
1412 { .name = "-dap", .value = CFG_DAP },
1413 { .name = "-ap-num", .value = CFG_AP_NUM },
1414 { .name = NULL, .value = -1 }
1415 };
1416
1417 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1418 {
1419 struct adiv5_private_config *pc;
1420 int e;
1421
1422 pc = (struct adiv5_private_config *)target->private_config;
1423 if (pc == NULL) {
1424 pc = calloc(1, sizeof(struct adiv5_private_config));
1425 pc->ap_num = -1;
1426 target->private_config = pc;
1427 }
1428
1429 target->has_dap = true;
1430
1431 if (goi->argc > 0) {
1432 Jim_Nvp *n;
1433
1434 Jim_SetEmptyResult(goi->interp);
1435
1436 /* check first if topmost item is for us */
1437 e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts,
1438 goi->argv[0], &n);
1439 if (e != JIM_OK)
1440 return JIM_CONTINUE;
1441
1442 e = Jim_GetOpt_Obj(goi, NULL);
1443 if (e != JIM_OK)
1444 return e;
1445
1446 switch (n->value) {
1447 case CFG_DAP:
1448 if (goi->isconfigure) {
1449 Jim_Obj *o_t;
1450 struct adiv5_dap *dap;
1451 e = Jim_GetOpt_Obj(goi, &o_t);
1452 if (e != JIM_OK)
1453 return e;
1454 dap = dap_instance_by_jim_obj(goi->interp, o_t);
1455 if (dap == NULL) {
1456 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
1457 return JIM_ERR;
1458 }
1459 if (pc->dap != NULL && pc->dap != dap) {
1460 Jim_SetResultString(goi->interp,
1461 "DAP assignment cannot be changed after target was created!", -1);
1462 return JIM_ERR;
1463 }
1464 if (target->tap_configured) {
1465 Jim_SetResultString(goi->interp,
1466 "-chain-position and -dap configparams are mutually exclusive!", -1);
1467 return JIM_ERR;
1468 }
1469 pc->dap = dap;
1470 target->tap = dap->tap;
1471 target->dap_configured = true;
1472 } else {
1473 if (goi->argc != 0) {
1474 Jim_WrongNumArgs(goi->interp,
1475 goi->argc, goi->argv,
1476 "NO PARAMS");
1477 return JIM_ERR;
1478 }
1479
1480 if (pc->dap == NULL) {
1481 Jim_SetResultString(goi->interp, "DAP not configured", -1);
1482 return JIM_ERR;
1483 }
1484 Jim_SetResultString(goi->interp, adiv5_dap_name(pc->dap), -1);
1485 }
1486 break;
1487
1488 case CFG_AP_NUM:
1489 if (goi->isconfigure) {
1490 jim_wide ap_num;
1491 e = Jim_GetOpt_Wide(goi, &ap_num);
1492 if (e != JIM_OK)
1493 return e;
1494 pc->ap_num = ap_num;
1495 } else {
1496 if (goi->argc != 0) {
1497 Jim_WrongNumArgs(goi->interp,
1498 goi->argc, goi->argv,
1499 "NO PARAMS");
1500 return JIM_ERR;
1501 }
1502
1503 if (pc->ap_num < 0) {
1504 Jim_SetResultString(goi->interp, "AP number not configured", -1);
1505 return JIM_ERR;
1506 }
1507 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, (int)pc->ap_num));
1508 }
1509 break;
1510 }
1511 }
1512
1513 return JIM_OK;
1514 }
1515
1516 int adiv5_verify_config(struct adiv5_private_config *pc)
1517 {
1518 if (pc == NULL)
1519 return ERROR_FAIL;
1520
1521 if (pc->dap == NULL)
1522 return ERROR_FAIL;
1523
1524 return ERROR_OK;
1525 }
1526
1527
1528 COMMAND_HANDLER(handle_dap_info_command)
1529 {
1530 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1531 uint32_t apsel;
1532
1533 switch (CMD_ARGC) {
1534 case 0:
1535 apsel = dap->apsel;
1536 break;
1537 case 1:
1538 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1539 if (apsel >= 256)
1540 return ERROR_COMMAND_SYNTAX_ERROR;
1541 break;
1542 default:
1543 return ERROR_COMMAND_SYNTAX_ERROR;
1544 }
1545
1546 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1547 }
1548
1549 COMMAND_HANDLER(dap_baseaddr_command)
1550 {
1551 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1552 uint32_t apsel, baseaddr;
1553 int retval;
1554
1555 switch (CMD_ARGC) {
1556 case 0:
1557 apsel = dap->apsel;
1558 break;
1559 case 1:
1560 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1561 /* AP address is in bits 31:24 of DP_SELECT */
1562 if (apsel >= 256)
1563 return ERROR_COMMAND_SYNTAX_ERROR;
1564 break;
1565 default:
1566 return ERROR_COMMAND_SYNTAX_ERROR;
1567 }
1568
1569 /* NOTE: assumes we're talking to a MEM-AP, which
1570 * has a base address. There are other kinds of AP,
1571 * though they're not common for now. This should
1572 * use the ID register to verify it's a MEM-AP.
1573 */
1574 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1575 if (retval != ERROR_OK)
1576 return retval;
1577 retval = dap_run(dap);
1578 if (retval != ERROR_OK)
1579 return retval;
1580
1581 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1582
1583 return retval;
1584 }
1585
1586 COMMAND_HANDLER(dap_memaccess_command)
1587 {
1588 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1589 uint32_t memaccess_tck;
1590
1591 switch (CMD_ARGC) {
1592 case 0:
1593 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1594 break;
1595 case 1:
1596 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1597 break;
1598 default:
1599 return ERROR_COMMAND_SYNTAX_ERROR;
1600 }
1601 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1602
1603 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1604 dap->ap[dap->apsel].memaccess_tck);
1605
1606 return ERROR_OK;
1607 }
1608
1609 COMMAND_HANDLER(dap_apsel_command)
1610 {
1611 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1612 uint32_t apsel, apid;
1613 int retval;
1614
1615 switch (CMD_ARGC) {
1616 case 0:
1617 apsel = dap->apsel;
1618 break;
1619 case 1:
1620 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1621 /* AP address is in bits 31:24 of DP_SELECT */
1622 if (apsel >= 256)
1623 return ERROR_COMMAND_SYNTAX_ERROR;
1624 break;
1625 default:
1626 return ERROR_COMMAND_SYNTAX_ERROR;
1627 }
1628
1629 dap->apsel = apsel;
1630
1631 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1632 if (retval != ERROR_OK)
1633 return retval;
1634 retval = dap_run(dap);
1635 if (retval != ERROR_OK)
1636 return retval;
1637
1638 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1639 apsel, apid);
1640
1641 return retval;
1642 }
1643
1644 COMMAND_HANDLER(dap_apcsw_command)
1645 {
1646 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1647 uint32_t apcsw = dap->ap[dap->apsel].csw_default;
1648 uint32_t sprot = 0;
1649
1650 switch (CMD_ARGC) {
1651 case 0:
1652 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1653 (dap->apsel), apcsw);
1654 break;
1655 case 1:
1656 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1657 /* AP address is in bits 31:24 of DP_SELECT */
1658 if (sprot > 1)
1659 return ERROR_COMMAND_SYNTAX_ERROR;
1660 if (sprot)
1661 apcsw |= CSW_SPROT;
1662 else
1663 apcsw &= ~CSW_SPROT;
1664 break;
1665 default:
1666 return ERROR_COMMAND_SYNTAX_ERROR;
1667 }
1668 dap->ap[dap->apsel].csw_default = apcsw;
1669
1670 return 0;
1671 }
1672
1673
1674
1675 COMMAND_HANDLER(dap_apid_command)
1676 {
1677 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1678 uint32_t apsel, apid;
1679 int retval;
1680
1681 switch (CMD_ARGC) {
1682 case 0:
1683 apsel = dap->apsel;
1684 break;
1685 case 1:
1686 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1687 /* AP address is in bits 31:24 of DP_SELECT */
1688 if (apsel >= 256)
1689 return ERROR_COMMAND_SYNTAX_ERROR;
1690 break;
1691 default:
1692 return ERROR_COMMAND_SYNTAX_ERROR;
1693 }
1694
1695 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1696 if (retval != ERROR_OK)
1697 return retval;
1698 retval = dap_run(dap);
1699 if (retval != ERROR_OK)
1700 return retval;
1701
1702 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1703
1704 return retval;
1705 }
1706
1707 COMMAND_HANDLER(dap_apreg_command)
1708 {
1709 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1710 uint32_t apsel, reg, value;
1711 int retval;
1712
1713 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1714 return ERROR_COMMAND_SYNTAX_ERROR;
1715
1716 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1717 /* AP address is in bits 31:24 of DP_SELECT */
1718 if (apsel >= 256)
1719 return ERROR_COMMAND_SYNTAX_ERROR;
1720
1721 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1722 if (reg >= 256 || (reg & 3))
1723 return ERROR_COMMAND_SYNTAX_ERROR;
1724
1725 if (CMD_ARGC == 3) {
1726 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1727 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1728 } else {
1729 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1730 }
1731 if (retval == ERROR_OK)
1732 retval = dap_run(dap);
1733
1734 if (retval != ERROR_OK)
1735 return retval;
1736
1737 if (CMD_ARGC == 2)
1738 command_print(CMD_CTX, "0x%08" PRIx32, value);
1739
1740 return retval;
1741 }
1742
1743 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1744 {
1745 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1746 uint32_t enable = dap->ti_be_32_quirks;
1747
1748 switch (CMD_ARGC) {
1749 case 0:
1750 break;
1751 case 1:
1752 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1753 if (enable > 1)
1754 return ERROR_COMMAND_SYNTAX_ERROR;
1755 break;
1756 default:
1757 return ERROR_COMMAND_SYNTAX_ERROR;
1758 }
1759 dap->ti_be_32_quirks = enable;
1760 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1761 enable ? "enabled" : "disabled");
1762
1763 return 0;
1764 }
1765
1766 const struct command_registration dap_instance_commands[] = {
1767 {
1768 .name = "info",
1769 .handler = handle_dap_info_command,
1770 .mode = COMMAND_EXEC,
1771 .help = "display ROM table for MEM-AP "
1772 "(default currently selected AP)",
1773 .usage = "[ap_num]",
1774 },
1775 {
1776 .name = "apsel",
1777 .handler = dap_apsel_command,
1778 .mode = COMMAND_EXEC,
1779 .help = "Set the currently selected AP (default 0) "
1780 "and display the result",
1781 .usage = "[ap_num]",
1782 },
1783 {
1784 .name = "apcsw",
1785 .handler = dap_apcsw_command,
1786 .mode = COMMAND_EXEC,
1787 .help = "Set csw access bit ",
1788 .usage = "[sprot]",
1789 },
1790
1791 {
1792 .name = "apid",
1793 .handler = dap_apid_command,
1794 .mode = COMMAND_EXEC,
1795 .help = "return ID register from AP "
1796 "(default currently selected AP)",
1797 .usage = "[ap_num]",
1798 },
1799 {
1800 .name = "apreg",
1801 .handler = dap_apreg_command,
1802 .mode = COMMAND_EXEC,
1803 .help = "read/write a register from AP "
1804 "(reg is byte address of a word register, like 0 4 8...)",
1805 .usage = "ap_num reg [value]",
1806 },
1807 {
1808 .name = "baseaddr",
1809 .handler = dap_baseaddr_command,
1810 .mode = COMMAND_EXEC,
1811 .help = "return debug base address from MEM-AP "
1812 "(default currently selected AP)",
1813 .usage = "[ap_num]",
1814 },
1815 {
1816 .name = "memaccess",
1817 .handler = dap_memaccess_command,
1818 .mode = COMMAND_EXEC,
1819 .help = "set/get number of extra tck for MEM-AP memory "
1820 "bus access [0-255]",
1821 .usage = "[cycles]",
1822 },
1823 {
1824 .name = "ti_be_32_quirks",
1825 .handler = dap_ti_be_32_quirks_command,
1826 .mode = COMMAND_CONFIG,
1827 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1828 .usage = "[enable]",
1829 },
1830 COMMAND_REGISTRATION_DONE
1831 };