1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
72 #include "jtag/interface.h"
74 #include "arm_adi_v5.h"
75 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
85 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap
*dap
, uint8_t ap
)
105 uint32_t new_ap
= (ap
<< 24) & 0xFF000000;
107 if (new_ap
!= dap
->ap_current
) {
108 dap
->ap_current
= new_ap
;
109 /* Switching AP invalidates cached values.
110 * Values MUST BE UPDATED BEFORE AP ACCESS.
112 dap
->ap_bank_value
= -1;
113 dap
->ap_csw_value
= -1;
114 dap
->ap_tar_value
= -1;
119 * Queue transactions setting up transfer parameters for the
120 * currently selected MEM-AP.
122 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
123 * initiate data reads or writes using memory or peripheral addresses.
124 * If the CSW is configured for it, the TAR may be automatically
125 * incremented after each transfer.
127 * @todo Rename to reflect it being specifically a MEM-AP function.
129 * @param dap The DAP connected to the MEM-AP.
130 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
131 * matches the cached value, the register is not changed.
132 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
133 * matches the cached address, the register is not changed.
135 * @return ERROR_OK if the transaction was properly queued, else a fault code.
137 int dap_setup_accessport(struct adiv5_dap
*dap
, uint32_t csw
, uint32_t tar
)
141 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
142 if (csw
!= dap
->ap_csw_value
) {
143 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
144 retval
= dap_queue_ap_write(dap
, AP_REG_CSW
, csw
);
145 if (retval
!= ERROR_OK
)
147 dap
->ap_csw_value
= csw
;
149 if (tar
!= dap
->ap_tar_value
) {
150 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
151 retval
= dap_queue_ap_write(dap
, AP_REG_TAR
, tar
);
152 if (retval
!= ERROR_OK
)
154 dap
->ap_tar_value
= tar
;
156 /* Disable TAR cache when autoincrementing */
157 if (csw
& CSW_ADDRINC_MASK
)
158 dap
->ap_tar_value
= -1;
163 * Asynchronous (queued) read of a word from memory or a system register.
165 * @param dap The DAP connected to the MEM-AP performing the read.
166 * @param address Address of the 32-bit word to read; it must be
167 * readable by the currently selected MEM-AP.
168 * @param value points to where the word will be stored when the
169 * transaction queue is flushed (assuming no errors).
171 * @return ERROR_OK for success. Otherwise a fault code.
173 int mem_ap_read_u32(struct adiv5_dap
*dap
, uint32_t address
,
178 /* Use banked addressing (REG_BDx) to avoid some link traffic
179 * (updating TAR) when reading several consecutive addresses.
181 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
182 address
& 0xFFFFFFF0);
183 if (retval
!= ERROR_OK
)
186 return dap_queue_ap_read(dap
, AP_REG_BD0
| (address
& 0xC), value
);
190 * Synchronous read of a word from memory or a system register.
191 * As a side effect, this flushes any queued transactions.
193 * @param dap The DAP connected to the MEM-AP performing the read.
194 * @param address Address of the 32-bit word to read; it must be
195 * readable by the currently selected MEM-AP.
196 * @param value points to where the result will be stored.
198 * @return ERROR_OK for success; *value holds the result.
199 * Otherwise a fault code.
201 int mem_ap_read_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
206 retval
= mem_ap_read_u32(dap
, address
, value
);
207 if (retval
!= ERROR_OK
)
214 * Asynchronous (queued) write of a word to memory or a system register.
216 * @param dap The DAP connected to the MEM-AP.
217 * @param address Address to be written; it must be writable by
218 * the currently selected MEM-AP.
219 * @param value Word that will be written to the address when transaction
220 * queue is flushed (assuming no errors).
222 * @return ERROR_OK for success. Otherwise a fault code.
224 int mem_ap_write_u32(struct adiv5_dap
*dap
, uint32_t address
,
229 /* Use banked addressing (REG_BDx) to avoid some link traffic
230 * (updating TAR) when writing several consecutive addresses.
232 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
233 address
& 0xFFFFFFF0);
234 if (retval
!= ERROR_OK
)
237 return dap_queue_ap_write(dap
, AP_REG_BD0
| (address
& 0xC),
242 * Synchronous write of a word to memory or a system register.
243 * As a side effect, this flushes any queued transactions.
245 * @param dap The DAP connected to the MEM-AP.
246 * @param address Address to be written; it must be writable by
247 * the currently selected MEM-AP.
248 * @param value Word that will be written.
250 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
252 int mem_ap_write_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
255 int retval
= mem_ap_write_u32(dap
, address
, value
);
257 if (retval
!= ERROR_OK
)
263 /*****************************************************************************
265 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address, bool addr_incr) *
267 * Write a buffer in target order (little endian) *
269 *****************************************************************************/
270 int mem_ap_write_buf_u32(struct adiv5_dap
*dap
, const uint8_t *buffer
, int count
, uint32_t address
, bool addr_incr
)
272 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
273 uint32_t adr
= address
;
274 const uint8_t *pBuffer
= buffer
;
275 uint32_t incr_flag
= CSW_ADDRINC_OFF
;
280 /* if we have an unaligned access - reorder data */
282 for (writecount
= 0; writecount
< count
; writecount
++) {
285 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
287 for (i
= 0; i
< 4; i
++) {
288 *((uint8_t *)pBuffer
+ (adr
& 0x3)) = outvalue
;
292 pBuffer
+= sizeof(uint32_t);
297 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
298 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
299 if (wcount
< blocksize
)
302 /* handle unaligned data at 4k boundary */
307 incr_flag
= CSW_ADDRINC_SINGLE
;
309 retval
= dap_setup_accessport(dap
, CSW_32BIT
| incr_flag
, address
);
310 if (retval
!= ERROR_OK
)
313 for (writecount
= 0; writecount
< blocksize
; writecount
++) {
315 tmp
= buf_get_u32(buffer
+ 4 * writecount
, 0, 32);
316 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, tmp
);
317 if (retval
!= ERROR_OK
)
321 retval
= dap_run(dap
);
322 if (retval
== ERROR_OK
) {
323 wcount
= wcount
- blocksize
;
325 address
= address
+ 4 * blocksize
;
326 buffer
= buffer
+ 4 * blocksize
;
330 if (errorcount
> 1) {
331 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
339 static int mem_ap_write_buf_packed_u16(struct adiv5_dap
*dap
,
340 const uint8_t *buffer
, int count
, uint32_t address
)
342 int retval
= ERROR_OK
;
343 int wcount
, blocksize
, writecount
, i
;
350 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
351 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
353 if (wcount
< blocksize
)
356 /* handle unaligned data at 4k boundary */
360 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
361 if (retval
!= ERROR_OK
)
363 writecount
= blocksize
;
366 nbytes
= MIN((writecount
<< 1), 4);
369 retval
= mem_ap_write_buf_u16(dap
, buffer
,
371 if (retval
!= ERROR_OK
) {
372 LOG_WARNING("Block write error address "
373 "0x%" PRIx32
", count 0x%x",
378 address
+= nbytes
>> 1;
381 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
383 for (i
= 0; i
< nbytes
; i
++) {
384 *((uint8_t *)buffer
+ (address
& 0x3)) = outvalue
;
389 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
390 retval
= dap_queue_ap_write(dap
,
391 AP_REG_DRW
, outvalue
);
392 if (retval
!= ERROR_OK
)
395 retval
= dap_run(dap
);
396 if (retval
!= ERROR_OK
) {
397 LOG_WARNING("Block write error address "
398 "0x%" PRIx32
", count 0x%x",
404 buffer
+= nbytes
>> 1;
405 writecount
-= nbytes
>> 1;
407 } while (writecount
);
414 int mem_ap_write_buf_u16(struct adiv5_dap
*dap
, const uint8_t *buffer
, int count
, uint32_t address
)
416 int retval
= ERROR_OK
;
419 return mem_ap_write_buf_packed_u16(dap
, buffer
, count
, address
);
422 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
423 if (retval
!= ERROR_OK
)
426 memcpy(&svalue
, buffer
, sizeof(uint16_t));
427 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
428 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
429 if (retval
!= ERROR_OK
)
432 retval
= dap_run(dap
);
433 if (retval
!= ERROR_OK
)
444 static int mem_ap_write_buf_packed_u8(struct adiv5_dap
*dap
,
445 const uint8_t *buffer
, int count
, uint32_t address
)
447 int retval
= ERROR_OK
;
448 int wcount
, blocksize
, writecount
, i
;
455 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
456 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
458 if (wcount
< blocksize
)
461 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
462 if (retval
!= ERROR_OK
)
464 writecount
= blocksize
;
467 nbytes
= MIN(writecount
, 4);
470 retval
= mem_ap_write_buf_u8(dap
, buffer
, nbytes
, address
);
471 if (retval
!= ERROR_OK
) {
472 LOG_WARNING("Block write error address "
473 "0x%" PRIx32
", count 0x%x",
481 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
483 for (i
= 0; i
< nbytes
; i
++) {
484 *((uint8_t *)buffer
+ (address
& 0x3)) = outvalue
;
489 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
490 retval
= dap_queue_ap_write(dap
,
491 AP_REG_DRW
, outvalue
);
492 if (retval
!= ERROR_OK
)
495 retval
= dap_run(dap
);
496 if (retval
!= ERROR_OK
) {
497 LOG_WARNING("Block write error address "
498 "0x%" PRIx32
", count 0x%x",
505 writecount
-= nbytes
;
507 } while (writecount
);
514 int mem_ap_write_buf_u8(struct adiv5_dap
*dap
, const uint8_t *buffer
, int count
, uint32_t address
)
516 int retval
= ERROR_OK
;
519 return mem_ap_write_buf_packed_u8(dap
, buffer
, count
, address
);
522 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
523 if (retval
!= ERROR_OK
)
525 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
526 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
527 if (retval
!= ERROR_OK
)
530 retval
= dap_run(dap
);
531 if (retval
!= ERROR_OK
)
543 * Synchronously read a block of 32-bit words into a buffer
544 * @param dap The DAP connected to the MEM-AP.
545 * @param buffer where the words will be stored (in host byte order).
546 * @param count How many words to read.
547 * @param address Memory address from which to read words; all the
548 * @param addr_incr if true, increment the source address for each u32
549 * words must be readable by the currently selected MEM-AP.
551 int mem_ap_read_buf_u32(struct adiv5_dap
*dap
, uint8_t *buffer
,
552 int count
, uint32_t address
, bool addr_incr
)
554 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
555 uint32_t adr
= address
;
556 uint8_t *pBuffer
= buffer
;
557 uint32_t incr_flag
= CSW_ADDRINC_OFF
;
563 /* Adjust to read blocks within boundaries aligned to the
564 * TAR autoincrement size (at least 2^10). Autoincrement
565 * mode avoids an extra per-word roundtrip to update TAR.
567 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
,
569 if (wcount
< blocksize
)
572 /* handle unaligned data at 4k boundary */
577 incr_flag
= CSW_ADDRINC_SINGLE
;
579 retval
= dap_setup_accessport(dap
, CSW_32BIT
| incr_flag
,
581 if (retval
!= ERROR_OK
)
584 retval
= dap_queue_ap_read_block(dap
, AP_REG_DRW
, blocksize
, buffer
);
586 retval
= dap_run(dap
);
587 if (retval
!= ERROR_OK
) {
589 if (errorcount
<= 1) {
593 LOG_WARNING("Block read error address 0x%" PRIx32
, address
);
596 wcount
= wcount
- blocksize
;
598 address
+= 4 * blocksize
;
599 buffer
+= 4 * blocksize
;
602 /* if we have an unaligned access - reorder data */
604 for (readcount
= 0; readcount
< count
; readcount
++) {
607 memcpy(&data
, pBuffer
, sizeof(uint32_t));
609 for (i
= 0; i
< 4; i
++) {
610 *((uint8_t *)pBuffer
) =
611 (data
>> 8 * (adr
& 0x3));
621 static int mem_ap_read_buf_packed_u16(struct adiv5_dap
*dap
,
622 uint8_t *buffer
, int count
, uint32_t address
)
625 int retval
= ERROR_OK
;
626 int wcount
, blocksize
, readcount
, i
;
633 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
634 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
635 if (wcount
< blocksize
)
638 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
639 if (retval
!= ERROR_OK
)
642 /* handle unaligned data at 4k boundary */
645 readcount
= blocksize
;
648 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
649 if (retval
!= ERROR_OK
)
651 retval
= dap_run(dap
);
652 if (retval
!= ERROR_OK
) {
653 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
657 nbytes
= MIN((readcount
<< 1), 4);
659 for (i
= 0; i
< nbytes
; i
++) {
660 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
665 readcount
-= (nbytes
>> 1);
674 * Synchronously read a block of 16-bit halfwords into a buffer
675 * @param dap The DAP connected to the MEM-AP.
676 * @param buffer where the halfwords will be stored (in host byte order).
677 * @param count How many halfwords to read.
678 * @param address Memory address from which to read words; all the
679 * words must be readable by the currently selected MEM-AP.
681 int mem_ap_read_buf_u16(struct adiv5_dap
*dap
, uint8_t *buffer
,
682 int count
, uint32_t address
)
685 int retval
= ERROR_OK
;
688 return mem_ap_read_buf_packed_u16(dap
, buffer
, count
, address
);
691 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
692 if (retval
!= ERROR_OK
)
694 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
695 if (retval
!= ERROR_OK
)
698 retval
= dap_run(dap
);
699 if (retval
!= ERROR_OK
)
703 for (i
= 0; i
< 2; i
++) {
704 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
709 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
710 memcpy(buffer
, &svalue
, sizeof(uint16_t));
720 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
721 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
723 * The solution is to arrange for a large out/in scan in this loop and
724 * and convert data afterwards.
726 static int mem_ap_read_buf_packed_u8(struct adiv5_dap
*dap
,
727 uint8_t *buffer
, int count
, uint32_t address
)
730 int retval
= ERROR_OK
;
731 int wcount
, blocksize
, readcount
, i
;
738 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
739 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
741 if (wcount
< blocksize
)
744 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
745 if (retval
!= ERROR_OK
)
747 readcount
= blocksize
;
750 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
751 if (retval
!= ERROR_OK
)
753 retval
= dap_run(dap
);
754 if (retval
!= ERROR_OK
) {
755 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
759 nbytes
= MIN(readcount
, 4);
761 for (i
= 0; i
< nbytes
; i
++) {
762 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
776 * Synchronously read a block of bytes into a buffer
777 * @param dap The DAP connected to the MEM-AP.
778 * @param buffer where the bytes will be stored.
779 * @param count How many bytes to read.
780 * @param address Memory address from which to read data; all the
781 * data must be readable by the currently selected MEM-AP.
783 int mem_ap_read_buf_u8(struct adiv5_dap
*dap
, uint8_t *buffer
,
784 int count
, uint32_t address
)
787 int retval
= ERROR_OK
;
790 return mem_ap_read_buf_packed_u8(dap
, buffer
, count
, address
);
793 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
794 if (retval
!= ERROR_OK
)
796 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
797 if (retval
!= ERROR_OK
)
799 retval
= dap_run(dap
);
800 if (retval
!= ERROR_OK
)
803 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
812 /*--------------------------------------------------------------------*/
813 /* Wrapping function with selection of AP */
814 /*--------------------------------------------------------------------*/
815 int mem_ap_sel_read_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
816 uint32_t address
, uint32_t *value
)
818 dap_ap_select(swjdp
, ap
);
819 return mem_ap_read_u32(swjdp
, address
, value
);
822 int mem_ap_sel_write_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
823 uint32_t address
, uint32_t value
)
825 dap_ap_select(swjdp
, ap
);
826 return mem_ap_write_u32(swjdp
, address
, value
);
829 int mem_ap_sel_read_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
830 uint32_t address
, uint32_t *value
)
832 dap_ap_select(swjdp
, ap
);
833 return mem_ap_read_atomic_u32(swjdp
, address
, value
);
836 int mem_ap_sel_write_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
837 uint32_t address
, uint32_t value
)
839 dap_ap_select(swjdp
, ap
);
840 return mem_ap_write_atomic_u32(swjdp
, address
, value
);
843 int mem_ap_sel_read_buf_u8(struct adiv5_dap
*swjdp
, uint8_t ap
,
844 uint8_t *buffer
, int count
, uint32_t address
)
846 dap_ap_select(swjdp
, ap
);
847 return mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
850 int mem_ap_sel_read_buf_u16(struct adiv5_dap
*swjdp
, uint8_t ap
,
851 uint8_t *buffer
, int count
, uint32_t address
)
853 dap_ap_select(swjdp
, ap
);
854 return mem_ap_read_buf_u16(swjdp
, buffer
, count
, address
);
857 int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap
*swjdp
, uint8_t ap
,
858 uint8_t *buffer
, int count
, uint32_t address
)
860 dap_ap_select(swjdp
, ap
);
861 return mem_ap_read_buf_u32(swjdp
, buffer
, count
, address
, false);
864 int mem_ap_sel_read_buf_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
865 uint8_t *buffer
, int count
, uint32_t address
)
867 dap_ap_select(swjdp
, ap
);
868 return mem_ap_read_buf_u32(swjdp
, buffer
, count
, address
, true);
871 int mem_ap_sel_write_buf_u8(struct adiv5_dap
*swjdp
, uint8_t ap
,
872 const uint8_t *buffer
, int count
, uint32_t address
)
874 dap_ap_select(swjdp
, ap
);
875 return mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
878 int mem_ap_sel_write_buf_u16(struct adiv5_dap
*swjdp
, uint8_t ap
,
879 const uint8_t *buffer
, int count
, uint32_t address
)
881 dap_ap_select(swjdp
, ap
);
882 return mem_ap_write_buf_u16(swjdp
, buffer
, count
, address
);
885 int mem_ap_sel_write_buf_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
886 const uint8_t *buffer
, int count
, uint32_t address
)
888 dap_ap_select(swjdp
, ap
);
889 return mem_ap_write_buf_u32(swjdp
, buffer
, count
, address
, true);
892 int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap
*swjdp
, uint8_t ap
,
893 const uint8_t *buffer
, int count
, uint32_t address
)
895 dap_ap_select(swjdp
, ap
);
896 return mem_ap_write_buf_u32(swjdp
, buffer
, count
, address
, false);
899 #define MDM_REG_STAT 0x00
900 #define MDM_REG_CTRL 0x04
901 #define MDM_REG_ID 0xfc
903 #define MDM_STAT_FMEACK (1<<0)
904 #define MDM_STAT_FREADY (1<<1)
905 #define MDM_STAT_SYSSEC (1<<2)
906 #define MDM_STAT_SYSRES (1<<3)
907 #define MDM_STAT_FMEEN (1<<5)
908 #define MDM_STAT_BACKDOOREN (1<<6)
909 #define MDM_STAT_LPEN (1<<7)
910 #define MDM_STAT_VLPEN (1<<8)
911 #define MDM_STAT_LLSMODEXIT (1<<9)
912 #define MDM_STAT_VLLSXMODEXIT (1<<10)
913 #define MDM_STAT_CORE_HALTED (1<<16)
914 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
915 #define MDM_STAT_CORESLEEPING (1<<18)
917 #define MEM_CTRL_FMEIP (1<<0)
918 #define MEM_CTRL_DBG_DIS (1<<1)
919 #define MEM_CTRL_DBG_REQ (1<<2)
920 #define MEM_CTRL_SYS_RES_REQ (1<<3)
921 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
922 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
923 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
924 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
929 int dap_syssec_kinetis_mdmap(struct adiv5_dap
*dap
)
933 enum reset_types jtag_reset_config
= jtag_get_reset_config();
935 dap_ap_select(dap
, 1);
937 /* first check mdm-ap id register */
938 retval
= dap_queue_ap_read(dap
, MDM_REG_ID
, &val
);
939 if (retval
!= ERROR_OK
)
943 if (val
!= 0x001C0000) {
944 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val
);
945 dap_ap_select(dap
, 0);
949 /* read and parse status register
950 * it's important that the device is out of
953 retval
= dap_queue_ap_read(dap
, MDM_REG_STAT
, &val
);
954 if (retval
!= ERROR_OK
)
958 LOG_DEBUG("MDM_REG_STAT %08X", val
);
960 if ((val
& (MDM_STAT_SYSSEC
|MDM_STAT_FREADY
)) != (MDM_STAT_FREADY
)) {
961 LOG_DEBUG("MDMAP: system is secured, masserase needed");
963 if (!(val
& MDM_STAT_FMEEN
))
964 LOG_DEBUG("MDMAP: masserase is disabled");
966 /* we need to assert reset */
967 if (jtag_reset_config
& RESET_HAS_SRST
) {
968 /* default to asserting srst */
969 adapter_assert_reset();
971 LOG_DEBUG("SRST not configured");
972 dap_ap_select(dap
, 0);
977 retval
= dap_queue_ap_write(dap
, MDM_REG_CTRL
, MEM_CTRL_FMEIP
);
978 if (retval
!= ERROR_OK
)
981 /* read status register and wait for ready */
982 retval
= dap_queue_ap_read(dap
, MDM_REG_STAT
, &val
);
983 if (retval
!= ERROR_OK
)
986 LOG_DEBUG("MDM_REG_STAT %08X", val
);
993 retval
= dap_queue_ap_write(dap
, MDM_REG_CTRL
, 0);
994 if (retval
!= ERROR_OK
)
997 /* read status register */
998 retval
= dap_queue_ap_read(dap
, MDM_REG_STAT
, &val
);
999 if (retval
!= ERROR_OK
)
1002 LOG_DEBUG("MDM_REG_STAT %08X", val
);
1003 /* read control register and wait for ready */
1004 retval
= dap_queue_ap_read(dap
, MDM_REG_CTRL
, &val
);
1005 if (retval
!= ERROR_OK
)
1008 LOG_DEBUG("MDM_REG_CTRL %08X", val
);
1016 dap_ap_select(dap
, 0);
1022 struct dap_syssec_filter
{
1026 int (*dap_init
)(struct adiv5_dap
*dap
);
1030 static struct dap_syssec_filter dap_syssec_filter_data
[] = {
1031 { 0x4BA00477, dap_syssec_kinetis_mdmap
}
1037 int dap_syssec(struct adiv5_dap
*dap
)
1040 struct jtag_tap
*tap
;
1042 for (i
= 0; i
< sizeof(dap_syssec_filter_data
); i
++) {
1043 tap
= dap
->jtag_info
->tap
;
1045 while (tap
!= NULL
) {
1046 if (tap
->hasidcode
&& (dap_syssec_filter_data
[i
].idcode
== tap
->idcode
)) {
1047 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap
->idcode
);
1048 dap_syssec_filter_data
[i
].dap_init(dap
);
1050 tap
= tap
->next_tap
;
1057 /*--------------------------------------------------------------------------*/
1060 /* FIXME don't import ... just initialize as
1061 * part of DAP transport setup
1063 extern const struct dap_ops jtag_dp_ops
;
1065 /*--------------------------------------------------------------------------*/
1068 * Initialize a DAP. This sets up the power domains, prepares the DP
1069 * for further use, and arranges to use AP #0 for all AP operations
1070 * until dap_ap-select() changes that policy.
1072 * @param dap The DAP being initialized.
1074 * @todo Rename this. We also need an initialization scheme which account
1075 * for SWD transports not just JTAG; that will need to address differences
1076 * in layering. (JTAG is useful without any debug target; but not SWD.)
1077 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1079 int ahbap_debugport_init(struct adiv5_dap
*dap
)
1087 /* JTAG-DP or SWJ-DP, in JTAG mode
1088 * ... for SWD mode this is patched as part
1089 * of link switchover
1092 dap
->ops
= &jtag_dp_ops
;
1094 /* Default MEM-AP setup.
1096 * REVISIT AP #0 may be an inappropriate default for this.
1097 * Should we probe, or take a hint from the caller?
1098 * Presumably we can ignore the possibility of multiple APs.
1100 dap
->ap_current
= !0;
1101 dap_ap_select(dap
, 0);
1103 /* DP initialization */
1105 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1106 if (retval
!= ERROR_OK
)
1109 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, SSTICKYERR
);
1110 if (retval
!= ERROR_OK
)
1113 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1114 if (retval
!= ERROR_OK
)
1117 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
1118 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
1119 if (retval
!= ERROR_OK
)
1122 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
1123 if (retval
!= ERROR_OK
)
1125 retval
= dap_run(dap
);
1126 if (retval
!= ERROR_OK
)
1129 /* Check that we have debug power domains activated */
1130 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10)) {
1131 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1132 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
1133 if (retval
!= ERROR_OK
)
1135 retval
= dap_run(dap
);
1136 if (retval
!= ERROR_OK
)
1141 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10)) {
1142 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1143 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
1144 if (retval
!= ERROR_OK
)
1146 retval
= dap_run(dap
);
1147 if (retval
!= ERROR_OK
)
1152 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1153 if (retval
!= ERROR_OK
)
1155 /* With debug power on we can activate OVERRUN checking */
1156 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
1157 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
1158 if (retval
!= ERROR_OK
)
1160 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1161 if (retval
!= ERROR_OK
)
1169 /* CID interpretation -- see ARM IHI 0029B section 3
1170 * and ARM IHI 0031A table 13-3.
1172 static const char *class_description
[16] = {
1173 "Reserved", "ROM table", "Reserved", "Reserved",
1174 "Reserved", "Reserved", "Reserved", "Reserved",
1175 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1176 "Reserved", "OptimoDE DESS",
1177 "Generic IP component", "PrimeCell or System component"
1180 static bool is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1182 return cid3
== 0xb1 && cid2
== 0x05
1183 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1187 * This function checks the ID for each access port to find the requested Access Port type
1189 int dap_find_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, uint8_t *ap_num_out
)
1193 /* Maximum AP number is 255 since the SELECT register is 8 bits */
1194 for (ap
= 0; ap
<= 255; ap
++) {
1196 /* read the IDR register of the Access Port */
1197 uint32_t id_val
= 0;
1198 dap_ap_select(dap
, ap
);
1200 int retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &id_val
);
1201 if (retval
!= ERROR_OK
)
1204 retval
= dap_run(dap
);
1208 * 27-24 : JEDEC bank (0x4 for ARM)
1209 * 23-17 : JEDEC code (0x3B for ARM)
1212 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
1215 /* Reading register for a non-existant AP should not cause an error,
1216 * but just to be sure, try to continue searching if an error does happen.
1218 if ((retval
== ERROR_OK
) && /* Register read success */
1219 ((id_val
& 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
1220 ((id_val
& 0xFF) == type_to_find
)) { /* type matches*/
1222 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08X)",
1223 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
1224 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
1225 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown",
1233 LOG_DEBUG("No %s found",
1234 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
1235 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
1236 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown");
1240 int dap_get_debugbase(struct adiv5_dap
*dap
, int ap
,
1241 uint32_t *out_dbgbase
, uint32_t *out_apid
)
1245 uint32_t dbgbase
, apid
;
1247 /* AP address is in bits 31:24 of DP_SELECT */
1249 return ERROR_COMMAND_SYNTAX_ERROR
;
1251 ap_old
= dap
->ap_current
;
1252 dap_ap_select(dap
, ap
);
1254 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &dbgbase
);
1255 if (retval
!= ERROR_OK
)
1257 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1258 if (retval
!= ERROR_OK
)
1260 retval
= dap_run(dap
);
1261 if (retval
!= ERROR_OK
)
1264 /* Excavate the device ID code */
1265 struct jtag_tap
*tap
= dap
->jtag_info
->tap
;
1266 while (tap
!= NULL
) {
1269 tap
= tap
->next_tap
;
1271 if (tap
== NULL
|| !tap
->hasidcode
)
1274 dap_ap_select(dap
, ap_old
);
1276 /* The asignment happens only here to prevent modification of these
1277 * values before they are certain. */
1278 *out_dbgbase
= dbgbase
;
1284 int dap_lookup_cs_component(struct adiv5_dap
*dap
, int ap
,
1285 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
)
1288 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
1289 int retval
= ERROR_FAIL
;
1292 return ERROR_COMMAND_SYNTAX_ERROR
;
1294 ap_old
= dap
->ap_current
;
1295 dap_ap_select(dap
, ap
);
1298 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) |
1299 entry_offset
, &romentry
);
1300 if (retval
!= ERROR_OK
)
1303 component_base
= (dbgbase
& 0xFFFFF000)
1304 + (romentry
& 0xFFFFF000);
1306 if (romentry
& 0x1) {
1307 retval
= mem_ap_read_atomic_u32(dap
,
1308 (component_base
& 0xfffff000) | 0xfcc,
1310 if (retval
!= ERROR_OK
)
1312 if ((devtype
& 0xff) == type
) {
1313 *addr
= component_base
;
1319 } while (romentry
> 0);
1321 dap_ap_select(dap
, ap_old
);
1326 static int dap_info_command(struct command_context
*cmd_ctx
,
1327 struct adiv5_dap
*dap
, int ap
)
1330 uint32_t dbgbase
= 0, apid
= 0; /* Silence gcc by initializing */
1331 int romtable_present
= 0;
1335 retval
= dap_get_debugbase(dap
, ap
, &dbgbase
, &apid
);
1336 if (retval
!= ERROR_OK
)
1339 ap_old
= dap
->ap_current
;
1340 dap_ap_select(dap
, ap
);
1342 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1343 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1344 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1346 switch (apid
&0x0F) {
1348 command_print(cmd_ctx
, "\tType is JTAG-AP");
1351 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1354 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1357 command_print(cmd_ctx
, "\tUnknown AP type");
1361 /* NOTE: a MEM-AP may have a single CoreSight component that's
1362 * not a ROM table ... or have no such components at all.
1365 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
, dbgbase
);
1367 command_print(cmd_ctx
, "No AP found at this ap 0x%x", ap
);
1369 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1370 if (romtable_present
) {
1371 uint32_t cid0
, cid1
, cid2
, cid3
, memtype
, romentry
;
1372 uint16_t entry_offset
;
1374 /* bit 16 of apid indicates a memory access port */
1376 command_print(cmd_ctx
, "\tValid ROM table present");
1378 command_print(cmd_ctx
, "\tROM table in legacy format");
1380 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1381 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1382 if (retval
!= ERROR_OK
)
1384 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1385 if (retval
!= ERROR_OK
)
1387 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1388 if (retval
!= ERROR_OK
)
1390 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1391 if (retval
!= ERROR_OK
)
1393 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1394 if (retval
!= ERROR_OK
)
1396 retval
= dap_run(dap
);
1397 if (retval
!= ERROR_OK
)
1400 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1401 command_print(cmd_ctx
, "\tCID3 0x%2.2x"
1405 (unsigned) cid3
, (unsigned)cid2
,
1406 (unsigned) cid1
, (unsigned) cid0
);
1408 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1410 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1411 "Dedicated debug bus.");
1413 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1416 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1417 if (retval
!= ERROR_OK
)
1419 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"", entry_offset
, romentry
);
1420 if (romentry
& 0x01) {
1421 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1422 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1423 uint32_t component_base
;
1427 component_base
= (dbgbase
& 0xFFFFF000) + (romentry
& 0xFFFFF000);
1429 /* IDs are in last 4K section */
1430 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE0, &c_pid0
);
1431 if (retval
!= ERROR_OK
)
1434 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE4, &c_pid1
);
1435 if (retval
!= ERROR_OK
)
1438 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE8, &c_pid2
);
1439 if (retval
!= ERROR_OK
)
1442 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFEC, &c_pid3
);
1443 if (retval
!= ERROR_OK
)
1446 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFD0, &c_pid4
);
1447 if (retval
!= ERROR_OK
)
1451 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF0, &c_cid0
);
1452 if (retval
!= ERROR_OK
)
1455 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF4, &c_cid1
);
1456 if (retval
!= ERROR_OK
)
1459 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF8, &c_cid2
);
1460 if (retval
!= ERROR_OK
)
1463 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFFC, &c_cid3
);
1464 if (retval
!= ERROR_OK
)
1468 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
","
1469 "start address 0x%" PRIx32
, component_base
,
1470 /* component may take multiple 4K pages */
1471 component_base
- 0x1000*(c_pid4
>> 4));
1472 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1473 (int) (c_cid1
>> 4) & 0xf,
1474 /* See ARM IHI 0029B Table 3-3 */
1475 class_description
[(c_cid1
>> 4) & 0xf]);
1477 /* CoreSight component? */
1478 if (((c_cid1
>> 4) & 0x0f) == 9) {
1481 char *major
= "Reserved", *subtype
= "Reserved";
1483 retval
= mem_ap_read_atomic_u32(dap
,
1484 (component_base
& 0xfffff000) | 0xfcc,
1486 if (retval
!= ERROR_OK
)
1488 minor
= (devtype
>> 4) & 0x0f;
1489 switch (devtype
& 0x0f) {
1491 major
= "Miscellaneous";
1497 subtype
= "Validation component";
1502 major
= "Trace Sink";
1516 major
= "Trace Link";
1522 subtype
= "Funnel, router";
1528 subtype
= "FIFO, buffer";
1533 major
= "Trace Source";
1539 subtype
= "Processor";
1545 subtype
= "Engine/Coprocessor";
1553 major
= "Debug Control";
1559 subtype
= "Trigger Matrix";
1562 subtype
= "Debug Auth";
1567 major
= "Debug Logic";
1573 subtype
= "Processor";
1579 subtype
= "Engine/Coprocessor";
1584 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1585 (unsigned) (devtype
& 0xff),
1587 /* REVISIT also show 0xfc8 DevId */
1590 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1591 command_print(cmd_ctx
,
1600 command_print(cmd_ctx
,
1601 "\t\tPeripheral ID[4..0] = hex "
1602 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1603 (int) c_pid4
, (int) c_pid3
, (int) c_pid2
,
1604 (int) c_pid1
, (int) c_pid0
);
1606 /* Part number interpretations are from Cortex
1607 * core specs, the CoreSight components TRM
1608 * (ARM DDI 0314H), CoreSight System Design
1609 * Guide (ARM DGI 0012D) and ETM specs; also
1610 * from chip observation (e.g. TI SDTI).
1612 part_num
= (c_pid0
& 0xff);
1613 part_num
|= (c_pid1
& 0x0f) << 8;
1616 type
= "Cortex-M3 NVIC";
1617 full
= "(Interrupt Controller)";
1620 type
= "Cortex-M3 ITM";
1621 full
= "(Instrumentation Trace Module)";
1624 type
= "Cortex-M3 DWT";
1625 full
= "(Data Watchpoint and Trace)";
1628 type
= "Cortex-M3 FBP";
1629 full
= "(Flash Patch and Breakpoint)";
1632 type
= "Cortex-M4 SCS";
1633 full
= "(System Control Space)";
1636 type
= "CoreSight ETM11";
1637 full
= "(Embedded Trace)";
1639 /* case 0x113: what? */
1640 case 0x120: /* from OMAP3 memmap */
1642 full
= "(System Debug Trace Interface)";
1644 case 0x343: /* from OMAP3 memmap */
1649 type
= "Coresight CTI";
1650 full
= "(Cross Trigger)";
1653 type
= "Coresight ETB";
1654 full
= "(Trace Buffer)";
1657 type
= "Coresight CSTF";
1658 full
= "(Trace Funnel)";
1661 type
= "CoreSight ETM9";
1662 full
= "(Embedded Trace)";
1665 type
= "Coresight TPIU";
1666 full
= "(Trace Port Interface Unit)";
1669 type
= "Cortex-A8 ETM";
1670 full
= "(Embedded Trace)";
1673 type
= "Cortex-A8 CTI";
1674 full
= "(Cross Trigger)";
1677 type
= "Cortex-M3 TPIU";
1678 full
= "(Trace Port Interface Unit)";
1681 type
= "Cortex-M3 ETM";
1682 full
= "(Embedded Trace)";
1685 type
= "Cortex-M4 ETM";
1686 full
= "(Embedded Trace)";
1689 type
= "Cortex-R4 ETM";
1690 full
= "(Embedded Trace)";
1693 type
= "Cortex-M4 TPUI";
1694 full
= "(Trace Port Interface Unit)";
1697 type
= "Cortex-A8 Debug";
1698 full
= "(Debug Unit)";
1701 type
= "-*- unrecognized -*-";
1705 command_print(cmd_ctx
, "\t\tPart is %s %s",
1709 command_print(cmd_ctx
, "\t\tComponent not present");
1711 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1714 } while (romentry
> 0);
1716 command_print(cmd_ctx
, "\tNo ROM table present");
1717 dap_ap_select(dap
, ap_old
);
1722 COMMAND_HANDLER(handle_dap_info_command
)
1724 struct target
*target
= get_current_target(CMD_CTX
);
1725 struct arm
*arm
= target_to_arm(target
);
1726 struct adiv5_dap
*dap
= arm
->dap
;
1734 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1737 return ERROR_COMMAND_SYNTAX_ERROR
;
1740 return dap_info_command(CMD_CTX
, dap
, apsel
);
1743 COMMAND_HANDLER(dap_baseaddr_command
)
1745 struct target
*target
= get_current_target(CMD_CTX
);
1746 struct arm
*arm
= target_to_arm(target
);
1747 struct adiv5_dap
*dap
= arm
->dap
;
1749 uint32_t apsel
, baseaddr
;
1757 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1758 /* AP address is in bits 31:24 of DP_SELECT */
1760 return ERROR_COMMAND_SYNTAX_ERROR
;
1763 return ERROR_COMMAND_SYNTAX_ERROR
;
1766 dap_ap_select(dap
, apsel
);
1768 /* NOTE: assumes we're talking to a MEM-AP, which
1769 * has a base address. There are other kinds of AP,
1770 * though they're not common for now. This should
1771 * use the ID register to verify it's a MEM-AP.
1773 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &baseaddr
);
1774 if (retval
!= ERROR_OK
)
1776 retval
= dap_run(dap
);
1777 if (retval
!= ERROR_OK
)
1780 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1785 COMMAND_HANDLER(dap_memaccess_command
)
1787 struct target
*target
= get_current_target(CMD_CTX
);
1788 struct arm
*arm
= target_to_arm(target
);
1789 struct adiv5_dap
*dap
= arm
->dap
;
1791 uint32_t memaccess_tck
;
1795 memaccess_tck
= dap
->memaccess_tck
;
1798 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1801 return ERROR_COMMAND_SYNTAX_ERROR
;
1803 dap
->memaccess_tck
= memaccess_tck
;
1805 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1806 dap
->memaccess_tck
);
1811 COMMAND_HANDLER(dap_apsel_command
)
1813 struct target
*target
= get_current_target(CMD_CTX
);
1814 struct arm
*arm
= target_to_arm(target
);
1815 struct adiv5_dap
*dap
= arm
->dap
;
1817 uint32_t apsel
, apid
;
1825 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1826 /* AP address is in bits 31:24 of DP_SELECT */
1828 return ERROR_COMMAND_SYNTAX_ERROR
;
1831 return ERROR_COMMAND_SYNTAX_ERROR
;
1835 dap_ap_select(dap
, apsel
);
1837 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1838 if (retval
!= ERROR_OK
)
1840 retval
= dap_run(dap
);
1841 if (retval
!= ERROR_OK
)
1844 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1850 COMMAND_HANDLER(dap_apid_command
)
1852 struct target
*target
= get_current_target(CMD_CTX
);
1853 struct arm
*arm
= target_to_arm(target
);
1854 struct adiv5_dap
*dap
= arm
->dap
;
1856 uint32_t apsel
, apid
;
1864 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1865 /* AP address is in bits 31:24 of DP_SELECT */
1867 return ERROR_COMMAND_SYNTAX_ERROR
;
1870 return ERROR_COMMAND_SYNTAX_ERROR
;
1873 dap_ap_select(dap
, apsel
);
1875 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1876 if (retval
!= ERROR_OK
)
1878 retval
= dap_run(dap
);
1879 if (retval
!= ERROR_OK
)
1882 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1887 static const struct command_registration dap_commands
[] = {
1890 .handler
= handle_dap_info_command
,
1891 .mode
= COMMAND_EXEC
,
1892 .help
= "display ROM table for MEM-AP "
1893 "(default currently selected AP)",
1894 .usage
= "[ap_num]",
1898 .handler
= dap_apsel_command
,
1899 .mode
= COMMAND_EXEC
,
1900 .help
= "Set the currently selected AP (default 0) "
1901 "and display the result",
1902 .usage
= "[ap_num]",
1906 .handler
= dap_apid_command
,
1907 .mode
= COMMAND_EXEC
,
1908 .help
= "return ID register from AP "
1909 "(default currently selected AP)",
1910 .usage
= "[ap_num]",
1914 .handler
= dap_baseaddr_command
,
1915 .mode
= COMMAND_EXEC
,
1916 .help
= "return debug base address from MEM-AP "
1917 "(default currently selected AP)",
1918 .usage
= "[ap_num]",
1921 .name
= "memaccess",
1922 .handler
= dap_memaccess_command
,
1923 .mode
= COMMAND_EXEC
,
1924 .help
= "set/get number of extra tck for MEM-AP memory "
1925 "bus access [0-255]",
1926 .usage
= "[cycles]",
1928 COMMAND_REGISTRATION_DONE
1931 const struct command_registration dap_command_handlers
[] = {
1934 .mode
= COMMAND_EXEC
,
1935 .help
= "DAP command group",
1937 .chain
= dap_commands
,
1939 COMMAND_REGISTRATION_DONE
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)