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[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "jtag/interface.h"
76 #include "arm.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
79
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
81
82 /*
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
85 */
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
87 {
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
89 }
90
91 /***************************************************************************
92 * *
93 * DP and MEM-AP register access through APACC and DPACC *
94 * *
95 ***************************************************************************/
96
97 /**
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
101 *
102 * @param dap The DAP
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
105 */
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
107 {
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
109
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
114 */
115 dap->ap_bank_value = -1;
116 dap->ap_csw_value = -1;
117 dap->ap_tar_value = -1;
118 }
119 }
120
121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
122 {
123 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
124 dap->apcsw[dap->ap_current >> 24];
125
126 if (csw != dap->ap_csw_value) {
127 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
128 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
129 if (retval != ERROR_OK)
130 return retval;
131 dap->ap_csw_value = csw;
132 }
133 return ERROR_OK;
134 }
135
136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
137 {
138 if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
139 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
140 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
141 if (retval != ERROR_OK)
142 return retval;
143 dap->ap_tar_value = tar;
144 }
145 return ERROR_OK;
146 }
147
148 /**
149 * Queue transactions setting up transfer parameters for the
150 * currently selected MEM-AP.
151 *
152 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
153 * initiate data reads or writes using memory or peripheral addresses.
154 * If the CSW is configured for it, the TAR may be automatically
155 * incremented after each transfer.
156 *
157 * @todo Rename to reflect it being specifically a MEM-AP function.
158 *
159 * @param dap The DAP connected to the MEM-AP.
160 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
161 * matches the cached value, the register is not changed.
162 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
163 * matches the cached address, the register is not changed.
164 *
165 * @return ERROR_OK if the transaction was properly queued, else a fault code.
166 */
167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
168 {
169 int retval;
170 retval = dap_setup_accessport_csw(dap, csw);
171 if (retval != ERROR_OK)
172 return retval;
173 retval = dap_setup_accessport_tar(dap, tar);
174 if (retval != ERROR_OK)
175 return retval;
176 return ERROR_OK;
177 }
178
179 /**
180 * Asynchronous (queued) read of a word from memory or a system register.
181 *
182 * @param dap The DAP connected to the MEM-AP performing the read.
183 * @param address Address of the 32-bit word to read; it must be
184 * readable by the currently selected MEM-AP.
185 * @param value points to where the word will be stored when the
186 * transaction queue is flushed (assuming no errors).
187 *
188 * @return ERROR_OK for success. Otherwise a fault code.
189 */
190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
191 uint32_t *value)
192 {
193 int retval;
194
195 /* Use banked addressing (REG_BDx) to avoid some link traffic
196 * (updating TAR) when reading several consecutive addresses.
197 */
198 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
199 address & 0xFFFFFFF0);
200 if (retval != ERROR_OK)
201 return retval;
202
203 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
204 }
205
206 /**
207 * Synchronous read of a word from memory or a system register.
208 * As a side effect, this flushes any queued transactions.
209 *
210 * @param dap The DAP connected to the MEM-AP performing the read.
211 * @param address Address of the 32-bit word to read; it must be
212 * readable by the currently selected MEM-AP.
213 * @param value points to where the result will be stored.
214 *
215 * @return ERROR_OK for success; *value holds the result.
216 * Otherwise a fault code.
217 */
218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
219 uint32_t *value)
220 {
221 int retval;
222
223 retval = mem_ap_read_u32(dap, address, value);
224 if (retval != ERROR_OK)
225 return retval;
226
227 return dap_run(dap);
228 }
229
230 /**
231 * Asynchronous (queued) write of a word to memory or a system register.
232 *
233 * @param dap The DAP connected to the MEM-AP.
234 * @param address Address to be written; it must be writable by
235 * the currently selected MEM-AP.
236 * @param value Word that will be written to the address when transaction
237 * queue is flushed (assuming no errors).
238 *
239 * @return ERROR_OK for success. Otherwise a fault code.
240 */
241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
242 uint32_t value)
243 {
244 int retval;
245
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when writing several consecutive addresses.
248 */
249 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
250 address & 0xFFFFFFF0);
251 if (retval != ERROR_OK)
252 return retval;
253
254 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
255 value);
256 }
257
258 /**
259 * Synchronous write of a word to memory or a system register.
260 * As a side effect, this flushes any queued transactions.
261 *
262 * @param dap The DAP connected to the MEM-AP.
263 * @param address Address to be written; it must be writable by
264 * the currently selected MEM-AP.
265 * @param value Word that will be written.
266 *
267 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
268 */
269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
270 uint32_t value)
271 {
272 int retval = mem_ap_write_u32(dap, address, value);
273
274 if (retval != ERROR_OK)
275 return retval;
276
277 return dap_run(dap);
278 }
279
280 /**
281 * Synchronous write of a block of memory, using a specific access size.
282 *
283 * @param dap The DAP connected to the MEM-AP.
284 * @param buffer The data buffer to write. No particular alignment is assumed.
285 * @param size Which access size to use, in bytes. 1, 2 or 4.
286 * @param count The number of writes to do (in size units, not bytes).
287 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
288 * @param addrinc Whether the target address should be increased for each write or not. This
289 * should normally be true, except when writing to e.g. a FIFO.
290 * @return ERROR_OK on success, otherwise an error code.
291 */
292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
293 uint32_t address, bool addrinc)
294 {
295 size_t nbytes = size * count;
296 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
297 uint32_t csw_size;
298 int retval;
299
300 if (size == 4)
301 csw_size = CSW_32BIT;
302 else if (size == 2)
303 csw_size = CSW_16BIT;
304 else if (size == 1)
305 csw_size = CSW_8BIT;
306 else
307 return ERROR_TARGET_UNALIGNED_ACCESS;
308
309 retval = dap_setup_accessport_tar(dap, address);
310 if (retval != ERROR_OK)
311 return retval;
312
313 while (nbytes > 0) {
314 uint32_t this_size = size;
315
316 /* Select packed transfer if possible */
317 if (addrinc && dap->packed_transfers && nbytes >= 4
318 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
319 this_size = 4;
320 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
321 } else {
322 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
323 }
324
325 if (retval != ERROR_OK)
326 break;
327
328 /* How many source bytes each transfer will consume, and their location in the DRW,
329 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
330 uint32_t outvalue = 0;
331 switch (this_size) {
332 case 4:
333 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
334 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
335 case 2:
336 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
337 case 1:
338 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
339 }
340
341 nbytes -= this_size;
342
343 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
344 if (retval != ERROR_OK)
345 break;
346
347 /* Rewrite TAR if it wrapped */
348 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
349 retval = dap_setup_accessport_tar(dap, address);
350 if (retval != ERROR_OK)
351 break;
352 }
353 }
354
355 /* REVISIT: Might want to have a queued version of this function that does not run. */
356 if (retval == ERROR_OK)
357 retval = dap_run(dap);
358
359 if (retval != ERROR_OK) {
360 uint32_t tar;
361 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
362 && dap_run(dap) == ERROR_OK)
363 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
364 else
365 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
366 }
367
368 return retval;
369 }
370
371 /* Compatibility wrappers around mem_ap_write(). Note that the count is in bytes for these. */
372 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address, bool addr_incr)
373 {
374 return mem_ap_write(dap, buffer, 4, count / 4, address, true);
375 }
376
377 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
378 {
379 return mem_ap_write(dap, buffer, 2, count / 2, address, true);
380 }
381
382 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
383 {
384 return mem_ap_write(dap, buffer, 1, count, address, true);
385 }
386
387 /**
388 * Synchronous read of a block of memory, using a specific access size.
389 *
390 * @param dap The DAP connected to the MEM-AP.
391 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
392 * @param size Which access size to use, in bytes. 1, 2 or 4.
393 * @param count The number of reads to do (in size units, not bytes).
394 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
395 * @param addrinc Whether the target address should be increased after each read or not. This
396 * should normally be true, except when reading from e.g. a FIFO.
397 * @return ERROR_OK on success, otherwise an error code.
398 */
399 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
400 uint32_t adr, bool addrinc)
401 {
402 size_t nbytes = size * count;
403 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
404 uint32_t csw_size;
405 uint32_t address = adr;
406 int retval;
407
408 if (size == 4)
409 csw_size = CSW_32BIT;
410 else if (size == 2)
411 csw_size = CSW_16BIT;
412 else if (size == 1)
413 csw_size = CSW_8BIT;
414 else
415 return ERROR_TARGET_UNALIGNED_ACCESS;
416
417 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
418 * over-allocation if packed transfers are going to be used, but determining the real need at
419 * this point would be messy. */
420 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
421 uint32_t *read_ptr = read_buf;
422 if (read_buf == NULL) {
423 LOG_ERROR("Failed to allocate read buffer");
424 return ERROR_FAIL;
425 }
426
427 retval = dap_setup_accessport_tar(dap, address);
428 if (retval != ERROR_OK)
429 return retval;
430
431 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
432 * useful bytes it contains, and their location in the word, depends on the type of transfer
433 * and alignment. */
434 while (nbytes > 0) {
435 uint32_t this_size = size;
436
437 /* Select packed transfer if possible */
438 if (addrinc && dap->packed_transfers && nbytes >= 4
439 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
440 this_size = 4;
441 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
442 } else {
443 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
444 }
445 if (retval != ERROR_OK)
446 break;
447
448 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
449 if (retval != ERROR_OK)
450 break;
451
452 nbytes -= this_size;
453 address += this_size;
454
455 /* Rewrite TAR if it wrapped */
456 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
457 retval = dap_setup_accessport_tar(dap, address);
458 if (retval != ERROR_OK)
459 break;
460 }
461 }
462
463 if (retval == ERROR_OK)
464 retval = dap_run(dap);
465
466 /* Restore state */
467 address = adr;
468 nbytes = size * count;
469 read_ptr = read_buf;
470
471 /* If something failed, read TAR to find out how much data was successfully read, so we can
472 * at least give the caller what we have. */
473 if (retval != ERROR_OK) {
474 uint32_t tar;
475 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
476 && dap_run(dap) == ERROR_OK) {
477 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
478 if (nbytes > tar - address)
479 nbytes = tar - address;
480 } else {
481 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
482 nbytes = 0;
483 }
484 }
485
486 /* Replay loop to populate caller's buffer from the correct word and byte lane */
487 while (nbytes > 0) {
488 uint32_t this_size = size;
489
490 if (addrinc && dap->packed_transfers && nbytes >= 4
491 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
492 this_size = 4;
493 }
494
495 switch (this_size) {
496 case 4:
497 *buffer++ = *read_ptr >> 8 * (address++ & 3);
498 *buffer++ = *read_ptr >> 8 * (address++ & 3);
499 case 2:
500 *buffer++ = *read_ptr >> 8 * (address++ & 3);
501 case 1:
502 *buffer++ = *read_ptr >> 8 * (address++ & 3);
503 }
504
505 read_ptr++;
506 nbytes -= this_size;
507 }
508
509 free(read_buf);
510 return retval;
511 }
512
513 /* Compatibility wrappers around mem_ap_read(). Note that the count is in bytes for these (despite
514 * what their doxygen documentation said). */
515 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
516 int count, uint32_t address, bool addr_incr)
517 {
518 return mem_ap_read(dap, buffer, 4, count / 4, address, addr_incr);
519 }
520
521 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
522 int count, uint32_t address)
523 {
524 return mem_ap_read(dap, buffer, 2, count / 2, address, true);
525 }
526
527 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
528 int count, uint32_t address)
529 {
530 return mem_ap_read(dap, buffer, 1, count, address, true);
531 }
532
533 /*--------------------------------------------------------------------*/
534 /* Wrapping function with selection of AP */
535 /*--------------------------------------------------------------------*/
536 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
537 uint32_t address, uint32_t *value)
538 {
539 dap_ap_select(swjdp, ap);
540 return mem_ap_read_u32(swjdp, address, value);
541 }
542
543 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
544 uint32_t address, uint32_t value)
545 {
546 dap_ap_select(swjdp, ap);
547 return mem_ap_write_u32(swjdp, address, value);
548 }
549
550 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
551 uint32_t address, uint32_t *value)
552 {
553 dap_ap_select(swjdp, ap);
554 return mem_ap_read_atomic_u32(swjdp, address, value);
555 }
556
557 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
558 uint32_t address, uint32_t value)
559 {
560 dap_ap_select(swjdp, ap);
561 return mem_ap_write_atomic_u32(swjdp, address, value);
562 }
563
564 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
565 uint8_t *buffer, int count, uint32_t address)
566 {
567 dap_ap_select(swjdp, ap);
568 return mem_ap_read_buf_u8(swjdp, buffer, count, address);
569 }
570
571 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
572 uint8_t *buffer, int count, uint32_t address)
573 {
574 dap_ap_select(swjdp, ap);
575 return mem_ap_read_buf_u16(swjdp, buffer, count, address);
576 }
577
578 int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
579 uint8_t *buffer, int count, uint32_t address)
580 {
581 dap_ap_select(swjdp, ap);
582 return mem_ap_read_buf_u32(swjdp, buffer, count, address, false);
583 }
584
585 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
586 uint8_t *buffer, int count, uint32_t address)
587 {
588 dap_ap_select(swjdp, ap);
589 return mem_ap_read_buf_u32(swjdp, buffer, count, address, true);
590 }
591
592 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
593 const uint8_t *buffer, int count, uint32_t address)
594 {
595 dap_ap_select(swjdp, ap);
596 return mem_ap_write_buf_u8(swjdp, buffer, count, address);
597 }
598
599 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
600 const uint8_t *buffer, int count, uint32_t address)
601 {
602 dap_ap_select(swjdp, ap);
603 return mem_ap_write_buf_u16(swjdp, buffer, count, address);
604 }
605
606 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
607 const uint8_t *buffer, int count, uint32_t address)
608 {
609 dap_ap_select(swjdp, ap);
610 return mem_ap_write_buf_u32(swjdp, buffer, count, address, true);
611 }
612
613 int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
614 const uint8_t *buffer, int count, uint32_t address)
615 {
616 dap_ap_select(swjdp, ap);
617 return mem_ap_write_buf_u32(swjdp, buffer, count, address, false);
618 }
619
620 #define MDM_REG_STAT 0x00
621 #define MDM_REG_CTRL 0x04
622 #define MDM_REG_ID 0xfc
623
624 #define MDM_STAT_FMEACK (1<<0)
625 #define MDM_STAT_FREADY (1<<1)
626 #define MDM_STAT_SYSSEC (1<<2)
627 #define MDM_STAT_SYSRES (1<<3)
628 #define MDM_STAT_FMEEN (1<<5)
629 #define MDM_STAT_BACKDOOREN (1<<6)
630 #define MDM_STAT_LPEN (1<<7)
631 #define MDM_STAT_VLPEN (1<<8)
632 #define MDM_STAT_LLSMODEXIT (1<<9)
633 #define MDM_STAT_VLLSXMODEXIT (1<<10)
634 #define MDM_STAT_CORE_HALTED (1<<16)
635 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
636 #define MDM_STAT_CORESLEEPING (1<<18)
637
638 #define MEM_CTRL_FMEIP (1<<0)
639 #define MEM_CTRL_DBG_DIS (1<<1)
640 #define MEM_CTRL_DBG_REQ (1<<2)
641 #define MEM_CTRL_SYS_RES_REQ (1<<3)
642 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
643 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
644 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
645 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
646
647 /**
648 *
649 */
650 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
651 {
652 uint32_t val;
653 int retval;
654 enum reset_types jtag_reset_config = jtag_get_reset_config();
655
656 dap_ap_select(dap, 1);
657
658 /* first check mdm-ap id register */
659 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
660 if (retval != ERROR_OK)
661 return retval;
662 dap_run(dap);
663
664 if (val != 0x001C0000) {
665 LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val);
666 dap_ap_select(dap, 0);
667 return ERROR_FAIL;
668 }
669
670 /* read and parse status register
671 * it's important that the device is out of
672 * reset here
673 */
674 do {
675 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
676 if (retval != ERROR_OK)
677 return retval;
678 dap_run(dap);
679
680 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
681 } while (!(val & MDM_STAT_FREADY));
682
683 if ((val & MDM_STAT_SYSSEC)) {
684 LOG_DEBUG("MDMAP: system is secured, masserase needed");
685
686 if (!(val & MDM_STAT_FMEEN))
687 LOG_DEBUG("MDMAP: masserase is disabled");
688 else {
689 /* we need to assert reset */
690 if (jtag_reset_config & RESET_HAS_SRST) {
691 /* default to asserting srst */
692 adapter_assert_reset();
693 } else {
694 LOG_DEBUG("SRST not configured");
695 dap_ap_select(dap, 0);
696 return ERROR_FAIL;
697 }
698
699 while (1) {
700 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
701 if (retval != ERROR_OK)
702 return retval;
703 dap_run(dap);
704 /* read status register and wait for ready */
705 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
706 if (retval != ERROR_OK)
707 return retval;
708 dap_run(dap);
709 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
710
711 if ((val & 1))
712 break;
713 }
714
715 while (1) {
716 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
717 if (retval != ERROR_OK)
718 return retval;
719 dap_run(dap);
720 /* read status register */
721 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
722 if (retval != ERROR_OK)
723 return retval;
724 dap_run(dap);
725 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
726 /* read control register and wait for ready */
727 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
728 if (retval != ERROR_OK)
729 return retval;
730 dap_run(dap);
731 LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val);
732
733 if (val == 0x00)
734 break;
735 }
736 }
737 }
738
739 dap_ap_select(dap, 0);
740
741 return ERROR_OK;
742 }
743
744 /** */
745 struct dap_syssec_filter {
746 /** */
747 uint32_t idcode;
748 /** */
749 int (*dap_init)(struct adiv5_dap *dap);
750 };
751
752 /** */
753 static struct dap_syssec_filter dap_syssec_filter_data[] = {
754 { 0x4BA00477, dap_syssec_kinetis_mdmap }
755 };
756
757 /**
758 *
759 */
760 int dap_syssec(struct adiv5_dap *dap)
761 {
762 unsigned int i;
763 struct jtag_tap *tap;
764
765 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
766 tap = dap->jtag_info->tap;
767
768 while (tap != NULL) {
769 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
770 LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode);
771 dap_syssec_filter_data[i].dap_init(dap);
772 }
773 tap = tap->next_tap;
774 }
775 }
776
777 return ERROR_OK;
778 }
779
780 /*--------------------------------------------------------------------------*/
781
782
783 /* FIXME don't import ... just initialize as
784 * part of DAP transport setup
785 */
786 extern const struct dap_ops jtag_dp_ops;
787
788 /*--------------------------------------------------------------------------*/
789
790 /**
791 * Initialize a DAP. This sets up the power domains, prepares the DP
792 * for further use, and arranges to use AP #0 for all AP operations
793 * until dap_ap-select() changes that policy.
794 *
795 * @param dap The DAP being initialized.
796 *
797 * @todo Rename this. We also need an initialization scheme which account
798 * for SWD transports not just JTAG; that will need to address differences
799 * in layering. (JTAG is useful without any debug target; but not SWD.)
800 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
801 */
802 int ahbap_debugport_init(struct adiv5_dap *dap)
803 {
804 uint32_t ctrlstat;
805 int cnt = 0;
806 int retval;
807
808 LOG_DEBUG(" ");
809
810 /* JTAG-DP or SWJ-DP, in JTAG mode
811 * ... for SWD mode this is patched as part
812 * of link switchover
813 */
814 if (!dap->ops)
815 dap->ops = &jtag_dp_ops;
816
817 /* Default MEM-AP setup.
818 *
819 * REVISIT AP #0 may be an inappropriate default for this.
820 * Should we probe, or take a hint from the caller?
821 * Presumably we can ignore the possibility of multiple APs.
822 */
823 dap->ap_current = !0;
824 dap_ap_select(dap, 0);
825
826 /* DP initialization */
827
828 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
829 if (retval != ERROR_OK)
830 return retval;
831
832 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
833 if (retval != ERROR_OK)
834 return retval;
835
836 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
837 if (retval != ERROR_OK)
838 return retval;
839
840 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
841 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
842 if (retval != ERROR_OK)
843 return retval;
844
845 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
846 if (retval != ERROR_OK)
847 return retval;
848 retval = dap_run(dap);
849 if (retval != ERROR_OK)
850 return retval;
851
852 /* Check that we have debug power domains activated */
853 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
854 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
855 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
856 if (retval != ERROR_OK)
857 return retval;
858 retval = dap_run(dap);
859 if (retval != ERROR_OK)
860 return retval;
861 alive_sleep(10);
862 }
863
864 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
865 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
866 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
867 if (retval != ERROR_OK)
868 return retval;
869 retval = dap_run(dap);
870 if (retval != ERROR_OK)
871 return retval;
872 alive_sleep(10);
873 }
874
875 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
876 if (retval != ERROR_OK)
877 return retval;
878 /* With debug power on we can activate OVERRUN checking */
879 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
880 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
881 if (retval != ERROR_OK)
882 return retval;
883 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
884 if (retval != ERROR_OK)
885 return retval;
886
887 dap_syssec(dap);
888
889 /* check that we support packed transfers */
890 uint32_t csw;
891
892 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
893 if (retval != ERROR_OK)
894 return retval;
895
896 retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
897 if (retval != ERROR_OK)
898 return retval;
899
900 retval = dap_run(dap);
901 if (retval != ERROR_OK)
902 return retval;
903
904 if (csw & CSW_ADDRINC_PACKED)
905 dap->packed_transfers = true;
906 else
907 dap->packed_transfers = false;
908
909 LOG_DEBUG("MEM_AP Packed Transfers: %s",
910 dap->packed_transfers ? "enabled" : "disabled");
911
912 return ERROR_OK;
913 }
914
915 /* CID interpretation -- see ARM IHI 0029B section 3
916 * and ARM IHI 0031A table 13-3.
917 */
918 static const char *class_description[16] = {
919 "Reserved", "ROM table", "Reserved", "Reserved",
920 "Reserved", "Reserved", "Reserved", "Reserved",
921 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
922 "Reserved", "OptimoDE DESS",
923 "Generic IP component", "PrimeCell or System component"
924 };
925
926 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
927 {
928 return cid3 == 0xb1 && cid2 == 0x05
929 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
930 }
931
932 /*
933 * This function checks the ID for each access port to find the requested Access Port type
934 */
935 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
936 {
937 int ap;
938
939 /* Maximum AP number is 255 since the SELECT register is 8 bits */
940 for (ap = 0; ap <= 255; ap++) {
941
942 /* read the IDR register of the Access Port */
943 uint32_t id_val = 0;
944 dap_ap_select(dap, ap);
945
946 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
947 if (retval != ERROR_OK)
948 return retval;
949
950 retval = dap_run(dap);
951
952 /* IDR bits:
953 * 31-28 : Revision
954 * 27-24 : JEDEC bank (0x4 for ARM)
955 * 23-17 : JEDEC code (0x3B for ARM)
956 * 16 : Mem-AP
957 * 15-8 : Reserved
958 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
959 */
960
961 /* Reading register for a non-existant AP should not cause an error,
962 * but just to be sure, try to continue searching if an error does happen.
963 */
964 if ((retval == ERROR_OK) && /* Register read success */
965 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
966 ((id_val & 0xFF) == type_to_find)) { /* type matches*/
967
968 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
969 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
970 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
971 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
972 ap, id_val);
973
974 *ap_num_out = ap;
975 return ERROR_OK;
976 }
977 }
978
979 LOG_DEBUG("No %s found",
980 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
981 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
982 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
983 return ERROR_FAIL;
984 }
985
986 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
987 uint32_t *out_dbgbase, uint32_t *out_apid)
988 {
989 uint32_t ap_old;
990 int retval;
991 uint32_t dbgbase, apid;
992
993 /* AP address is in bits 31:24 of DP_SELECT */
994 if (ap >= 256)
995 return ERROR_COMMAND_SYNTAX_ERROR;
996
997 ap_old = dap->ap_current;
998 dap_ap_select(dap, ap);
999
1000 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1001 if (retval != ERROR_OK)
1002 return retval;
1003 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1004 if (retval != ERROR_OK)
1005 return retval;
1006 retval = dap_run(dap);
1007 if (retval != ERROR_OK)
1008 return retval;
1009
1010 /* Excavate the device ID code */
1011 struct jtag_tap *tap = dap->jtag_info->tap;
1012 while (tap != NULL) {
1013 if (tap->hasidcode)
1014 break;
1015 tap = tap->next_tap;
1016 }
1017 if (tap == NULL || !tap->hasidcode)
1018 return ERROR_OK;
1019
1020 dap_ap_select(dap, ap_old);
1021
1022 /* The asignment happens only here to prevent modification of these
1023 * values before they are certain. */
1024 *out_dbgbase = dbgbase;
1025 *out_apid = apid;
1026
1027 return ERROR_OK;
1028 }
1029
1030 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1031 uint32_t dbgbase, uint8_t type, uint32_t *addr)
1032 {
1033 uint32_t ap_old;
1034 uint32_t romentry, entry_offset = 0, component_base, devtype;
1035 int retval = ERROR_FAIL;
1036
1037 if (ap >= 256)
1038 return ERROR_COMMAND_SYNTAX_ERROR;
1039
1040 ap_old = dap->ap_current;
1041 dap_ap_select(dap, ap);
1042
1043 do {
1044 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1045 entry_offset, &romentry);
1046 if (retval != ERROR_OK)
1047 return retval;
1048
1049 component_base = (dbgbase & 0xFFFFF000)
1050 + (romentry & 0xFFFFF000);
1051
1052 if (romentry & 0x1) {
1053 retval = mem_ap_read_atomic_u32(dap,
1054 (component_base & 0xfffff000) | 0xfcc,
1055 &devtype);
1056 if (retval != ERROR_OK)
1057 return retval;
1058 if ((devtype & 0xff) == type) {
1059 *addr = component_base;
1060 retval = ERROR_OK;
1061 break;
1062 }
1063 }
1064 entry_offset += 4;
1065 } while (romentry > 0);
1066
1067 dap_ap_select(dap, ap_old);
1068
1069 return retval;
1070 }
1071
1072 static int dap_info_command(struct command_context *cmd_ctx,
1073 struct adiv5_dap *dap, int ap)
1074 {
1075 int retval;
1076 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1077 int romtable_present = 0;
1078 uint8_t mem_ap;
1079 uint32_t ap_old;
1080
1081 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1082 if (retval != ERROR_OK)
1083 return retval;
1084
1085 ap_old = dap->ap_current;
1086 dap_ap_select(dap, ap);
1087
1088 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1089 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1090 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1091 if (apid) {
1092 switch (apid&0x0F) {
1093 case 0:
1094 command_print(cmd_ctx, "\tType is JTAG-AP");
1095 break;
1096 case 1:
1097 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1098 break;
1099 case 2:
1100 command_print(cmd_ctx, "\tType is MEM-AP APB");
1101 break;
1102 default:
1103 command_print(cmd_ctx, "\tUnknown AP type");
1104 break;
1105 }
1106
1107 /* NOTE: a MEM-AP may have a single CoreSight component that's
1108 * not a ROM table ... or have no such components at all.
1109 */
1110 if (mem_ap)
1111 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1112 } else
1113 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1114
1115 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1116 if (romtable_present) {
1117 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1118 uint16_t entry_offset;
1119
1120 /* bit 16 of apid indicates a memory access port */
1121 if (dbgbase & 0x02)
1122 command_print(cmd_ctx, "\tValid ROM table present");
1123 else
1124 command_print(cmd_ctx, "\tROM table in legacy format");
1125
1126 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1127 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1128 if (retval != ERROR_OK)
1129 return retval;
1130 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1131 if (retval != ERROR_OK)
1132 return retval;
1133 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1134 if (retval != ERROR_OK)
1135 return retval;
1136 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1137 if (retval != ERROR_OK)
1138 return retval;
1139 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1140 if (retval != ERROR_OK)
1141 return retval;
1142 retval = dap_run(dap);
1143 if (retval != ERROR_OK)
1144 return retval;
1145
1146 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1147 command_print(cmd_ctx, "\tCID3 0x%2.2x"
1148 ", CID2 0x%2.2x"
1149 ", CID1 0x%2.2x"
1150 ", CID0 0x%2.2x",
1151 (unsigned) cid3, (unsigned)cid2,
1152 (unsigned) cid1, (unsigned) cid0);
1153 if (memtype & 0x01)
1154 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1155 else
1156 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1157 "Dedicated debug bus.");
1158
1159 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1160 entry_offset = 0;
1161 do {
1162 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1163 if (retval != ERROR_OK)
1164 return retval;
1165 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1166 if (romentry & 0x01) {
1167 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1168 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1169 uint32_t component_base;
1170 unsigned part_num;
1171 char *type, *full;
1172
1173 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1174
1175 /* IDs are in last 4K section */
1176 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1177 if (retval != ERROR_OK)
1178 return retval;
1179 c_pid0 &= 0xff;
1180 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1181 if (retval != ERROR_OK)
1182 return retval;
1183 c_pid1 &= 0xff;
1184 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1185 if (retval != ERROR_OK)
1186 return retval;
1187 c_pid2 &= 0xff;
1188 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1189 if (retval != ERROR_OK)
1190 return retval;
1191 c_pid3 &= 0xff;
1192 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1193 if (retval != ERROR_OK)
1194 return retval;
1195 c_pid4 &= 0xff;
1196
1197 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1198 if (retval != ERROR_OK)
1199 return retval;
1200 c_cid0 &= 0xff;
1201 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1202 if (retval != ERROR_OK)
1203 return retval;
1204 c_cid1 &= 0xff;
1205 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1206 if (retval != ERROR_OK)
1207 return retval;
1208 c_cid2 &= 0xff;
1209 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1210 if (retval != ERROR_OK)
1211 return retval;
1212 c_cid3 &= 0xff;
1213
1214 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1215 "start address 0x%" PRIx32, component_base,
1216 /* component may take multiple 4K pages */
1217 component_base - 0x1000*(c_pid4 >> 4));
1218 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1219 (int) (c_cid1 >> 4) & 0xf,
1220 /* See ARM IHI 0029B Table 3-3 */
1221 class_description[(c_cid1 >> 4) & 0xf]);
1222
1223 /* CoreSight component? */
1224 if (((c_cid1 >> 4) & 0x0f) == 9) {
1225 uint32_t devtype;
1226 unsigned minor;
1227 char *major = "Reserved", *subtype = "Reserved";
1228
1229 retval = mem_ap_read_atomic_u32(dap,
1230 (component_base & 0xfffff000) | 0xfcc,
1231 &devtype);
1232 if (retval != ERROR_OK)
1233 return retval;
1234 minor = (devtype >> 4) & 0x0f;
1235 switch (devtype & 0x0f) {
1236 case 0:
1237 major = "Miscellaneous";
1238 switch (minor) {
1239 case 0:
1240 subtype = "other";
1241 break;
1242 case 4:
1243 subtype = "Validation component";
1244 break;
1245 }
1246 break;
1247 case 1:
1248 major = "Trace Sink";
1249 switch (minor) {
1250 case 0:
1251 subtype = "other";
1252 break;
1253 case 1:
1254 subtype = "Port";
1255 break;
1256 case 2:
1257 subtype = "Buffer";
1258 break;
1259 }
1260 break;
1261 case 2:
1262 major = "Trace Link";
1263 switch (minor) {
1264 case 0:
1265 subtype = "other";
1266 break;
1267 case 1:
1268 subtype = "Funnel, router";
1269 break;
1270 case 2:
1271 subtype = "Filter";
1272 break;
1273 case 3:
1274 subtype = "FIFO, buffer";
1275 break;
1276 }
1277 break;
1278 case 3:
1279 major = "Trace Source";
1280 switch (minor) {
1281 case 0:
1282 subtype = "other";
1283 break;
1284 case 1:
1285 subtype = "Processor";
1286 break;
1287 case 2:
1288 subtype = "DSP";
1289 break;
1290 case 3:
1291 subtype = "Engine/Coprocessor";
1292 break;
1293 case 4:
1294 subtype = "Bus";
1295 break;
1296 }
1297 break;
1298 case 4:
1299 major = "Debug Control";
1300 switch (minor) {
1301 case 0:
1302 subtype = "other";
1303 break;
1304 case 1:
1305 subtype = "Trigger Matrix";
1306 break;
1307 case 2:
1308 subtype = "Debug Auth";
1309 break;
1310 }
1311 break;
1312 case 5:
1313 major = "Debug Logic";
1314 switch (minor) {
1315 case 0:
1316 subtype = "other";
1317 break;
1318 case 1:
1319 subtype = "Processor";
1320 break;
1321 case 2:
1322 subtype = "DSP";
1323 break;
1324 case 3:
1325 subtype = "Engine/Coprocessor";
1326 break;
1327 }
1328 break;
1329 }
1330 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1331 (unsigned) (devtype & 0xff),
1332 major, subtype);
1333 /* REVISIT also show 0xfc8 DevId */
1334 }
1335
1336 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1337 command_print(cmd_ctx,
1338 "\t\tCID3 0%2.2x"
1339 ", CID2 0%2.2x"
1340 ", CID1 0%2.2x"
1341 ", CID0 0%2.2x",
1342 (int) c_cid3,
1343 (int) c_cid2,
1344 (int)c_cid1,
1345 (int)c_cid0);
1346 command_print(cmd_ctx,
1347 "\t\tPeripheral ID[4..0] = hex "
1348 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1349 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1350 (int) c_pid1, (int) c_pid0);
1351
1352 /* Part number interpretations are from Cortex
1353 * core specs, the CoreSight components TRM
1354 * (ARM DDI 0314H), CoreSight System Design
1355 * Guide (ARM DGI 0012D) and ETM specs; also
1356 * from chip observation (e.g. TI SDTI).
1357 */
1358 part_num = (c_pid0 & 0xff);
1359 part_num |= (c_pid1 & 0x0f) << 8;
1360 switch (part_num) {
1361 case 0x000:
1362 type = "Cortex-M3 NVIC";
1363 full = "(Interrupt Controller)";
1364 break;
1365 case 0x001:
1366 type = "Cortex-M3 ITM";
1367 full = "(Instrumentation Trace Module)";
1368 break;
1369 case 0x002:
1370 type = "Cortex-M3 DWT";
1371 full = "(Data Watchpoint and Trace)";
1372 break;
1373 case 0x003:
1374 type = "Cortex-M3 FBP";
1375 full = "(Flash Patch and Breakpoint)";
1376 break;
1377 case 0x00c:
1378 type = "Cortex-M4 SCS";
1379 full = "(System Control Space)";
1380 break;
1381 case 0x00d:
1382 type = "CoreSight ETM11";
1383 full = "(Embedded Trace)";
1384 break;
1385 /* case 0x113: what? */
1386 case 0x120: /* from OMAP3 memmap */
1387 type = "TI SDTI";
1388 full = "(System Debug Trace Interface)";
1389 break;
1390 case 0x343: /* from OMAP3 memmap */
1391 type = "TI DAPCTL";
1392 full = "";
1393 break;
1394 case 0x906:
1395 type = "Coresight CTI";
1396 full = "(Cross Trigger)";
1397 break;
1398 case 0x907:
1399 type = "Coresight ETB";
1400 full = "(Trace Buffer)";
1401 break;
1402 case 0x908:
1403 type = "Coresight CSTF";
1404 full = "(Trace Funnel)";
1405 break;
1406 case 0x910:
1407 type = "CoreSight ETM9";
1408 full = "(Embedded Trace)";
1409 break;
1410 case 0x912:
1411 type = "Coresight TPIU";
1412 full = "(Trace Port Interface Unit)";
1413 break;
1414 case 0x921:
1415 type = "Cortex-A8 ETM";
1416 full = "(Embedded Trace)";
1417 break;
1418 case 0x922:
1419 type = "Cortex-A8 CTI";
1420 full = "(Cross Trigger)";
1421 break;
1422 case 0x923:
1423 type = "Cortex-M3 TPIU";
1424 full = "(Trace Port Interface Unit)";
1425 break;
1426 case 0x924:
1427 type = "Cortex-M3 ETM";
1428 full = "(Embedded Trace)";
1429 break;
1430 case 0x925:
1431 type = "Cortex-M4 ETM";
1432 full = "(Embedded Trace)";
1433 break;
1434 case 0x930:
1435 type = "Cortex-R4 ETM";
1436 full = "(Embedded Trace)";
1437 break;
1438 case 0x9a1:
1439 type = "Cortex-M4 TPUI";
1440 full = "(Trace Port Interface Unit)";
1441 break;
1442 case 0xc08:
1443 type = "Cortex-A8 Debug";
1444 full = "(Debug Unit)";
1445 break;
1446 default:
1447 type = "-*- unrecognized -*-";
1448 full = "";
1449 break;
1450 }
1451 command_print(cmd_ctx, "\t\tPart is %s %s",
1452 type, full);
1453 } else {
1454 if (romentry)
1455 command_print(cmd_ctx, "\t\tComponent not present");
1456 else
1457 command_print(cmd_ctx, "\t\tEnd of ROM table");
1458 }
1459 entry_offset += 4;
1460 } while (romentry > 0);
1461 } else
1462 command_print(cmd_ctx, "\tNo ROM table present");
1463 dap_ap_select(dap, ap_old);
1464
1465 return ERROR_OK;
1466 }
1467
1468 COMMAND_HANDLER(handle_dap_info_command)
1469 {
1470 struct target *target = get_current_target(CMD_CTX);
1471 struct arm *arm = target_to_arm(target);
1472 struct adiv5_dap *dap = arm->dap;
1473 uint32_t apsel;
1474
1475 switch (CMD_ARGC) {
1476 case 0:
1477 apsel = dap->apsel;
1478 break;
1479 case 1:
1480 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1481 break;
1482 default:
1483 return ERROR_COMMAND_SYNTAX_ERROR;
1484 }
1485
1486 return dap_info_command(CMD_CTX, dap, apsel);
1487 }
1488
1489 COMMAND_HANDLER(dap_baseaddr_command)
1490 {
1491 struct target *target = get_current_target(CMD_CTX);
1492 struct arm *arm = target_to_arm(target);
1493 struct adiv5_dap *dap = arm->dap;
1494
1495 uint32_t apsel, baseaddr;
1496 int retval;
1497
1498 switch (CMD_ARGC) {
1499 case 0:
1500 apsel = dap->apsel;
1501 break;
1502 case 1:
1503 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1504 /* AP address is in bits 31:24 of DP_SELECT */
1505 if (apsel >= 256)
1506 return ERROR_COMMAND_SYNTAX_ERROR;
1507 break;
1508 default:
1509 return ERROR_COMMAND_SYNTAX_ERROR;
1510 }
1511
1512 dap_ap_select(dap, apsel);
1513
1514 /* NOTE: assumes we're talking to a MEM-AP, which
1515 * has a base address. There are other kinds of AP,
1516 * though they're not common for now. This should
1517 * use the ID register to verify it's a MEM-AP.
1518 */
1519 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1520 if (retval != ERROR_OK)
1521 return retval;
1522 retval = dap_run(dap);
1523 if (retval != ERROR_OK)
1524 return retval;
1525
1526 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1527
1528 return retval;
1529 }
1530
1531 COMMAND_HANDLER(dap_memaccess_command)
1532 {
1533 struct target *target = get_current_target(CMD_CTX);
1534 struct arm *arm = target_to_arm(target);
1535 struct adiv5_dap *dap = arm->dap;
1536
1537 uint32_t memaccess_tck;
1538
1539 switch (CMD_ARGC) {
1540 case 0:
1541 memaccess_tck = dap->memaccess_tck;
1542 break;
1543 case 1:
1544 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1545 break;
1546 default:
1547 return ERROR_COMMAND_SYNTAX_ERROR;
1548 }
1549 dap->memaccess_tck = memaccess_tck;
1550
1551 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1552 dap->memaccess_tck);
1553
1554 return ERROR_OK;
1555 }
1556
1557 COMMAND_HANDLER(dap_apsel_command)
1558 {
1559 struct target *target = get_current_target(CMD_CTX);
1560 struct arm *arm = target_to_arm(target);
1561 struct adiv5_dap *dap = arm->dap;
1562
1563 uint32_t apsel, apid;
1564 int retval;
1565
1566 switch (CMD_ARGC) {
1567 case 0:
1568 apsel = 0;
1569 break;
1570 case 1:
1571 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1572 /* AP address is in bits 31:24 of DP_SELECT */
1573 if (apsel >= 256)
1574 return ERROR_COMMAND_SYNTAX_ERROR;
1575 break;
1576 default:
1577 return ERROR_COMMAND_SYNTAX_ERROR;
1578 }
1579
1580 dap->apsel = apsel;
1581 dap_ap_select(dap, apsel);
1582
1583 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1584 if (retval != ERROR_OK)
1585 return retval;
1586 retval = dap_run(dap);
1587 if (retval != ERROR_OK)
1588 return retval;
1589
1590 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1591 apsel, apid);
1592
1593 return retval;
1594 }
1595
1596 COMMAND_HANDLER(dap_apcsw_command)
1597 {
1598 struct target *target = get_current_target(CMD_CTX);
1599 struct arm *arm = target_to_arm(target);
1600 struct adiv5_dap *dap = arm->dap;
1601
1602 uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1603
1604 switch (CMD_ARGC) {
1605 case 0:
1606 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1607 (dap->apsel), apcsw);
1608 break;
1609 case 1:
1610 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1611 /* AP address is in bits 31:24 of DP_SELECT */
1612 if (sprot > 1)
1613 return ERROR_COMMAND_SYNTAX_ERROR;
1614 if (sprot)
1615 apcsw |= CSW_SPROT;
1616 else
1617 apcsw &= ~CSW_SPROT;
1618 break;
1619 default:
1620 return ERROR_COMMAND_SYNTAX_ERROR;
1621 }
1622 dap->apcsw[dap->apsel] = apcsw;
1623
1624 return 0;
1625 }
1626
1627
1628
1629 COMMAND_HANDLER(dap_apid_command)
1630 {
1631 struct target *target = get_current_target(CMD_CTX);
1632 struct arm *arm = target_to_arm(target);
1633 struct adiv5_dap *dap = arm->dap;
1634
1635 uint32_t apsel, apid;
1636 int retval;
1637
1638 switch (CMD_ARGC) {
1639 case 0:
1640 apsel = dap->apsel;
1641 break;
1642 case 1:
1643 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1644 /* AP address is in bits 31:24 of DP_SELECT */
1645 if (apsel >= 256)
1646 return ERROR_COMMAND_SYNTAX_ERROR;
1647 break;
1648 default:
1649 return ERROR_COMMAND_SYNTAX_ERROR;
1650 }
1651
1652 dap_ap_select(dap, apsel);
1653
1654 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1655 if (retval != ERROR_OK)
1656 return retval;
1657 retval = dap_run(dap);
1658 if (retval != ERROR_OK)
1659 return retval;
1660
1661 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1662
1663 return retval;
1664 }
1665
1666 static const struct command_registration dap_commands[] = {
1667 {
1668 .name = "info",
1669 .handler = handle_dap_info_command,
1670 .mode = COMMAND_EXEC,
1671 .help = "display ROM table for MEM-AP "
1672 "(default currently selected AP)",
1673 .usage = "[ap_num]",
1674 },
1675 {
1676 .name = "apsel",
1677 .handler = dap_apsel_command,
1678 .mode = COMMAND_EXEC,
1679 .help = "Set the currently selected AP (default 0) "
1680 "and display the result",
1681 .usage = "[ap_num]",
1682 },
1683 {
1684 .name = "apcsw",
1685 .handler = dap_apcsw_command,
1686 .mode = COMMAND_EXEC,
1687 .help = "Set csw access bit ",
1688 .usage = "[sprot]",
1689 },
1690
1691 {
1692 .name = "apid",
1693 .handler = dap_apid_command,
1694 .mode = COMMAND_EXEC,
1695 .help = "return ID register from AP "
1696 "(default currently selected AP)",
1697 .usage = "[ap_num]",
1698 },
1699 {
1700 .name = "baseaddr",
1701 .handler = dap_baseaddr_command,
1702 .mode = COMMAND_EXEC,
1703 .help = "return debug base address from MEM-AP "
1704 "(default currently selected AP)",
1705 .usage = "[ap_num]",
1706 },
1707 {
1708 .name = "memaccess",
1709 .handler = dap_memaccess_command,
1710 .mode = COMMAND_EXEC,
1711 .help = "set/get number of extra tck for MEM-AP memory "
1712 "bus access [0-255]",
1713 .usage = "[cycles]",
1714 },
1715 COMMAND_REGISTRATION_DONE
1716 };
1717
1718 const struct command_registration dap_command_handlers[] = {
1719 {
1720 .name = "dap",
1721 .mode = COMMAND_EXEC,
1722 .help = "DAP command group",
1723 .usage = "",
1724 .chain = dap_commands,
1725 },
1726 COMMAND_REGISTRATION_DONE
1727 };
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