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434b5c9931dae5d590a9e1d2d92a3e9d7596c2f4
[openocd.git] / src / target / arm9tdmi.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm9tdmi.h"
25
26 #include "arm7_9_common.h"
27 #include "register.h"
28 #include "target.h"
29 #include "armv4_5.h"
30 #include "embeddedice.h"
31 #include "etm.h"
32 #include "log.h"
33 #include "jtag.h"
34 #include "arm_jtag.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43 /* cli handling */
44 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
45
46 /* forward declarations */
47 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
48 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
49 int arm9tdmi_quit();
50
51 target_type_t arm9tdmi_target =
52 {
53 .name = "arm9tdmi",
54
55 .poll = arm7_9_poll,
56 .arch_state = armv4_5_arch_state,
57
58 .halt = arm7_9_halt,
59 .resume = arm7_9_resume,
60 .step = arm7_9_step,
61
62 .assert_reset = arm7_9_assert_reset,
63 .deassert_reset = arm7_9_deassert_reset,
64 .soft_reset_halt = arm7_9_soft_reset_halt,
65
66 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
67
68 .read_memory = arm7_9_read_memory,
69 .write_memory = arm7_9_write_memory,
70 .bulk_write_memory = arm7_9_bulk_write_memory,
71
72 .run_algorithm = armv4_5_run_algorithm,
73
74 .add_breakpoint = arm7_9_add_breakpoint,
75 .remove_breakpoint = arm7_9_remove_breakpoint,
76 .add_watchpoint = arm7_9_add_watchpoint,
77 .remove_watchpoint = arm7_9_remove_watchpoint,
78
79 .register_commands = arm9tdmi_register_commands,
80 .target_command = arm9tdmi_target_command,
81 .init_target = arm9tdmi_init_target,
82 .quit = arm9tdmi_quit
83 };
84
85 int arm9tdmi_examine_debug_reason(target_t *target)
86 {
87 /* get pointers to arch-specific information */
88 armv4_5_common_t *armv4_5 = target->arch_info;
89 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
90
91 /* only check the debug reason if we don't know it already */
92 if ((target->debug_reason != DBG_REASON_DBGRQ)
93 && (target->debug_reason != DBG_REASON_SINGLESTEP))
94 {
95 scan_field_t fields[3];
96 u8 databus[4];
97 u8 instructionbus[4];
98 u8 debug_reason;
99
100 jtag_add_end_state(TAP_PD);
101
102 fields[0].device = arm7_9->jtag_info.chain_pos;
103 fields[0].num_bits = 32;
104 fields[0].out_value = NULL;
105 fields[0].out_mask = NULL;
106 fields[0].in_value = databus;
107 fields[0].in_check_value = NULL;
108 fields[0].in_check_mask = NULL;
109 fields[0].in_handler = NULL;
110 fields[0].in_handler_priv = NULL;
111
112 fields[1].device = arm7_9->jtag_info.chain_pos;
113 fields[1].num_bits = 3;
114 fields[1].out_value = NULL;
115 fields[1].out_mask = NULL;
116 fields[1].in_value = &debug_reason;
117 fields[1].in_check_value = NULL;
118 fields[1].in_check_mask = NULL;
119 fields[1].in_handler = NULL;
120 fields[1].in_handler_priv = NULL;
121
122 fields[2].device = arm7_9->jtag_info.chain_pos;
123 fields[2].num_bits = 32;
124 fields[2].out_value = NULL;
125 fields[2].out_mask = NULL;
126 fields[2].in_value = instructionbus;
127 fields[2].in_check_value = NULL;
128 fields[2].in_check_mask = NULL;
129 fields[2].in_handler = NULL;
130 fields[2].in_handler_priv = NULL;
131
132 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
133 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
134
135 jtag_add_dr_scan(3, fields, TAP_PD);
136 jtag_execute_queue();
137
138 fields[0].in_value = NULL;
139 fields[0].out_value = databus;
140 fields[1].in_value = NULL;
141 fields[1].out_value = &debug_reason;
142 fields[2].in_value = NULL;
143 fields[2].out_value = instructionbus;
144
145 jtag_add_dr_scan(3, fields, TAP_PD);
146
147 if (debug_reason & 0x4)
148 if (debug_reason & 0x2)
149 target->debug_reason = DBG_REASON_WPTANDBKPT;
150 else
151 target->debug_reason = DBG_REASON_WATCHPOINT;
152 else
153 target->debug_reason = DBG_REASON_BREAKPOINT;
154 }
155
156 return ERROR_OK;
157 }
158
159 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
160 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
161 {
162 scan_field_t fields[3];
163 u8 out_buf[4];
164 u8 instr_buf[4];
165 u8 sysspeed_buf = 0x0;
166
167 /* prepare buffer */
168 buf_set_u32(out_buf, 0, 32, out);
169
170 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
171
172 if (sysspeed)
173 buf_set_u32(&sysspeed_buf, 2, 1, 1);
174
175 jtag_add_end_state(TAP_PD);
176 arm_jtag_scann(jtag_info, 0x1);
177 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
178
179 fields[0].device = jtag_info->chain_pos;
180 fields[0].num_bits = 32;
181 fields[0].out_value = out_buf;
182 fields[0].out_mask = NULL;
183 fields[0].in_value = NULL;
184 if (in)
185 {
186 fields[0].in_handler = arm_jtag_buf_to_u32;
187 fields[0].in_handler_priv = in;
188 }
189 else
190 {
191 fields[0].in_handler = NULL;
192 fields[0].in_handler_priv = NULL;
193 }
194 fields[0].in_check_value = NULL;
195 fields[0].in_check_mask = NULL;
196
197 fields[1].device = jtag_info->chain_pos;
198 fields[1].num_bits = 3;
199 fields[1].out_value = &sysspeed_buf;
200 fields[1].out_mask = NULL;
201 fields[1].in_value = NULL;
202 fields[1].in_check_value = NULL;
203 fields[1].in_check_mask = NULL;
204 fields[1].in_handler = NULL;
205 fields[1].in_handler_priv = NULL;
206
207 fields[2].device = jtag_info->chain_pos;
208 fields[2].num_bits = 32;
209 fields[2].out_value = instr_buf;
210 fields[2].out_mask = NULL;
211 fields[2].in_value = NULL;
212 fields[2].in_check_value = NULL;
213 fields[2].in_check_mask = NULL;
214 fields[2].in_handler = NULL;
215 fields[2].in_handler_priv = NULL;
216
217 jtag_add_dr_scan(3, fields, -1);
218
219 jtag_add_runtest(0, -1);
220
221 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
222 {
223 jtag_execute_queue();
224
225 if (in)
226 {
227 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
228 }
229 else
230 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
231 }
232 #endif
233
234 return ERROR_OK;
235 }
236
237 /* just read data (instruction and data-out = don't care) */
238 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
239 {
240 scan_field_t fields[3];
241
242 jtag_add_end_state(TAP_PD);
243 arm_jtag_scann(jtag_info, 0x1);
244 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
245
246 fields[0].device = jtag_info->chain_pos;
247 fields[0].num_bits = 32;
248 fields[0].out_value = NULL;
249 fields[0].out_mask = NULL;
250 fields[0].in_value = NULL;
251 fields[0].in_handler = arm_jtag_buf_to_u32;
252 fields[0].in_handler_priv = in;
253 fields[0].in_check_value = NULL;
254 fields[0].in_check_mask = NULL;
255
256 fields[1].device = jtag_info->chain_pos;
257 fields[1].num_bits = 3;
258 fields[1].out_value = NULL;
259 fields[1].out_mask = NULL;
260 fields[1].in_value = NULL;
261 fields[1].in_handler = NULL;
262 fields[1].in_handler_priv = NULL;
263 fields[1].in_check_value = NULL;
264 fields[1].in_check_mask = NULL;
265
266 fields[2].device = jtag_info->chain_pos;
267 fields[2].num_bits = 32;
268 fields[2].out_value = NULL;
269 fields[2].out_mask = NULL;
270 fields[2].in_value = NULL;
271 fields[2].in_check_value = NULL;
272 fields[2].in_check_mask = NULL;
273 fields[2].in_handler = NULL;
274 fields[2].in_handler_priv = NULL;
275
276 jtag_add_dr_scan(3, fields, -1);
277
278 jtag_add_runtest(0, -1);
279
280 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
281 {
282 jtag_execute_queue();
283
284 if (in)
285 {
286 DEBUG("in: 0x%8.8x", *in);
287 }
288 else
289 {
290 ERROR("BUG: called with in == NULL");
291 }
292 }
293 #endif
294
295 return ERROR_OK;
296 }
297
298 /* clock the target, and read the databus
299 * the *in pointer points to a buffer where elements of 'size' bytes
300 * are stored in big (be==1) or little (be==0) endianness
301 */
302 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
303 {
304 scan_field_t fields[3];
305
306 jtag_add_end_state(TAP_PD);
307 arm_jtag_scann(jtag_info, 0x1);
308 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
309
310 fields[0].device = jtag_info->chain_pos;
311 fields[0].num_bits = 32;
312 fields[0].out_value = NULL;
313 fields[0].out_mask = NULL;
314 fields[0].in_value = NULL;
315 switch (size)
316 {
317 case 4:
318 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
319 break;
320 case 2:
321 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
322 break;
323 case 1:
324 fields[0].in_handler = arm_jtag_buf_to_8;
325 break;
326 }
327 fields[0].in_handler_priv = in;
328 fields[0].in_check_value = NULL;
329 fields[0].in_check_mask = NULL;
330
331 fields[1].device = jtag_info->chain_pos;
332 fields[1].num_bits = 3;
333 fields[1].out_value = NULL;
334 fields[1].out_mask = NULL;
335 fields[1].in_value = NULL;
336 fields[1].in_handler = NULL;
337 fields[1].in_handler_priv = NULL;
338 fields[1].in_check_value = NULL;
339 fields[1].in_check_mask = NULL;
340
341 fields[2].device = jtag_info->chain_pos;
342 fields[2].num_bits = 32;
343 fields[2].out_value = NULL;
344 fields[2].out_mask = NULL;
345 fields[2].in_value = NULL;
346 fields[2].in_check_value = NULL;
347 fields[2].in_check_mask = NULL;
348 fields[2].in_handler = NULL;
349 fields[2].in_handler_priv = NULL;
350
351 jtag_add_dr_scan(3, fields, -1);
352
353 jtag_add_runtest(0, -1);
354
355 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
356 {
357 jtag_execute_queue();
358
359 if (in)
360 {
361 DEBUG("in: 0x%8.8x", *in);
362 }
363 else
364 {
365 ERROR("BUG: called with in == NULL");
366 }
367 }
368 #endif
369
370 return ERROR_OK;
371 }
372
373 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
374 {
375 /* get pointers to arch-specific information */
376 armv4_5_common_t *armv4_5 = target->arch_info;
377 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
378 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
379
380 /* save r0 before using it and put system in ARM state
381 * to allow common handling of ARM and THUMB debugging */
382
383 /* fetch STR r0, [r0] */
384 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
385 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
386 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
387 /* STR r0, [r0] in Memory */
388 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
389
390 /* MOV r0, r15 fetched, STR in Decode */
391 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
392 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
393 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
394 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
395 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
396 /* nothing fetched, STR r0, [r0] in Memory */
397 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
398
399 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
400 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
401 /* LDR in Decode */
402 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
403 /* LDR in Execute */
404 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
405 /* LDR in Memory (to account for interlock) */
406 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
407
408 /* fetch BX */
409 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
410 /* NOP fetched, BX in Decode, MOV in Execute */
411 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
412 /* NOP fetched, BX in Execute (1) */
413 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
414
415 jtag_execute_queue();
416
417 /* fix program counter:
418 * MOV r0, r15 was the 5th instruction (+8)
419 * reading PC in Thumb state gives address of instruction + 4
420 */
421 *pc -= 0xc;
422 }
423
424 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
425 {
426 int i;
427 /* get pointers to arch-specific information */
428 armv4_5_common_t *armv4_5 = target->arch_info;
429 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
430 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
431
432 /* STMIA r0-15, [r0] at debug speed
433 * register values will start to appear on 4th DCLK
434 */
435 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
436
437 /* fetch NOP, STM in DECODE stage */
438 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
439 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
440 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
441
442 for (i = 0; i <= 15; i++)
443 {
444 if (mask & (1 << i))
445 /* nothing fetched, STM in MEMORY (i'th cycle) */
446 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
447 }
448
449 }
450
451 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
452 {
453 int i;
454 /* get pointers to arch-specific information */
455 armv4_5_common_t *armv4_5 = target->arch_info;
456 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
457 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
458 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
459 u32 *buf_u32 = buffer;
460 u16 *buf_u16 = buffer;
461 u8 *buf_u8 = buffer;
462
463 /* STMIA r0-15, [r0] at debug speed
464 * register values will start to appear on 4th DCLK
465 */
466 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
467
468 /* fetch NOP, STM in DECODE stage */
469 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
470 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
471 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
472
473 for (i = 0; i <= 15; i++)
474 {
475 if (mask & (1 << i))
476 /* nothing fetched, STM in MEMORY (i'th cycle) */
477 switch (size)
478 {
479 case 4:
480 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
481 break;
482 case 2:
483 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
484 break;
485 case 1:
486 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
487 break;
488 }
489 }
490
491 }
492
493 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
494 {
495 /* get pointers to arch-specific information */
496 armv4_5_common_t *armv4_5 = target->arch_info;
497 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
498 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
499
500 /* MRS r0, cpsr */
501 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
502 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
503 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
504 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
505 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
506
507 /* STR r0, [r15] */
508 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
509 /* fetch NOP, STR in DECODE stage */
510 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
511 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
512 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
513 /* nothing fetched, STR in MEMORY */
514 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
515
516 }
517
518 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
519 {
520 /* get pointers to arch-specific information */
521 armv4_5_common_t *armv4_5 = target->arch_info;
522 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
523 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
524
525 DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
526
527 /* MSR1 fetched */
528 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
529 /* MSR2 fetched, MSR1 in DECODE */
530 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
531 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
532 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
533 /* nothing fetched, MSR1 in EXECUTE (2) */
534 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
535 /* nothing fetched, MSR1 in EXECUTE (3) */
536 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
537 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
538 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
539 /* nothing fetched, MSR2 in EXECUTE (2) */
540 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
541 /* nothing fetched, MSR2 in EXECUTE (3) */
542 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
543 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
544 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
545 /* nothing fetched, MSR3 in EXECUTE (2) */
546 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
547 /* nothing fetched, MSR3 in EXECUTE (3) */
548 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
549 /* NOP fetched, MSR4 in EXECUTE (1) */
550 /* last MSR writes flags, which takes only one cycle */
551 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
552 }
553
554 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
555 {
556 /* get pointers to arch-specific information */
557 armv4_5_common_t *armv4_5 = target->arch_info;
558 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
559 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
560
561 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
562
563 /* MSR fetched */
564 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
565 /* NOP fetched, MSR in DECODE */
566 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
567 /* NOP fetched, MSR in EXECUTE (1) */
568 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
569
570 /* rot == 4 writes flags, which takes only one cycle */
571 if (rot != 4)
572 {
573 /* nothing fetched, MSR in EXECUTE (2) */
574 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
575 /* nothing fetched, MSR in EXECUTE (3) */
576 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
577 }
578 }
579
580 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
581 {
582 int i;
583 /* get pointers to arch-specific information */
584 armv4_5_common_t *armv4_5 = target->arch_info;
585 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
586 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
587
588 /* LDMIA r0-15, [r0] at debug speed
589 * register values will start to appear on 4th DCLK
590 */
591 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
592
593 /* fetch NOP, LDM in DECODE stage */
594 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
595 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
596 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
597
598 for (i = 0; i <= 15; i++)
599 {
600 if (mask & (1 << i))
601 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
602 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
603 }
604 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
605
606 }
607
608 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
609 {
610 /* get pointers to arch-specific information */
611 armv4_5_common_t *armv4_5 = target->arch_info;
612 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
613 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
614
615 /* put system-speed load-multiple into the pipeline */
616 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
617 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
618
619 }
620
621 void arm9tdmi_load_hword_reg(target_t *target, int num)
622 {
623 /* get pointers to arch-specific information */
624 armv4_5_common_t *armv4_5 = target->arch_info;
625 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
626 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
627
628 /* put system-speed load half-word into the pipeline */
629 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
630 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
631 }
632
633 void arm9tdmi_load_byte_reg(target_t *target, int num)
634 {
635 /* get pointers to arch-specific information */
636 armv4_5_common_t *armv4_5 = target->arch_info;
637 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
638 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
639
640 /* put system-speed load byte into the pipeline */
641 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
642 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
643
644 }
645
646 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
647 {
648 /* get pointers to arch-specific information */
649 armv4_5_common_t *armv4_5 = target->arch_info;
650 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
651 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
652
653 /* put system-speed store-multiple into the pipeline */
654 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
655 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
656
657 }
658
659 void arm9tdmi_store_hword_reg(target_t *target, int num)
660 {
661 /* get pointers to arch-specific information */
662 armv4_5_common_t *armv4_5 = target->arch_info;
663 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
664 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
665
666 /* put system-speed store half-word into the pipeline */
667 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
668 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
669
670 }
671
672 void arm9tdmi_store_byte_reg(target_t *target, int num)
673 {
674 /* get pointers to arch-specific information */
675 armv4_5_common_t *armv4_5 = target->arch_info;
676 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
677 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
678
679 /* put system-speed store byte into the pipeline */
680 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
681 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
682
683 }
684
685 void arm9tdmi_write_pc(target_t *target, u32 pc)
686 {
687 /* get pointers to arch-specific information */
688 armv4_5_common_t *armv4_5 = target->arch_info;
689 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
690 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
691
692 /* LDMIA r0-15, [r0] at debug speed
693 * register values will start to appear on 4th DCLK
694 */
695 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
696
697 /* fetch NOP, LDM in DECODE stage */
698 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
699 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
700 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
701 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
702 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
703 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
704 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
705 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
706 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
707 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
708 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
709
710 }
711
712 void arm9tdmi_branch_resume(target_t *target)
713 {
714 /* get pointers to arch-specific information */
715 armv4_5_common_t *armv4_5 = target->arch_info;
716 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
717 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
718
719 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
720 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
721
722 }
723
724 void arm9tdmi_branch_resume_thumb(target_t *target)
725 {
726 DEBUG("");
727
728 /* get pointers to arch-specific information */
729 armv4_5_common_t *armv4_5 = target->arch_info;
730 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
731 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
732 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
733
734 /* LDMIA r0-15, [r0] at debug speed
735 * register values will start to appear on 4th DCLK
736 */
737 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
738
739 /* fetch NOP, LDM in DECODE stage */
740 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
741 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
742 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
743 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
744 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
745 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
746 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
747
748 /* Branch and eXchange */
749 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
750
751 embeddedice_read_reg(dbg_stat);
752
753 /* fetch NOP, BX in DECODE stage */
754 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
755
756 embeddedice_read_reg(dbg_stat);
757
758 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
759 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
760
761 /* target is now in Thumb state */
762 embeddedice_read_reg(dbg_stat);
763
764 /* load r0 value, MOV_IM in Decode*/
765 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
766 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
767 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
768 /* fetch NOP, LDR in Execute */
769 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
770 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
771 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
772 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
773 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
774
775 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
776 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
777
778 embeddedice_read_reg(dbg_stat);
779
780 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
781 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
782
783 }
784
785 void arm9tdmi_enable_single_step(target_t *target)
786 {
787 /* get pointers to arch-specific information */
788 armv4_5_common_t *armv4_5 = target->arch_info;
789 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
790 arm9tdmi_common_t *arm9 = arm7_9->arch_info;
791
792 if (arm7_9->has_single_step)
793 {
794 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
795 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
796 }
797 else
798 {
799 arm7_9_enable_eice_step(target);
800 }
801 }
802
803 void arm9tdmi_disable_single_step(target_t *target)
804 {
805 /* get pointers to arch-specific information */
806 armv4_5_common_t *armv4_5 = target->arch_info;
807 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
808 arm9tdmi_common_t *arm9 = arm7_9->arch_info;
809
810 if (arm7_9->has_single_step)
811 {
812 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
813 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
814 }
815 else
816 {
817 arm7_9_disable_eice_step(target);
818 }
819 }
820
821 void arm9tdmi_build_reg_cache(target_t *target)
822 {
823 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
824 /* get pointers to arch-specific information */
825 armv4_5_common_t *armv4_5 = target->arch_info;
826 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
827 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
828
829 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
830 armv4_5->core_cache = (*cache_p);
831
832 /* one extra register (vector catch) */
833 (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
834 arm7_9->eice_cache = (*cache_p)->next;
835
836 if (arm7_9->has_etm)
837 {
838 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
839 arm7_9->etm_cache = (*cache_p)->next->next;
840 }
841 }
842
843 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
844 {
845
846 arm9tdmi_build_reg_cache(target);
847
848 return ERROR_OK;
849
850 }
851
852 int arm9tdmi_quit()
853 {
854
855 return ERROR_OK;
856 }
857
858 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
859 {
860 armv4_5_common_t *armv4_5;
861 arm7_9_common_t *arm7_9;
862
863 arm7_9 = &arm9tdmi->arm7_9_common;
864 armv4_5 = &arm7_9->armv4_5_common;
865
866 /* prepare JTAG information for the new target */
867 arm7_9->jtag_info.chain_pos = chain_pos;
868 arm7_9->jtag_info.scann_size = 5;
869
870 /* register arch-specific functions */
871 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
872 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
873 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
874 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
875 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
876
877 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
878 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
879 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
880
881 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
882 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
883 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
884
885 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
886 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
887 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
888
889 arm7_9->write_pc = arm9tdmi_write_pc;
890 arm7_9->branch_resume = arm9tdmi_branch_resume;
891 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
892
893 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
894 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
895
896 arm7_9->pre_debug_entry = NULL;
897 arm7_9->post_debug_entry = NULL;
898
899 arm7_9->pre_restore_context = NULL;
900 arm7_9->post_restore_context = NULL;
901
902 /* initialize arch-specific breakpoint handling */
903 buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
904 buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
905
906 arm7_9->sw_bkpts_use_wp = 1;
907 arm7_9->sw_bkpts_enabled = 0;
908 arm7_9->dbgreq_adjust_pc = 3;
909 arm7_9->arch_info = arm9tdmi;
910
911 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
912 arm9tdmi->arch_info = NULL;
913
914 if (variant)
915 {
916 arm9tdmi->variant = strdup(variant);
917 }
918 else
919 {
920 arm9tdmi->variant = strdup("");
921 }
922
923 arm7_9_init_arch_info(target, arm7_9);
924
925 /* override use of DBGRQ, this is safe on ARM9TDMI */
926 arm7_9->use_dbgrq = 1;
927
928 /* all ARM9s have the vector catch register */
929 arm7_9->has_vector_catch = 1;
930
931 return ERROR_OK;
932 }
933
934 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
935 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
936 {
937 int chain_pos;
938 char *variant = NULL;
939 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
940
941 if (argc < 4)
942 {
943 ERROR("'target arm9tdmi' requires at least one additional argument");
944 exit(-1);
945 }
946
947 chain_pos = strtoul(args[3], NULL, 0);
948
949 if (argc >= 5)
950 variant = args[4];
951
952 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
953
954 return ERROR_OK;
955 }
956
957 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
958 {
959 int retval;
960
961 retval = arm7_9_register_commands(cmd_ctx);
962
963 return ERROR_OK;
964
965 }
966
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