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3b06b0e48d50155fca4588e86a8eef7ecf062b28
[openocd.git] / src / target / arm9tdmi.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm9tdmi.h"
25
26 #include "arm7_9_common.h"
27 #include "register.h"
28 #include "target.h"
29 #include "armv4_5.h"
30 #include "embeddedice.h"
31 #include "etm.h"
32 #include "etb.h"
33 #include "log.h"
34 #include "jtag.h"
35 #include "arm_jtag.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39
40 #if 0
41 #define _DEBUG_INSTRUCTION_EXECUTION_
42 #endif
43
44 /* cli handling */
45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm9tdmi_quit();
52
53 target_type_t arm9tdmi_target =
54 {
55 .name = "arm9tdmi",
56
57 .poll = arm7_9_poll,
58 .arch_state = armv4_5_arch_state,
59
60 .halt = arm7_9_halt,
61 .resume = arm7_9_resume,
62 .step = arm7_9_step,
63
64 .assert_reset = arm7_9_assert_reset,
65 .deassert_reset = arm7_9_deassert_reset,
66 .soft_reset_halt = arm7_9_soft_reset_halt,
67 .prepare_reset_halt = arm7_9_prepare_reset_halt,
68
69 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
70
71 .read_memory = arm7_9_read_memory,
72 .write_memory = arm7_9_write_memory,
73 .bulk_write_memory = arm7_9_bulk_write_memory,
74
75 .run_algorithm = armv4_5_run_algorithm,
76
77 .add_breakpoint = arm7_9_add_breakpoint,
78 .remove_breakpoint = arm7_9_remove_breakpoint,
79 .add_watchpoint = arm7_9_add_watchpoint,
80 .remove_watchpoint = arm7_9_remove_watchpoint,
81
82 .register_commands = arm9tdmi_register_commands,
83 .target_command = arm9tdmi_target_command,
84 .init_target = arm9tdmi_init_target,
85 .quit = arm9tdmi_quit
86 };
87
88 arm9tdmi_vector_t arm9tdmi_vectors[] =
89 {
90 {"reset", ARM9TDMI_RESET_VECTOR},
91 {"undef", ARM9TDMI_UNDEF_VECTOR},
92 {"swi", ARM9TDMI_SWI_VECTOR},
93 {"pabt", ARM9TDMI_PABT_VECTOR},
94 {"dabt", ARM9TDMI_DABT_VECTOR},
95 {"reserved", ARM9TDMI_RESERVED_VECTOR},
96 {"irq", ARM9TDMI_IRQ_VECTOR},
97 {"fiq", ARM9TDMI_FIQ_VECTOR},
98 {0, 0},
99 };
100
101 int arm9tdmi_jtag_error_handler(u8 *in_value, void *priv)
102 {
103 char *caller = priv;
104
105 DEBUG("caller: %s", caller);
106
107 return ERROR_JTAG_QUEUE_FAILED;
108 }
109
110 int arm9tdmi_examine_debug_reason(target_t *target)
111 {
112 /* get pointers to arch-specific information */
113 armv4_5_common_t *armv4_5 = target->arch_info;
114 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
115
116 /* only check the debug reason if we don't know it already */
117 if ((target->debug_reason != DBG_REASON_DBGRQ)
118 && (target->debug_reason != DBG_REASON_SINGLESTEP))
119 {
120 scan_field_t fields[3];
121 u8 databus[4];
122 u8 instructionbus[4];
123 u8 debug_reason;
124
125 jtag_add_end_state(TAP_PD);
126
127 fields[0].device = arm7_9->jtag_info.chain_pos;
128 fields[0].num_bits = 32;
129 fields[0].out_value = NULL;
130 fields[0].out_mask = NULL;
131 fields[0].in_value = databus;
132 fields[0].in_check_value = NULL;
133 fields[0].in_check_mask = NULL;
134 fields[0].in_handler = NULL;
135 fields[0].in_handler_priv = NULL;
136
137 fields[1].device = arm7_9->jtag_info.chain_pos;
138 fields[1].num_bits = 3;
139 fields[1].out_value = NULL;
140 fields[1].out_mask = NULL;
141 fields[1].in_value = &debug_reason;
142 fields[1].in_check_value = NULL;
143 fields[1].in_check_mask = NULL;
144 fields[1].in_handler = NULL;
145 fields[1].in_handler_priv = NULL;
146
147 fields[2].device = arm7_9->jtag_info.chain_pos;
148 fields[2].num_bits = 32;
149 fields[2].out_value = NULL;
150 fields[2].out_mask = NULL;
151 fields[2].in_value = instructionbus;
152 fields[2].in_check_value = NULL;
153 fields[2].in_check_mask = NULL;
154 fields[2].in_handler = NULL;
155 fields[2].in_handler_priv = NULL;
156
157 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
158 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
159
160 jtag_add_dr_scan(3, fields, TAP_PD, NULL);
161 jtag_execute_queue();
162
163 fields[0].in_value = NULL;
164 fields[0].out_value = databus;
165 fields[1].in_value = NULL;
166 fields[1].out_value = &debug_reason;
167 fields[2].in_value = NULL;
168 fields[2].out_value = instructionbus;
169
170 jtag_add_dr_scan(3, fields, TAP_PD, NULL);
171
172 if (debug_reason & 0x4)
173 if (debug_reason & 0x2)
174 target->debug_reason = DBG_REASON_WPTANDBKPT;
175 else
176 target->debug_reason = DBG_REASON_WATCHPOINT;
177 else
178 target->debug_reason = DBG_REASON_BREAKPOINT;
179 }
180
181 return ERROR_OK;
182 }
183
184 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
185 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
186 {
187 scan_field_t fields[3];
188 u8 out_buf[4];
189 u8 instr_buf[4];
190 u8 sysspeed_buf = 0x0;
191
192 /* prepare buffer */
193 buf_set_u32(out_buf, 0, 32, out);
194
195 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
196
197 if (sysspeed)
198 buf_set_u32(&sysspeed_buf, 2, 1, 1);
199
200 jtag_add_end_state(TAP_PD);
201 arm_jtag_scann(jtag_info, 0x1);
202
203 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
204
205 fields[0].device = jtag_info->chain_pos;
206 fields[0].num_bits = 32;
207 fields[0].out_value = out_buf;
208 fields[0].out_mask = NULL;
209 fields[0].in_value = NULL;
210 if (in)
211 {
212 fields[0].in_handler = arm_jtag_buf_to_u32;
213 fields[0].in_handler_priv = in;
214 }
215 else
216 {
217 fields[0].in_handler = NULL;
218 fields[0].in_handler_priv = NULL;
219 }
220 fields[0].in_check_value = NULL;
221 fields[0].in_check_mask = NULL;
222
223 fields[1].device = jtag_info->chain_pos;
224 fields[1].num_bits = 3;
225 fields[1].out_value = &sysspeed_buf;
226 fields[1].out_mask = NULL;
227 fields[1].in_value = NULL;
228 fields[1].in_check_value = NULL;
229 fields[1].in_check_mask = NULL;
230 fields[1].in_handler = NULL;
231 fields[1].in_handler_priv = NULL;
232
233 fields[2].device = jtag_info->chain_pos;
234 fields[2].num_bits = 32;
235 fields[2].out_value = instr_buf;
236 fields[2].out_mask = NULL;
237 fields[2].in_value = NULL;
238 fields[2].in_check_value = NULL;
239 fields[2].in_check_mask = NULL;
240 fields[2].in_handler = NULL;
241 fields[2].in_handler_priv = NULL;
242
243 jtag_add_dr_scan(3, fields, -1, NULL);
244
245 jtag_add_runtest(0, -1);
246
247 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
248 {
249 jtag_execute_queue();
250
251 if (in)
252 {
253 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
254 }
255 else
256 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
257 }
258 #endif
259
260 return ERROR_OK;
261 }
262
263 /* just read data (instruction and data-out = don't care) */
264 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
265 {
266 scan_field_t fields[3];
267
268 jtag_add_end_state(TAP_PD);
269 arm_jtag_scann(jtag_info, 0x1);
270
271 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
272
273 fields[0].device = jtag_info->chain_pos;
274 fields[0].num_bits = 32;
275 fields[0].out_value = NULL;
276 fields[0].out_mask = NULL;
277 fields[0].in_value = NULL;
278 fields[0].in_handler = arm_jtag_buf_to_u32;
279 fields[0].in_handler_priv = in;
280 fields[0].in_check_value = NULL;
281 fields[0].in_check_mask = NULL;
282
283 fields[1].device = jtag_info->chain_pos;
284 fields[1].num_bits = 3;
285 fields[1].out_value = NULL;
286 fields[1].out_mask = NULL;
287 fields[1].in_value = NULL;
288 fields[1].in_handler = NULL;
289 fields[1].in_handler_priv = NULL;
290 fields[1].in_check_value = NULL;
291 fields[1].in_check_mask = NULL;
292
293 fields[2].device = jtag_info->chain_pos;
294 fields[2].num_bits = 32;
295 fields[2].out_value = NULL;
296 fields[2].out_mask = NULL;
297 fields[2].in_value = NULL;
298 fields[2].in_check_value = NULL;
299 fields[2].in_check_mask = NULL;
300 fields[2].in_handler = NULL;
301 fields[2].in_handler_priv = NULL;
302
303 jtag_add_dr_scan(3, fields, -1, NULL);
304
305 jtag_add_runtest(0, -1);
306
307 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
308 {
309 jtag_execute_queue();
310
311 if (in)
312 {
313 DEBUG("in: 0x%8.8x", *in);
314 }
315 else
316 {
317 ERROR("BUG: called with in == NULL");
318 }
319 }
320 #endif
321
322 return ERROR_OK;
323 }
324
325 /* clock the target, and read the databus
326 * the *in pointer points to a buffer where elements of 'size' bytes
327 * are stored in big (be==1) or little (be==0) endianness
328 */
329 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
330 {
331 scan_field_t fields[3];
332
333 jtag_add_end_state(TAP_PD);
334 arm_jtag_scann(jtag_info, 0x1);
335
336 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
337
338 fields[0].device = jtag_info->chain_pos;
339 fields[0].num_bits = 32;
340 fields[0].out_value = NULL;
341 fields[0].out_mask = NULL;
342 fields[0].in_value = NULL;
343 switch (size)
344 {
345 case 4:
346 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
347 break;
348 case 2:
349 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
350 break;
351 case 1:
352 fields[0].in_handler = arm_jtag_buf_to_8;
353 break;
354 }
355 fields[0].in_handler_priv = in;
356 fields[0].in_check_value = NULL;
357 fields[0].in_check_mask = NULL;
358
359 fields[1].device = jtag_info->chain_pos;
360 fields[1].num_bits = 3;
361 fields[1].out_value = NULL;
362 fields[1].out_mask = NULL;
363 fields[1].in_value = NULL;
364 fields[1].in_handler = NULL;
365 fields[1].in_handler_priv = NULL;
366 fields[1].in_check_value = NULL;
367 fields[1].in_check_mask = NULL;
368
369 fields[2].device = jtag_info->chain_pos;
370 fields[2].num_bits = 32;
371 fields[2].out_value = NULL;
372 fields[2].out_mask = NULL;
373 fields[2].in_value = NULL;
374 fields[2].in_check_value = NULL;
375 fields[2].in_check_mask = NULL;
376 fields[2].in_handler = NULL;
377 fields[2].in_handler_priv = NULL;
378
379 jtag_add_dr_scan(3, fields, -1, NULL);
380
381 jtag_add_runtest(0, -1);
382
383 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
384 {
385 jtag_execute_queue();
386
387 if (in)
388 {
389 DEBUG("in: 0x%8.8x", *in);
390 }
391 else
392 {
393 ERROR("BUG: called with in == NULL");
394 }
395 }
396 #endif
397
398 return ERROR_OK;
399 }
400
401 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
402 {
403 /* get pointers to arch-specific information */
404 armv4_5_common_t *armv4_5 = target->arch_info;
405 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
406 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
407
408 /* save r0 before using it and put system in ARM state
409 * to allow common handling of ARM and THUMB debugging */
410
411 /* fetch STR r0, [r0] */
412 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
413 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
414 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
415 /* STR r0, [r0] in Memory */
416 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
417
418 /* MOV r0, r15 fetched, STR in Decode */
419 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
420 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
421 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
422 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
423 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
424 /* nothing fetched, STR r0, [r0] in Memory */
425 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
426
427 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
428 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
429 /* LDR in Decode */
430 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
431 /* LDR in Execute */
432 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
433 /* LDR in Memory (to account for interlock) */
434 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
435
436 /* fetch BX */
437 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
438 /* NOP fetched, BX in Decode, MOV in Execute */
439 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
440 /* NOP fetched, BX in Execute (1) */
441 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
442
443 jtag_execute_queue();
444
445 /* fix program counter:
446 * MOV r0, r15 was the 5th instruction (+8)
447 * reading PC in Thumb state gives address of instruction + 4
448 */
449 *pc -= 0xc;
450 }
451
452 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
453 {
454 int i;
455 /* get pointers to arch-specific information */
456 armv4_5_common_t *armv4_5 = target->arch_info;
457 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
458 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
459
460 /* STMIA r0-15, [r0] at debug speed
461 * register values will start to appear on 4th DCLK
462 */
463 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
464
465 /* fetch NOP, STM in DECODE stage */
466 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
467 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
468 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
469
470 for (i = 0; i <= 15; i++)
471 {
472 if (mask & (1 << i))
473 /* nothing fetched, STM in MEMORY (i'th cycle) */
474 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
475 }
476
477 }
478
479 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
480 {
481 int i;
482 /* get pointers to arch-specific information */
483 armv4_5_common_t *armv4_5 = target->arch_info;
484 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
485 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
486 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
487 u32 *buf_u32 = buffer;
488 u16 *buf_u16 = buffer;
489 u8 *buf_u8 = buffer;
490
491 /* STMIA r0-15, [r0] at debug speed
492 * register values will start to appear on 4th DCLK
493 */
494 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
495
496 /* fetch NOP, STM in DECODE stage */
497 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
498 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
499 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
500
501 for (i = 0; i <= 15; i++)
502 {
503 if (mask & (1 << i))
504 /* nothing fetched, STM in MEMORY (i'th cycle) */
505 switch (size)
506 {
507 case 4:
508 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
509 break;
510 case 2:
511 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
512 break;
513 case 1:
514 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
515 break;
516 }
517 }
518
519 }
520
521 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
522 {
523 /* get pointers to arch-specific information */
524 armv4_5_common_t *armv4_5 = target->arch_info;
525 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
526 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
527
528 /* MRS r0, cpsr */
529 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
530 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
531 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
532 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
534
535 /* STR r0, [r15] */
536 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
537 /* fetch NOP, STR in DECODE stage */
538 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
539 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
540 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
541 /* nothing fetched, STR in MEMORY */
542 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
543
544 }
545
546 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
547 {
548 /* get pointers to arch-specific information */
549 armv4_5_common_t *armv4_5 = target->arch_info;
550 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
551 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
552
553 DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
554
555 /* MSR1 fetched */
556 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
557 /* MSR2 fetched, MSR1 in DECODE */
558 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
559 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
560 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
561 /* nothing fetched, MSR1 in EXECUTE (2) */
562 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
563 /* nothing fetched, MSR1 in EXECUTE (3) */
564 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
565 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
566 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
567 /* nothing fetched, MSR2 in EXECUTE (2) */
568 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
569 /* nothing fetched, MSR2 in EXECUTE (3) */
570 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
571 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
572 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
573 /* nothing fetched, MSR3 in EXECUTE (2) */
574 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
575 /* nothing fetched, MSR3 in EXECUTE (3) */
576 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
577 /* NOP fetched, MSR4 in EXECUTE (1) */
578 /* last MSR writes flags, which takes only one cycle */
579 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
580 }
581
582 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
583 {
584 /* get pointers to arch-specific information */
585 armv4_5_common_t *armv4_5 = target->arch_info;
586 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
587 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
588
589 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
590
591 /* MSR fetched */
592 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
593 /* NOP fetched, MSR in DECODE */
594 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
595 /* NOP fetched, MSR in EXECUTE (1) */
596 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
597
598 /* rot == 4 writes flags, which takes only one cycle */
599 if (rot != 4)
600 {
601 /* nothing fetched, MSR in EXECUTE (2) */
602 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
603 /* nothing fetched, MSR in EXECUTE (3) */
604 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
605 }
606 }
607
608 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
609 {
610 int i;
611 /* get pointers to arch-specific information */
612 armv4_5_common_t *armv4_5 = target->arch_info;
613 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
614 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
615
616 /* LDMIA r0-15, [r0] at debug speed
617 * register values will start to appear on 4th DCLK
618 */
619 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
620
621 /* fetch NOP, LDM in DECODE stage */
622 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
623 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
624 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
625
626 for (i = 0; i <= 15; i++)
627 {
628 if (mask & (1 << i))
629 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
630 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
631 }
632 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
633
634 }
635
636 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
637 {
638 /* get pointers to arch-specific information */
639 armv4_5_common_t *armv4_5 = target->arch_info;
640 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
641 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
642
643 /* put system-speed load-multiple into the pipeline */
644 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
645 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
646
647 }
648
649 void arm9tdmi_load_hword_reg(target_t *target, int num)
650 {
651 /* get pointers to arch-specific information */
652 armv4_5_common_t *armv4_5 = target->arch_info;
653 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
654 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
655
656 /* put system-speed load half-word into the pipeline */
657 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
658 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
659 }
660
661 void arm9tdmi_load_byte_reg(target_t *target, int num)
662 {
663 /* get pointers to arch-specific information */
664 armv4_5_common_t *armv4_5 = target->arch_info;
665 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
666 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
667
668 /* put system-speed load byte into the pipeline */
669 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
670 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
671
672 }
673
674 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
675 {
676 /* get pointers to arch-specific information */
677 armv4_5_common_t *armv4_5 = target->arch_info;
678 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
679 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
680
681 /* put system-speed store-multiple into the pipeline */
682 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
683 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
684
685 }
686
687 void arm9tdmi_store_hword_reg(target_t *target, int num)
688 {
689 /* get pointers to arch-specific information */
690 armv4_5_common_t *armv4_5 = target->arch_info;
691 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
692 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
693
694 /* put system-speed store half-word into the pipeline */
695 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
696 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
697
698 }
699
700 void arm9tdmi_store_byte_reg(target_t *target, int num)
701 {
702 /* get pointers to arch-specific information */
703 armv4_5_common_t *armv4_5 = target->arch_info;
704 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
705 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
706
707 /* put system-speed store byte into the pipeline */
708 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
709 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
710
711 }
712
713 void arm9tdmi_write_pc(target_t *target, u32 pc)
714 {
715 /* get pointers to arch-specific information */
716 armv4_5_common_t *armv4_5 = target->arch_info;
717 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
718 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
719
720 /* LDMIA r0-15, [r0] at debug speed
721 * register values will start to appear on 4th DCLK
722 */
723 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
724
725 /* fetch NOP, LDM in DECODE stage */
726 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
727 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
728 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
729 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
730 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
731 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
732 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
733 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
734 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
735 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
736 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
737
738 }
739
740 void arm9tdmi_branch_resume(target_t *target)
741 {
742 /* get pointers to arch-specific information */
743 armv4_5_common_t *armv4_5 = target->arch_info;
744 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
745 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
746
747 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
748 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
749
750 }
751
752 void arm9tdmi_branch_resume_thumb(target_t *target)
753 {
754 DEBUG("-");
755
756 /* get pointers to arch-specific information */
757 armv4_5_common_t *armv4_5 = target->arch_info;
758 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
759 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
760 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
761
762 /* LDMIA r0-15, [r0] at debug speed
763 * register values will start to appear on 4th DCLK
764 */
765 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
766
767 /* fetch NOP, LDM in DECODE stage */
768 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
769 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
771 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
772 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
773 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
774 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
775
776 /* Branch and eXchange */
777 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
778
779 embeddedice_read_reg(dbg_stat);
780
781 /* fetch NOP, BX in DECODE stage */
782 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
783
784 embeddedice_read_reg(dbg_stat);
785
786 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
787 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
788
789 /* target is now in Thumb state */
790 embeddedice_read_reg(dbg_stat);
791
792 /* load r0 value, MOV_IM in Decode*/
793 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
794 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
795 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
796 /* fetch NOP, LDR in Execute */
797 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
798 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
799 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
800 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
801 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
802
803 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
804 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
805
806 embeddedice_read_reg(dbg_stat);
807
808 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
809 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
810
811 }
812
813 void arm9tdmi_enable_single_step(target_t *target)
814 {
815 /* get pointers to arch-specific information */
816 armv4_5_common_t *armv4_5 = target->arch_info;
817 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
818
819 if (arm7_9->has_single_step)
820 {
821 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
822 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
823 }
824 else
825 {
826 arm7_9_enable_eice_step(target);
827 }
828 }
829
830 void arm9tdmi_disable_single_step(target_t *target)
831 {
832 /* get pointers to arch-specific information */
833 armv4_5_common_t *armv4_5 = target->arch_info;
834 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
835
836 if (arm7_9->has_single_step)
837 {
838 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
839 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
840 }
841 else
842 {
843 arm7_9_disable_eice_step(target);
844 }
845 }
846
847 void arm9tdmi_build_reg_cache(target_t *target)
848 {
849 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
850 /* get pointers to arch-specific information */
851 armv4_5_common_t *armv4_5 = target->arch_info;
852 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
853 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
854
855 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
856 armv4_5->core_cache = (*cache_p);
857
858 /* one extra register (vector catch) */
859 (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
860 arm7_9->eice_cache = (*cache_p)->next;
861
862 if (arm7_9->etm_ctx)
863 {
864 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
865 arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
866 }
867 }
868
869 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
870 {
871
872 arm9tdmi_build_reg_cache(target);
873
874 return ERROR_OK;
875
876 }
877
878 int arm9tdmi_quit()
879 {
880
881 return ERROR_OK;
882 }
883
884 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
885 {
886 armv4_5_common_t *armv4_5;
887 arm7_9_common_t *arm7_9;
888
889 arm7_9 = &arm9tdmi->arm7_9_common;
890 armv4_5 = &arm7_9->armv4_5_common;
891
892 /* prepare JTAG information for the new target */
893 arm7_9->jtag_info.chain_pos = chain_pos;
894 arm7_9->jtag_info.scann_size = 5;
895
896 /* register arch-specific functions */
897 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
898 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
899 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
900 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
901 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
902
903 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
904 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
905 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
906
907 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
908 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
909 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
910
911 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
912 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
913 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
914
915 arm7_9->write_pc = arm9tdmi_write_pc;
916 arm7_9->branch_resume = arm9tdmi_branch_resume;
917 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
918
919 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
920 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
921
922 arm7_9->pre_debug_entry = NULL;
923 arm7_9->post_debug_entry = NULL;
924
925 arm7_9->pre_restore_context = NULL;
926 arm7_9->post_restore_context = NULL;
927
928 /* initialize arch-specific breakpoint handling */
929 arm7_9->arm_bkpt = 0xdeeedeee;
930 arm7_9->thumb_bkpt = 0xdeee;
931
932 arm7_9->sw_bkpts_use_wp = 1;
933 arm7_9->sw_bkpts_enabled = 0;
934 arm7_9->dbgreq_adjust_pc = 3;
935 arm7_9->arch_info = arm9tdmi;
936
937 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
938 arm9tdmi->arch_info = NULL;
939
940 if (variant)
941 {
942 arm9tdmi->variant = strdup(variant);
943 }
944 else
945 {
946 arm9tdmi->variant = strdup("");
947 }
948
949 arm7_9_init_arch_info(target, arm7_9);
950
951 /* override use of DBGRQ, this is safe on ARM9TDMI */
952 arm7_9->use_dbgrq = 1;
953
954 /* all ARM9s have the vector catch register */
955 arm7_9->has_vector_catch = 1;
956
957 return ERROR_OK;
958 }
959
960 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
961 {
962 armv4_5_common_t *armv4_5 = target->arch_info;
963 arm7_9_common_t *arm7_9;
964 arm9tdmi_common_t *arm9tdmi;
965
966 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
967 {
968 return -1;
969 }
970
971 arm7_9 = armv4_5->arch_info;
972 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
973 {
974 return -1;
975 }
976
977 arm9tdmi = arm7_9->arch_info;
978 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
979 {
980 return -1;
981 }
982
983 *armv4_5_p = armv4_5;
984 *arm7_9_p = arm7_9;
985 *arm9tdmi_p = arm9tdmi;
986
987 return ERROR_OK;
988 }
989
990
991 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
992 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
993 {
994 int chain_pos;
995 char *variant = NULL;
996 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
997
998 if (argc < 4)
999 {
1000 ERROR("'target arm9tdmi' requires at least one additional argument");
1001 exit(-1);
1002 }
1003
1004 chain_pos = strtoul(args[3], NULL, 0);
1005
1006 if (argc >= 5)
1007 variant = args[4];
1008
1009 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
1010
1011 return ERROR_OK;
1012 }
1013
1014 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1015 {
1016 int retval;
1017
1018 command_t *arm9tdmi_cmd;
1019
1020
1021 retval = arm7_9_register_commands(cmd_ctx);
1022
1023 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1024
1025 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1026
1027
1028 return ERROR_OK;
1029
1030 }
1031
1032 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1033 {
1034 target_t *target = get_current_target(cmd_ctx);
1035 armv4_5_common_t *armv4_5;
1036 arm7_9_common_t *arm7_9;
1037 arm9tdmi_common_t *arm9tdmi;
1038 reg_t *vector_catch;
1039 u32 vector_catch_value;
1040 int i, j;
1041
1042 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1043 {
1044 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1045 return ERROR_OK;
1046 }
1047
1048 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1049
1050 /* read the vector catch register if necessary */
1051 if (!vector_catch->valid)
1052 embeddedice_read_reg(vector_catch);
1053
1054 /* get the current setting */
1055 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1056
1057 if (argc > 0)
1058 {
1059 vector_catch_value = 0x0;
1060 if (strcmp(args[0], "all") == 0)
1061 {
1062 vector_catch_value = 0xdf;
1063 }
1064 else if (strcmp(args[0], "none") == 0)
1065 {
1066 /* do nothing */
1067 }
1068 else
1069 {
1070 for (i = 0; i < argc; i++)
1071 {
1072 /* go through list of vectors */
1073 for(j = 0; arm9tdmi_vectors[j].name; j++)
1074 {
1075 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1076 {
1077 vector_catch_value |= arm9tdmi_vectors[j].value;
1078 break;
1079 }
1080 }
1081
1082 /* complain if vector wasn't found */
1083 if (!arm9tdmi_vectors[j].name)
1084 {
1085 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1086
1087 /* reread current setting */
1088 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1089
1090 break;
1091 }
1092 }
1093 }
1094
1095 /* store new settings */
1096 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1097 embeddedice_store_reg(vector_catch);
1098 }
1099
1100 /* output current settings (skip RESERVED vector) */
1101 for (i = 0; i < 8; i++)
1102 {
1103 if (i != 5)
1104 {
1105 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1106 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1107 }
1108 }
1109
1110 return ERROR_OK;
1111 }
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