src/target/arm966e.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm966e.h"
  25
  26 #include "arm7_9_common.h"
  27 #include "register.h"
  28 #include "target.h"
  29 #include "armv4_5.h"
  30 #include "embeddedice.h"
  31 #include "log.h"
  32 #include "jtag.h"
  33 #include "arm_jtag.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37
  38 #if 0
  39 #define _DEBUG_INSTRUCTION_EXECUTION_
  40 #endif
  41
  42 /* cli handling */
  43 int arm966e_register_commands(struct command_context_s *cmd_ctx);
  44
  45 /* forward declarations */
  46 int arm966e_deassert_reset(target_t *target);
  47 int arm966e_assert_reset(target_t *target);
  48 int arm966e_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  49 int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  50 int arm966e_quit(void);
  51
  52 target_type_t arm966e_target =
  53 {
  54         .name = "arm966e",
  55
  56         .poll = arm7_9_poll,
  57         .arch_state = armv4_5_arch_state,
  58
  59         .halt = arm7_9_halt,
  60         .resume = arm7_9_resume,
  61         .step = arm7_9_step,
  62
  63         .assert_reset = arm966e_assert_reset,
  64         .deassert_reset = arm966e_deassert_reset,
  65         .soft_reset_halt = arm7_9_soft_reset_halt,
  66
  67         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  68
  69         .read_memory = arm7_9_read_memory,
  70         .write_memory = arm7_9_write_memory,
  71         .bulk_write_memory = arm7_9_bulk_write_memory,
  72
  73         .add_breakpoint = arm7_9_add_breakpoint,
  74         .remove_breakpoint = arm7_9_remove_breakpoint,
  75         .add_watchpoint = arm7_9_add_watchpoint,
  76         .remove_watchpoint = arm7_9_remove_watchpoint,
  77
  78         .register_commands = arm966e_register_commands,
  79         .target_command = arm966e_target_command,
  80         .init_target = arm966e_init_target,
  81         .quit = arm966e_quit,
  82 };
  83
  84 int arm966e_assert_reset(target_t *target)
  85 {
  86         armv4_5_common_t *armv4_5 = target->arch_info;
  87         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  88         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
  89         arm966e_common_t *arm966e = arm9tdmi->arch_info;
  90         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
  91         int retval;
  92         int trst_asserted_with_srt = 0;
  93
  94         arm966e->monitor_mode_set = 1;
  95
  96         DEBUG("target->state: %s", target_state_strings[target->state]);
  97
  98         if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
  99         {
 100                 /* assert SRST and TRST */
 101                 /* system would get ouf sync if we didn't reset test-logic, too */
 102                 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
 103                 {
 104                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 105                         {
 106                                 WARNING("can't assert srst");
 107                                 return retval;
 108                         }
 109                         else
 110                         {
 111                                 ERROR("unknown error");
 112                                 exit(-1);
 113                         }
 114                 }
 115                 jtag_add_sleep(5000);
 116                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 117                 {
 118                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 119                         {
 120                                 WARNING("srst resets test logic, too");
 121                                 retval = jtag_add_reset(1, 1);
 122                                 trst_asserted_with_srt = 1;
 123                         }
 124                 }
 125         }
 126         else
 127         {
 128                 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
 129                 {
 130                         if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 131                         {
 132                                 WARNING("srst resets test logic, too");
 133                                 retval = jtag_add_reset(1, 1);
 134                                 trst_asserted_with_srt = 1;
 135                         }
 136
 137                         if (retval == ERROR_JTAG_RESET_CANT_SRST)
 138                         {
 139                                 WARNING("can't assert srst");
 140                                 return retval;
 141                         }
 142                         else if (retval != ERROR_OK)
 143                         {
 144                                 ERROR("unknown error");
 145                                 exit(-1);
 146                         }
 147                 }
 148         }
 149
 150         target->state = TARGET_RESET;
 151         jtag_add_sleep(50000);
 152
 153         armv4_5_invalidate_core_regs(target);
 154
 155         if( trst_asserted_with_srt == 0 )
 156         {
 157                 DEBUG("monitor mode needs clearing");
 158
 159                 /* arm9e monitor mode enabled at reset */
 160                 embeddedice_read_reg(dbg_ctrl);
 161                 jtag_execute_queue();
 162
 163                 if(buf_get_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1))
 164                 {
 165                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1, 0);
 166                         embeddedice_store_reg(dbg_ctrl);
 167                         DEBUG("monitor mode disabled");
 168                 }
 169                 arm966e->monitor_mode_set = 0;
 170         }
 171
 172         return ERROR_OK;
 173 }
 174
 175 int arm966e_deassert_reset(target_t *target)
 176 {
 177         armv4_5_common_t *armv4_5 = target->arch_info;
 178         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 179         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 180         arm966e_common_t *arm966e = arm9tdmi->arch_info;
 181         reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 182
 183         arm7_9_deassert_reset( target );
 184
 185         if( arm966e->monitor_mode_set == 1 )
 186         {
 187                 DEBUG("monitor mode needs clearing");
 188
 189                 /* arm9e monitor mode enabled at reset */
 190                 embeddedice_read_reg(dbg_ctrl);
 191                 jtag_execute_queue();
 192
 193                 if(buf_get_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1))
 194                 {
 195                         buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1, 0);
 196                         embeddedice_store_reg(dbg_ctrl);
 197                         arm966e->monitor_mode_set = 0;
 198                         DEBUG("monitor mode disabled");
 199                 }
 200         }
 201
 202         return ERROR_OK;
 203 }
 204
 205 int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 206 {
 207         arm9tdmi_init_target(cmd_ctx, target);
 208
 209         return ERROR_OK;
 210 }
 211
 212 int arm966e_quit(void)
 213 {
 214
 215         return ERROR_OK;
 216 }
 217
 218 int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, int chain_pos, char *variant)
 219 {
 220         arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
 221
 222         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 223
 224         arm9tdmi->arch_info = arm966e;
 225         arm966e->common_magic = ARM966E_COMMON_MAGIC;
 226
 227         arm9tdmi->has_single_step = 0;
 228         arm9tdmi->has_monitor_mode = 1;
 229
 230         return ERROR_OK;
 231 }
 232
 233 int arm966e_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 234 {
 235         int chain_pos;
 236         char *variant = NULL;
 237         arm966e_common_t *arm966e = malloc(sizeof(arm966e_common_t));
 238
 239         if (argc < 4)
 240         {
 241                 ERROR("'target arm966e' requires at least one additional argument");
 242                 exit(-1);
 243         }
 244
 245         chain_pos = strtoul(args[3], NULL, 0);
 246
 247         if (argc >= 5)
 248                 variant = args[4];
 249
 250         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 251
 252         arm966e_init_arch_info(target, arm966e, chain_pos, variant);
 253
 254         return ERROR_OK;
 255 }
 256
 257 int arm966e_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm966e_common_t **arm966e_p)
 258 {
 259         armv4_5_common_t *armv4_5 = target->arch_info;
 260         arm7_9_common_t *arm7_9;
 261         arm9tdmi_common_t *arm9tdmi;
 262         arm966e_common_t *arm966e;
 263
 264         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 265         {
 266                 return -1;
 267         }
 268
 269         arm7_9 = armv4_5->arch_info;
 270         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 271         {
 272                 return -1;
 273         }
 274
 275         arm9tdmi = arm7_9->arch_info;
 276         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 277         {
 278                 return -1;
 279         }
 280
 281         arm966e = arm9tdmi->arch_info;
 282         if (arm966e->common_magic != ARM966E_COMMON_MAGIC)
 283         {
 284                 return -1;
 285         }
 286
 287         *armv4_5_p = armv4_5;
 288         *arm7_9_p = arm7_9;
 289         *arm9tdmi_p = arm9tdmi;
 290         *arm966e_p = arm966e;
 291
 292         return ERROR_OK;
 293 }
 294
 295 int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
 296 {
 297         armv4_5_common_t *armv4_5 = target->arch_info;
 298         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 299         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 300         scan_field_t fields[3];
 301         u8 reg_addr_buf = reg_addr & 0x3f;
 302         u8 nr_w_buf = 0;
 303
 304         jtag_add_end_state(TAP_RTI);
 305         arm_jtag_scann(jtag_info, 0xf);
 306         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 307
 308         fields[0].device = jtag_info->chain_pos;
 309         fields[0].num_bits = 32;
 310         fields[0].out_value = NULL;
 311         fields[0].out_mask = NULL;
 312         fields[0].in_value = NULL;
 313         fields[0].in_check_value = NULL;
 314         fields[0].in_check_mask = NULL;
 315         fields[0].in_handler = NULL;
 316         fields[0].in_handler_priv = NULL;
 317
 318         fields[1].device = jtag_info->chain_pos;
 319         fields[1].num_bits = 6;
 320         fields[1].out_value = &reg_addr_buf;
 321         fields[1].out_mask = NULL;
 322         fields[1].in_value = NULL;
 323         fields[1].in_check_value = NULL;
 324         fields[1].in_check_mask = NULL;
 325         fields[1].in_handler = NULL;
 326         fields[1].in_handler_priv = NULL;
 327
 328         fields[2].device = jtag_info->chain_pos;
 329         fields[2].num_bits = 1;
 330         fields[2].out_value = &nr_w_buf;
 331         fields[2].out_mask = NULL;
 332         fields[2].in_value = NULL;
 333         fields[2].in_check_value = NULL;
 334         fields[2].in_check_mask = NULL;
 335         fields[2].in_handler = NULL;
 336         fields[2].in_handler_priv = NULL;
 337
 338         jtag_add_dr_scan(3, fields, -1);
 339
 340         fields[0].in_value = (u8*)value;
 341
 342         jtag_add_dr_scan(3, fields, -1);
 343
 344         return ERROR_OK;
 345 }
 346
 347 int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
 348 {
 349         armv4_5_common_t *armv4_5 = target->arch_info;
 350         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 351         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 352         scan_field_t fields[3];
 353         u8 reg_addr_buf = reg_addr & 0x3f;
 354         u8 nr_w_buf = 1;
 355
 356         jtag_add_end_state(TAP_RTI);
 357         arm_jtag_scann(jtag_info, 0xf);
 358         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 359
 360         fields[0].device = jtag_info->chain_pos;
 361         fields[0].num_bits = 32;
 362         fields[0].out_value = (u8*)&value;
 363         fields[0].out_mask = NULL;
 364         fields[0].in_value = NULL;
 365         fields[0].in_check_value = NULL;
 366         fields[0].in_check_mask = NULL;
 367         fields[0].in_handler = NULL;
 368         fields[0].in_handler_priv = NULL;
 369
 370         fields[1].device = jtag_info->chain_pos;
 371         fields[1].num_bits = 6;
 372         fields[1].out_value = &reg_addr_buf;
 373         fields[1].out_mask = NULL;
 374         fields[1].in_value = NULL;
 375         fields[1].in_check_value = NULL;
 376         fields[1].in_check_mask = NULL;
 377         fields[1].in_handler = NULL;
 378         fields[1].in_handler_priv = NULL;
 379
 380         fields[2].device = jtag_info->chain_pos;
 381         fields[2].num_bits = 1;
 382         fields[2].out_value = &nr_w_buf;
 383         fields[2].out_mask = NULL;
 384         fields[2].in_value = NULL;
 385         fields[2].in_check_value = NULL;
 386         fields[2].in_check_mask = NULL;
 387         fields[2].in_handler = NULL;
 388         fields[2].in_handler_priv = NULL;
 389
 390         jtag_add_dr_scan(3, fields, -1);
 391
 392         return ERROR_OK;
 393 }
 394
 395 int arm966e_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 396 {
 397         int retval;
 398         target_t *target = get_current_target(cmd_ctx);
 399         armv4_5_common_t *armv4_5;
 400         arm7_9_common_t *arm7_9;
 401         arm9tdmi_common_t *arm9tdmi;
 402         arm966e_common_t *arm966e;
 403         arm_jtag_t *jtag_info;
 404
 405         if (arm966e_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm966e) != ERROR_OK)
 406         {
 407                 command_print(cmd_ctx, "current target isn't an ARM966e target");
 408                 return ERROR_OK;
 409         }
 410
 411         jtag_info = &arm7_9->jtag_info;
 412
 413         if (target->state != TARGET_HALTED)
 414         {
 415                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 416                 return ERROR_OK;
 417         }
 418
 419         /* one or more argument, access a single register (write if second argument is given */
 420         if (argc >= 1)
 421         {
 422                 int address = strtoul(args[0], NULL, 0);
 423
 424                 if (argc == 1)
 425                 {
 426                         u32 value;
 427                         if ((retval = arm966e_read_cp15(target, address, &value)) != ERROR_OK)
 428                         {
 429                                 command_print(cmd_ctx, "couldn't access reg %i", address);
 430                                 return ERROR_OK;
 431                         }
 432                         jtag_execute_queue();
 433
 434                         command_print(cmd_ctx, "%i: %8.8x", address, value);
 435                 }
 436                 else if (argc == 2)
 437                 {
 438                         u32 value = strtoul(args[1], NULL, 0);
 439                         if ((retval = arm966e_write_cp15(target, address, value)) != ERROR_OK)
 440                         {
 441                                 command_print(cmd_ctx, "couldn't access reg %i", address);
 442                                 return ERROR_OK;
 443                         }
 444                         command_print(cmd_ctx, "%i: %8.8x", address, value);
 445                 }
 446         }
 447
 448         return ERROR_OK;
 449 }
 450
 451 int arm966e_register_commands(struct command_context_s *cmd_ctx)
 452 {
 453         int retval;
 454         command_t *arm966e_cmd;
 455
 456         retval = arm7_9_register_commands(cmd_ctx);
 457         arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands");
 458         register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
 459
 460         return ERROR_OK;
 461 }