3112e0fcdf4f8b7b60d22dfc4f860bedef5eda68
[openocd.git] / src / target / arm966e.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm966e.h"
25
26 #include "arm7_9_common.h"
27 #include "register.h"
28 #include "target.h"
29 #include "armv4_5.h"
30 #include "embeddedice.h"
31 #include "log.h"
32 #include "jtag.h"
33 #include "arm_jtag.h"
34
35 #include <stdlib.h>
36 #include <string.h>
37
38 #if 0
39 #define _DEBUG_INSTRUCTION_EXECUTION_
40 #endif
41
42 /* cli handling */
43 int arm966e_register_commands(struct command_context_s *cmd_ctx);
44
45 /* forward declarations */
46 int arm966e_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
47 int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
48 int arm966e_quit(void);
49
50 target_type_t arm966e_target =
51 {
52 .name = "arm966e",
53
54 .poll = arm7_9_poll,
55 .arch_state = armv4_5_arch_state,
56
57 .target_request_data = arm7_9_target_request_data,
58
59 .halt = arm7_9_halt,
60 .resume = arm7_9_resume,
61 .step = arm7_9_step,
62
63 .assert_reset = arm7_9_assert_reset,
64 .deassert_reset = arm7_9_deassert_reset,
65 .soft_reset_halt = arm7_9_soft_reset_halt,
66
67 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
68
69 .read_memory = arm7_9_read_memory,
70 .write_memory = arm7_9_write_memory,
71 .bulk_write_memory = arm7_9_bulk_write_memory,
72 .checksum_memory = arm7_9_checksum_memory,
73
74 .run_algorithm = armv4_5_run_algorithm,
75
76 .add_breakpoint = arm7_9_add_breakpoint,
77 .remove_breakpoint = arm7_9_remove_breakpoint,
78 .add_watchpoint = arm7_9_add_watchpoint,
79 .remove_watchpoint = arm7_9_remove_watchpoint,
80
81 .register_commands = arm966e_register_commands,
82 .target_command = arm966e_target_command,
83 .init_target = arm966e_init_target,
84 .examine = arm9tdmi_examine,
85 .quit = arm966e_quit,
86 };
87
88 int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
89 {
90 arm9tdmi_init_target(cmd_ctx, target);
91
92 return ERROR_OK;
93 }
94
95 int arm966e_quit(void)
96 {
97
98 return ERROR_OK;
99 }
100
101 int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, int chain_pos, char *variant)
102 {
103 arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
104 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
105
106 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
107
108 arm9tdmi->arch_info = arm966e;
109 arm966e->common_magic = ARM966E_COMMON_MAGIC;
110
111 /* The ARM966E-S implements the ARMv5TE architecture which
112 * has the BKPT instruction, so we don't have to use a watchpoint comparator
113 */
114 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
115 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
116
117 arm7_9->sw_bkpts_use_wp = 0;
118 arm7_9->sw_bkpts_enabled = 1;
119
120 return ERROR_OK;
121 }
122
123 int arm966e_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
124 {
125 int chain_pos;
126 char *variant = NULL;
127 arm966e_common_t *arm966e = malloc(sizeof(arm966e_common_t));
128 memset(arm966e, 0, sizeof(*arm966e));
129
130 if (argc < 4)
131 {
132 LOG_ERROR("'target arm966e' requires at least one additional argument");
133 exit(-1);
134 }
135
136 chain_pos = strtoul(args[3], NULL, 0);
137
138 if (argc >= 5)
139 variant = args[4];
140
141 LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
142
143 arm966e_init_arch_info(target, arm966e, chain_pos, variant);
144
145 return ERROR_OK;
146 }
147
148 int arm966e_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm966e_common_t **arm966e_p)
149 {
150 armv4_5_common_t *armv4_5 = target->arch_info;
151 arm7_9_common_t *arm7_9;
152 arm9tdmi_common_t *arm9tdmi;
153 arm966e_common_t *arm966e;
154
155 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
156 {
157 return -1;
158 }
159
160 arm7_9 = armv4_5->arch_info;
161 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
162 {
163 return -1;
164 }
165
166 arm9tdmi = arm7_9->arch_info;
167 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
168 {
169 return -1;
170 }
171
172 arm966e = arm9tdmi->arch_info;
173 if (arm966e->common_magic != ARM966E_COMMON_MAGIC)
174 {
175 return -1;
176 }
177
178 *armv4_5_p = armv4_5;
179 *arm7_9_p = arm7_9;
180 *arm9tdmi_p = arm9tdmi;
181 *arm966e_p = arm966e;
182
183 return ERROR_OK;
184 }
185
186 int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
187 {
188 armv4_5_common_t *armv4_5 = target->arch_info;
189 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
190 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
191 scan_field_t fields[3];
192 u8 reg_addr_buf = reg_addr & 0x3f;
193 u8 nr_w_buf = 0;
194
195 jtag_add_end_state(TAP_RTI);
196 arm_jtag_scann(jtag_info, 0xf);
197 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
198
199 fields[0].device = jtag_info->chain_pos;
200 fields[0].num_bits = 32;
201 fields[0].out_value = NULL;
202 fields[0].out_mask = NULL;
203 fields[0].in_value = NULL;
204 fields[0].in_check_value = NULL;
205 fields[0].in_check_mask = NULL;
206 fields[0].in_handler = NULL;
207 fields[0].in_handler_priv = NULL;
208
209 fields[1].device = jtag_info->chain_pos;
210 fields[1].num_bits = 6;
211 fields[1].out_value = &reg_addr_buf;
212 fields[1].out_mask = NULL;
213 fields[1].in_value = NULL;
214 fields[1].in_check_value = NULL;
215 fields[1].in_check_mask = NULL;
216 fields[1].in_handler = NULL;
217 fields[1].in_handler_priv = NULL;
218
219 fields[2].device = jtag_info->chain_pos;
220 fields[2].num_bits = 1;
221 fields[2].out_value = &nr_w_buf;
222 fields[2].out_mask = NULL;
223 fields[2].in_value = NULL;
224 fields[2].in_check_value = NULL;
225 fields[2].in_check_mask = NULL;
226 fields[2].in_handler = NULL;
227 fields[2].in_handler_priv = NULL;
228
229 jtag_add_dr_scan(3, fields, -1);
230
231 fields[0].in_handler_priv = value;
232 fields[0].in_handler = arm_jtag_buf_to_u32;
233
234 jtag_add_dr_scan(3, fields, -1);
235
236 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
237 jtag_execute_queue();
238 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
239 #endif
240
241 return ERROR_OK;
242 }
243
244 int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
245 {
246 armv4_5_common_t *armv4_5 = target->arch_info;
247 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
248 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
249 scan_field_t fields[3];
250 u8 reg_addr_buf = reg_addr & 0x3f;
251 u8 nr_w_buf = 1;
252 u8 value_buf[4];
253
254 buf_set_u32(value_buf, 0, 32, value);
255
256 jtag_add_end_state(TAP_RTI);
257 arm_jtag_scann(jtag_info, 0xf);
258 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
259
260 fields[0].device = jtag_info->chain_pos;
261 fields[0].num_bits = 32;
262 fields[0].out_value = value_buf;
263 fields[0].out_mask = NULL;
264 fields[0].in_value = NULL;
265 fields[0].in_check_value = NULL;
266 fields[0].in_check_mask = NULL;
267 fields[0].in_handler = NULL;
268 fields[0].in_handler_priv = NULL;
269
270 fields[1].device = jtag_info->chain_pos;
271 fields[1].num_bits = 6;
272 fields[1].out_value = &reg_addr_buf;
273 fields[1].out_mask = NULL;
274 fields[1].in_value = NULL;
275 fields[1].in_check_value = NULL;
276 fields[1].in_check_mask = NULL;
277 fields[1].in_handler = NULL;
278 fields[1].in_handler_priv = NULL;
279
280 fields[2].device = jtag_info->chain_pos;
281 fields[2].num_bits = 1;
282 fields[2].out_value = &nr_w_buf;
283 fields[2].out_mask = NULL;
284 fields[2].in_value = NULL;
285 fields[2].in_check_value = NULL;
286 fields[2].in_check_mask = NULL;
287 fields[2].in_handler = NULL;
288 fields[2].in_handler_priv = NULL;
289
290 jtag_add_dr_scan(3, fields, -1);
291
292 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
293 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
294 #endif
295
296 return ERROR_OK;
297 }
298
299 int arm966e_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
300 {
301 int retval;
302 target_t *target = get_current_target(cmd_ctx);
303 armv4_5_common_t *armv4_5;
304 arm7_9_common_t *arm7_9;
305 arm9tdmi_common_t *arm9tdmi;
306 arm966e_common_t *arm966e;
307 arm_jtag_t *jtag_info;
308
309 if (arm966e_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm966e) != ERROR_OK)
310 {
311 command_print(cmd_ctx, "current target isn't an ARM966e target");
312 return ERROR_OK;
313 }
314
315 jtag_info = &arm7_9->jtag_info;
316
317 if (target->state != TARGET_HALTED)
318 {
319 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
320 return ERROR_OK;
321 }
322
323 /* one or more argument, access a single register (write if second argument is given */
324 if (argc >= 1)
325 {
326 int address = strtoul(args[0], NULL, 0);
327
328 if (argc == 1)
329 {
330 u32 value;
331 if ((retval = arm966e_read_cp15(target, address, &value)) != ERROR_OK)
332 {
333 command_print(cmd_ctx, "couldn't access reg %i", address);
334 return ERROR_OK;
335 }
336 jtag_execute_queue();
337
338 command_print(cmd_ctx, "%i: %8.8x", address, value);
339 }
340 else if (argc == 2)
341 {
342 u32 value = strtoul(args[1], NULL, 0);
343 if ((retval = arm966e_write_cp15(target, address, value)) != ERROR_OK)
344 {
345 command_print(cmd_ctx, "couldn't access reg %i", address);
346 return ERROR_OK;
347 }
348 command_print(cmd_ctx, "%i: %8.8x", address, value);
349 }
350 }
351
352 return ERROR_OK;
353 }
354
355 int arm966e_register_commands(struct command_context_s *cmd_ctx)
356 {
357 int retval;
358 command_t *arm966e_cmd;
359
360 retval = arm9tdmi_register_commands(cmd_ctx);
361 arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands");
362 register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
363
364 return ERROR_OK;
365 }

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