target/arm946e: change prototype of arm946e_verify_pointer()
[openocd.git] / src / target / arm946e.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2010 by Drasko DRASKOVIC *
9 * drasko.draskovic@gmail.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm946e.h"
30 #include "target_type.h"
31 #include "arm_opcodes.h"
32
33 #include "breakpoints.h"
34
35 #if 0
36 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #endif
38
39 #define NB_CACHE_WAYS 4
40
41 #define CP15_CTL 0x02
42 #define CP15_CTL_DCACHE (1<<2)
43 #define CP15_CTL_ICACHE (1<<12)
44
45 /**
46 * flag to give info about cache manipulation during debug :
47 * "0" - cache lines are invalidated "on the fly", for affected addresses.
48 * This is prefered from performance point of view.
49 * "1" - cache is invalidated and switched off on debug_entry, and switched back on on restore.
50 * It is kept off during debugging.
51 */
52 static uint8_t arm946e_preserve_cache;
53
54 int arm946e_post_debug_entry(struct target *target);
55 void arm946e_pre_restore_context(struct target *target);
56 static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value);
57
58 int arm946e_init_arch_info(struct target *target,
59 struct arm946e_common *arm946e,
60 struct jtag_tap *tap)
61 {
62 struct arm7_9_common *arm7_9 = &arm946e->arm7_9_common;
63
64 /* initialize arm7/arm9 specific info (including armv4_5) */
65 arm9tdmi_init_arch_info(target, arm7_9, tap);
66
67 arm946e->common_magic = ARM946E_COMMON_MAGIC;
68
69 /**
70 * The ARM946E-S implements the ARMv5TE architecture which
71 * has the BKPT instruction, so we don't have to use a watchpoint comparator
72 */
73 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
74 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
75
76
77 arm7_9->post_debug_entry = arm946e_post_debug_entry;
78 arm7_9->pre_restore_context = arm946e_pre_restore_context;
79
80 /**
81 * disabling linefills leads to lockups, so keep them enabled for now
82 * this doesn't affect correctness, but might affect timing issues, if
83 * important data is evicted from the cache during the debug session
84 */
85 arm946e_preserve_cache = 0;
86
87 /* override hw single-step capability from ARM9TDMI */
88 /* arm7_9->has_single_step = 1; */
89
90 return ERROR_OK;
91 }
92
93 static int arm946e_target_create(struct target *target, Jim_Interp *interp)
94 {
95 struct arm946e_common *arm946e = calloc(1, sizeof(struct arm946e_common));
96
97 arm946e_init_arch_info(target, arm946e, target->tap);
98
99 return ERROR_OK;
100 }
101
102 static int arm946e_verify_pointer(struct command_invocation *cmd,
103 struct arm946e_common *arm946e)
104 {
105 if (arm946e->common_magic != ARM946E_COMMON_MAGIC) {
106 command_print(cmd->ctx, "target is not an ARM946");
107 return ERROR_TARGET_INVALID;
108 }
109 return ERROR_OK;
110 }
111
112 /*
113 * Update cp15_control_reg, saved on debug_entry.
114 */
115 static void arm946e_update_cp15_caches(struct target *target, uint32_t value)
116 {
117 struct arm946e_common *arm946e = target_to_arm946(target);
118 arm946e->cp15_control_reg = (arm946e->cp15_control_reg & ~(CP15_CTL_DCACHE|CP15_CTL_ICACHE))
119 | (value & (CP15_CTL_DCACHE|CP15_CTL_ICACHE));
120 }
121
122 /*
123 * REVISIT: The "read_cp15" and "write_cp15" commands could hook up
124 * to eventual mrc() and mcr() routines ... the reg_addr values being
125 * constructed (for CP15 only) from Opcode_1, Opcode_2, and CRn values.
126 * See section 7.3 of the ARM946E-S TRM.
127 */
128 static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value)
129 {
130 int retval = ERROR_OK;
131 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
132 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
133 struct scan_field fields[3];
134 uint8_t reg_addr_buf = reg_addr & 0x3f;
135 uint8_t nr_w_buf = 0;
136
137 retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
138 if (retval != ERROR_OK)
139 return retval;
140 retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
141 if (retval != ERROR_OK)
142 return retval;
143
144 fields[0].num_bits = 32;
145 /* REVISIT: table 7-2 shows that bits 31-31 need to be
146 * specified for accessing BIST registers ...
147 */
148 fields[0].out_value = NULL;
149 fields[0].in_value = NULL;
150
151 fields[1].num_bits = 6;
152 fields[1].out_value = &reg_addr_buf;
153 fields[1].in_value = NULL;
154
155 fields[2].num_bits = 1;
156 fields[2].out_value = &nr_w_buf;
157 fields[2].in_value = NULL;
158
159 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
160
161 fields[0].in_value = (uint8_t *)value;
162 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
163
164 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
165
166 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
167 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
168 #endif
169
170 retval = jtag_execute_queue();
171 if (retval != ERROR_OK)
172 return retval;
173
174 return ERROR_OK;
175 }
176
177 int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)
178 {
179 int retval = ERROR_OK;
180 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
181 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
182 struct scan_field fields[3];
183 uint8_t reg_addr_buf = reg_addr & 0x3f;
184 uint8_t nr_w_buf = 1;
185 uint8_t value_buf[4];
186
187 buf_set_u32(value_buf, 0, 32, value);
188
189 retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
190 if (retval != ERROR_OK)
191 return retval;
192 retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
193 if (retval != ERROR_OK)
194 return retval;
195
196 fields[0].num_bits = 32;
197 fields[0].out_value = value_buf;
198 fields[0].in_value = NULL;
199
200 fields[1].num_bits = 6;
201 fields[1].out_value = &reg_addr_buf;
202 fields[1].in_value = NULL;
203
204 fields[2].num_bits = 1;
205 fields[2].out_value = &nr_w_buf;
206 fields[2].in_value = NULL;
207
208 jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
209
210 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
211 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
212 #endif
213
214 retval = jtag_execute_queue();
215 if (retval != ERROR_OK)
216 return retval;
217
218 return ERROR_OK;
219 }
220
221 #define GET_ICACHE_SIZE 6
222 #define GET_DCACHE_SIZE 18
223
224 /*
225 * \param target struct target pointer
226 * \param idsel select GET_ICACHE_SIZE or GET_DCACHE_SIZE
227 * \returns cache size, given in bytes
228 */
229 static uint32_t arm946e_cp15_get_csize(struct target *target, int idsel)
230 {
231 struct arm946e_common *arm946e = target_to_arm946(target);
232 uint32_t csize = arm946e->cp15_cache_info;
233 if (csize == 0) {
234 if (arm946e_read_cp15(target, 0x01, &csize) == ERROR_OK)
235 arm946e->cp15_cache_info = csize;
236 }
237 if (csize & (1<<(idsel-4))) /* cache absent */
238 return 0;
239 csize = (csize >> idsel) & 0x0F;
240 return csize ? 1 << (12 + (csize-3)) : 0;
241 }
242
243 uint32_t arm946e_invalidate_whole_dcache(struct target *target)
244 {
245 uint32_t csize = arm946e_cp15_get_csize(target, GET_DCACHE_SIZE);
246 if (csize == 0)
247 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
248
249 /* One line (index) is 32 bytes (8 words) long, 4-way assoc
250 * ARM DDI 0201D, Section 3.3.5
251 */
252 int nb_idx = (csize / (4*8*NB_CACHE_WAYS)); /* gives nb of lines (indexes) in the cache */
253
254 /* Loop for all segmentde (i.e. ways) */
255 uint32_t seg;
256 for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
257 /* Loop for all indexes */
258 int idx;
259 for (idx = 0; idx < nb_idx; idx++) {
260 /* Form and write cp15 index (segment + line idx) */
261 uint32_t cp15_idx = seg << 30 | idx << 5;
262 int retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
263 if (retval != ERROR_OK) {
264 LOG_DEBUG("ERROR writing index");
265 return retval;
266 }
267
268 /* Read dtag */
269 uint32_t dtag;
270 arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
271
272 /* Check cache line VALID bit */
273 if (!(dtag >> 4 & 0x1))
274 continue;
275
276 /* Clean data cache line */
277 retval = arm946e_write_cp15(target, 0x35, 0x1);
278 if (retval != ERROR_OK) {
279 LOG_DEBUG("ERROR cleaning cache line");
280 return retval;
281 }
282
283 /* Flush data cache line */
284 retval = arm946e_write_cp15(target, 0x1a, 0x1);
285 if (retval != ERROR_OK) {
286 LOG_DEBUG("ERROR flushing cache line");
287 return retval;
288 }
289 }
290 }
291
292 return ERROR_OK;
293 }
294
295 uint32_t arm946e_invalidate_whole_icache(struct target *target)
296 {
297 /* Check cache presence before flushing - avoid undefined behavior */
298 uint32_t csize = arm946e_cp15_get_csize(target, GET_ICACHE_SIZE);
299 if (csize == 0)
300 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
301
302 LOG_DEBUG("FLUSHING I$");
303 /**
304 * Invalidate (flush) I$
305 * mcr 15, 0, r0, cr7, cr5, {0}
306 */
307 int retval = arm946e_write_cp15(target, 0x0f, 0x1);
308 if (retval != ERROR_OK) {
309 LOG_DEBUG("ERROR flushing I$");
310 return retval;
311 }
312
313 return ERROR_OK;
314 }
315
316 int arm946e_post_debug_entry(struct target *target)
317 {
318 uint32_t ctr_reg = 0x0;
319 uint32_t retval = ERROR_OK;
320 struct arm946e_common *arm946e = target_to_arm946(target);
321
322 /* See if CACHES are enabled, and save that info
323 * in the context bits, so that arm946e_pre_restore_context() can use them */
324 arm946e_read_cp15(target, CP15_CTL, (uint32_t *) &ctr_reg);
325
326 /* Save control reg in the context */
327 arm946e->cp15_control_reg = ctr_reg;
328
329 if (arm946e_preserve_cache) {
330 if (ctr_reg & CP15_CTL_DCACHE) {
331 /* Clean and flush D$ */
332 arm946e_invalidate_whole_dcache(target);
333
334 /* Disable D$ */
335 ctr_reg &= ~CP15_CTL_DCACHE;
336 }
337
338 if (ctr_reg & CP15_CTL_ICACHE) {
339 /* Flush I$ */
340 arm946e_invalidate_whole_icache(target);
341
342 /* Disable I$ */
343 ctr_reg &= ~CP15_CTL_ICACHE;
344 }
345
346 /* Write the new configuration */
347 retval = arm946e_write_cp15(target, CP15_CTL, ctr_reg);
348 if (retval != ERROR_OK) {
349 LOG_DEBUG("ERROR disabling cache");
350 return retval;
351 }
352 } /* if preserve_cache */
353
354 return ERROR_OK;
355 }
356
357 void arm946e_pre_restore_context(struct target *target)
358 {
359 uint32_t ctr_reg = 0x0;
360 uint32_t retval;
361
362 if (arm946e_preserve_cache) {
363 struct arm946e_common *arm946e = target_to_arm946(target);
364 /* Get the contents of the CTR reg */
365 arm946e_read_cp15(target, CP15_CTL, (uint32_t *) &ctr_reg);
366
367 /**
368 * Read-modify-write CP15 control
369 * to reenable I/D-cache operation
370 * NOTE: It is not possible to disable cache by CP15.
371 * if arm946e_preserve_cache debugging flag enabled.
372 */
373 ctr_reg |= arm946e->cp15_control_reg & (CP15_CTL_DCACHE|CP15_CTL_ICACHE);
374
375 /* Write the new configuration */
376 retval = arm946e_write_cp15(target, CP15_CTL, ctr_reg);
377 if (retval != ERROR_OK)
378 LOG_DEBUG("ERROR enabling cache");
379 } /* if preserve_cache */
380 }
381
382 uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
383 uint32_t size, uint32_t count)
384 {
385 uint32_t cur_addr = 0x0;
386 uint32_t cp15_idx, set, way, dtag;
387 uint32_t i = 0;
388 int retval;
389
390 for (i = 0; i < count*size; i++) {
391 cur_addr = address + i;
392
393
394 set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */
395
396 for (way = 0; way < NB_CACHE_WAYS; way++) {
397 /**
398 * Find if the affected address is kept in the cache.
399 * Because JTAG Scan Chain 15 offers limited approach,
400 * we have to loop through all cache ways (segments) and
401 * read cache tags, then compare them with with address.
402 */
403
404 /* Form and write cp15 index (segment + line idx) */
405 cp15_idx = way << 30 | set << 5;
406 retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
407 if (retval != ERROR_OK) {
408 LOG_DEBUG("ERROR writing index");
409 return retval;
410 }
411
412 /* Read dtag */
413 arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
414
415 /* Check cache line VALID bit */
416 if (!(dtag >> 4 & 0x1))
417 continue;
418
419 /* If line is valid and corresponds to affected address - invalidate it */
420 if (dtag >> 5 == cur_addr >> 5) {
421 /* Clean data cache line */
422 retval = arm946e_write_cp15(target, 0x35, 0x1);
423 if (retval != ERROR_OK) {
424 LOG_DEBUG("ERROR cleaning cache line");
425 return retval;
426 }
427
428 /* Flush data cache line */
429 retval = arm946e_write_cp15(target, 0x1c, 0x1);
430 if (retval != ERROR_OK) {
431 LOG_DEBUG("ERROR flushing cache line");
432 return retval;
433 }
434
435 break;
436 }
437 } /* loop through all 4 ways */
438 } /* loop through all addresses */
439
440 return ERROR_OK;
441 }
442
443 uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
444 uint32_t size, uint32_t count)
445 {
446 uint32_t cur_addr = 0x0;
447 uint32_t cp15_idx, set, way, itag;
448 uint32_t i = 0;
449 int retval;
450
451 for (i = 0; i < count*size; i++) {
452 cur_addr = address + i;
453
454 set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */
455
456 for (way = 0; way < NB_CACHE_WAYS; way++) {
457 /* Form and write cp15 index (segment + line idx) */
458 cp15_idx = way << 30 | set << 5;
459 retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
460 if (retval != ERROR_OK) {
461 LOG_DEBUG("ERROR writing index");
462 return retval;
463 }
464
465 /* Read itag */
466 arm946e_read_cp15(target, 0x17, (uint32_t *) &itag);
467
468 /* Check cache line VALID bit */
469 if (!(itag >> 4 & 0x1))
470 continue;
471
472 /* If line is valid and corresponds to affected address - invalidate it */
473 if (itag >> 5 == cur_addr >> 5) {
474 /* Flush I$ line */
475 retval = arm946e_write_cp15(target, 0x1d, 0x0);
476 if (retval != ERROR_OK) {
477 LOG_DEBUG("ERROR flushing cache line");
478 return retval;
479 }
480
481 break;
482 }
483 } /* way loop */
484 } /* addr loop */
485
486 return ERROR_OK;
487 }
488
489 /** Writes a buffer, in the specified word size, with current MMU settings. */
490 int arm946e_write_memory(struct target *target, target_addr_t address,
491 uint32_t size, uint32_t count, const uint8_t *buffer)
492 {
493 int retval;
494
495 LOG_DEBUG("-");
496
497 struct arm946e_common *arm946e = target_to_arm946(target);
498 /* Invalidate D$ if it is ON */
499 if (!arm946e_preserve_cache && (arm946e->cp15_control_reg & CP15_CTL_DCACHE))
500 arm946e_invalidate_dcache(target, address, size, count);
501
502 /**
503 * Write memory
504 */
505 retval = arm7_9_write_memory_opt(target, address, size, count, buffer);
506 if (retval != ERROR_OK)
507 return retval;
508
509 /* *
510 * Invalidate I$ if it is ON.
511 *
512 * D$ has been cleaned and flushed before mem write thus forcing it to behave like write-through,
513 * because arm7_9_write_memory() has seen non-valid bit in D$
514 * and wrote data into physical RAM (without touching or allocating the cache line).
515 * From ARM946ES Technical Reference Manual we can see that it uses "allocate on read-miss"
516 * policy for both I$ and D$ (Chapter 3.2 and 3.3)
517 *
518 * Explanation :
519 * "ARM system developer's guide: designing and optimizing system software" by
520 * Andrew N. Sloss, Dominic Symes and Chris Wright,
521 * Chapter 12.3.3 Allocating Policy on a Cache Miss :
522 * A read allocate on cache miss policy allocates a cache line only during a read from main memory.
523 * If the victim cache line contains valid data, then it is written to main memory before the cache line
524 * is filled with new data.
525 * Under this strategy, a write of new data to memory does not update the contents of the cache memory
526 * unless a cache line was allocated on a previous read from main memory.
527 * If the cache line contains valid data, then the write updates the cache and may update the main memory if
528 * the cache write policy is write-through.
529 * If the data is not in the cache, the controller writes to main memory only.
530 */
531 if (!arm946e_preserve_cache && (arm946e->cp15_control_reg & CP15_CTL_ICACHE))
532 arm946e_invalidate_icache(target, address, size, count);
533
534 return ERROR_OK;
535
536 }
537
538 int arm946e_read_memory(struct target *target, target_addr_t address,
539 uint32_t size, uint32_t count, uint8_t *buffer)
540 {
541 int retval;
542
543 LOG_DEBUG("-");
544
545 retval = arm7_9_read_memory(target, address, size, count, buffer);
546 if (retval != ERROR_OK)
547 return retval;
548
549 return ERROR_OK;
550 }
551
552 COMMAND_HANDLER(arm946e_handle_cp15)
553 {
554 /* one or two arguments, access a single register (write if second argument is given) */
555 if (CMD_ARGC < 1 || CMD_ARGC > 2)
556 return ERROR_COMMAND_SYNTAX_ERROR;
557
558 struct target *target = get_current_target(CMD_CTX);
559
560 struct arm946e_common *arm946e = target_to_arm946(target);
561 int retval = arm946e_verify_pointer(CMD, arm946e);
562 if (retval != ERROR_OK)
563 return retval;
564
565 if (target->state != TARGET_HALTED) {
566 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
567 return ERROR_TARGET_NOT_HALTED;
568 }
569
570 uint32_t address;
571 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
572
573 if (CMD_ARGC == 1) {
574 uint32_t value;
575 retval = arm946e_read_cp15(target, address, &value);
576 if (retval != ERROR_OK) {
577 command_print(CMD_CTX, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
578 return retval;
579 }
580 retval = jtag_execute_queue();
581 if (retval != ERROR_OK)
582 return retval;
583
584 /* Return value in hex format */
585 command_print(CMD_CTX, "0x%08" PRIx32, value);
586 } else if (CMD_ARGC == 2) {
587 uint32_t value;
588 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
589
590 retval = arm946e_write_cp15(target, address, value);
591 if (retval != ERROR_OK) {
592 command_print(CMD_CTX, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
593 return retval;
594 }
595 if (address == CP15_CTL)
596 arm946e_update_cp15_caches(target, value);
597 }
598
599 return ERROR_OK;
600 }
601
602 COMMAND_HANDLER(arm946e_handle_idcache)
603 {
604 if (CMD_ARGC > 1)
605 return ERROR_COMMAND_SYNTAX_ERROR;
606
607 int retval;
608 struct target *target = get_current_target(CMD_CTX);
609 struct arm946e_common *arm946e = target_to_arm946(target);
610
611 retval = arm946e_verify_pointer(CMD, arm946e);
612 if (retval != ERROR_OK)
613 return retval;
614
615 if (target->state != TARGET_HALTED) {
616 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
617 return ERROR_TARGET_NOT_HALTED;
618 }
619
620 bool icache = (strcmp(CMD_NAME, "icache") == 0);
621 uint32_t csize = arm946e_cp15_get_csize(target, icache ? GET_ICACHE_SIZE : GET_DCACHE_SIZE) / 1024;
622 if (CMD_ARGC == 0) {
623 bool bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0)
624 && (arm946e->cp15_control_reg & 0x1);
625 if (csize == 0)
626 command_print(CMD_CTX, "%s-cache absent", icache ? "I" : "D");
627 else
628 command_print(CMD_CTX, "%s-cache size: %" PRIu32 "K, %s",
629 icache ? "I" : "D", csize, bena ? "enabled" : "disabled");
630 return ERROR_OK;
631 }
632
633 bool flush = false;
634 bool enable = false;
635 retval = command_parse_bool_arg(CMD_ARGV[0], &enable);
636 if (retval == ERROR_COMMAND_SYNTAX_ERROR) {
637 if (strcmp(CMD_ARGV[0], "flush") == 0) {
638 flush = true;
639 retval = ERROR_OK;
640 } else
641 return retval;
642 }
643
644 /* Do not invalidate or change state, if cache is absent */
645 if (csize == 0) {
646 command_print(CMD_CTX, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
647 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
648 }
649
650 /* NOTE: flushing entire cache will not preserve lock-down cache regions */
651 if (icache) {
652 if ((arm946e->cp15_control_reg & CP15_CTL_ICACHE) && !enable)
653 retval = arm946e_invalidate_whole_icache(target);
654 } else {
655 if ((arm946e->cp15_control_reg & CP15_CTL_DCACHE) && !enable)
656 retval = arm946e_invalidate_whole_dcache(target);
657 }
658
659 if (retval != ERROR_OK || flush)
660 return retval;
661
662 uint32_t value;
663 retval = arm946e_read_cp15(target, CP15_CTL, &value);
664 if (retval != ERROR_OK)
665 return retval;
666
667 uint32_t vnew = value;
668 uint32_t cmask = icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE;
669 if (enable) {
670 if ((value & 0x1) == 0)
671 LOG_WARNING("arm946e: MPU must be enabled for cache to operate");
672 vnew |= cmask;
673 } else
674 vnew &= ~cmask;
675
676 if (vnew == value)
677 return ERROR_OK;
678
679 retval = arm946e_write_cp15(target, CP15_CTL, vnew);
680 if (retval != ERROR_OK)
681 return retval;
682
683 arm946e_update_cp15_caches(target, vnew);
684 return ERROR_OK;
685 }
686
687 static const struct command_registration arm946e_exec_command_handlers[] = {
688 {
689 .name = "cp15",
690 .handler = arm946e_handle_cp15,
691 .mode = COMMAND_EXEC,
692 .usage = "regnum [value]",
693 .help = "read/modify cp15 register",
694 },
695 {
696 .name = "icache",
697 .handler = arm946e_handle_idcache,
698 .mode = COMMAND_EXEC,
699 .usage = "['enable'|'disable'|'flush']",
700 .help = "I-cache info and operations",
701 },
702 {
703 .name = "dcache",
704 .handler = arm946e_handle_idcache,
705 .mode = COMMAND_EXEC,
706 .usage = "['enable'|'disable'|'flush']",
707 .help = "D-cache info and operations",
708 },
709 COMMAND_REGISTRATION_DONE
710 };
711
712 const struct command_registration arm946e_command_handlers[] = {
713 {
714 .chain = arm9tdmi_command_handlers,
715 },
716 {
717 .name = "arm946e",
718 .mode = COMMAND_ANY,
719 .help = "arm946e command group",
720 .usage = "",
721 .chain = arm946e_exec_command_handlers,
722 },
723 COMMAND_REGISTRATION_DONE
724 };
725
726 /** Holds methods for ARM946 targets. */
727 struct target_type arm946e_target = {
728 .name = "arm946e",
729
730 .poll = arm7_9_poll,
731 .arch_state = arm_arch_state,
732
733 .target_request_data = arm7_9_target_request_data,
734
735 .halt = arm7_9_halt,
736 .resume = arm7_9_resume,
737 .step = arm7_9_step,
738
739 .assert_reset = arm7_9_assert_reset,
740 .deassert_reset = arm7_9_deassert_reset,
741 .soft_reset_halt = arm7_9_soft_reset_halt,
742
743 .get_gdb_arch = arm_get_gdb_arch,
744 .get_gdb_reg_list = arm_get_gdb_reg_list,
745
746 /* .read_memory = arm7_9_read_memory, */
747 /* .write_memory = arm7_9_write_memory, */
748 .read_memory = arm946e_read_memory,
749 .write_memory = arm946e_write_memory,
750
751 .checksum_memory = arm_checksum_memory,
752 .blank_check_memory = arm_blank_check_memory,
753
754 .run_algorithm = armv4_5_run_algorithm,
755
756 .add_breakpoint = arm7_9_add_breakpoint,
757 .remove_breakpoint = arm7_9_remove_breakpoint,
758 /* .add_breakpoint = arm946e_add_breakpoint, */
759 /* .remove_breakpoint = arm946e_remove_breakpoint, */
760
761 .add_watchpoint = arm7_9_add_watchpoint,
762 .remove_watchpoint = arm7_9_remove_watchpoint,
763
764 .commands = arm946e_command_handlers,
765 .target_create = arm946e_target_create,
766 .init_target = arm9tdmi_init_target,
767 .examine = arm7_9_examine,
768 .check_reset = arm7_9_check_reset,
769 };