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retire out_mask - not used anywhere
[openocd.git] / src / target / arm926ejs.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm926ejs.h"
25 #include "jtag.h"
26 #include "log.h"
27 #include "time_support.h"
28
29 #include <stdlib.h>
30 #include <string.h>
31
32 #if 0
33 #define _DEBUG_INSTRUCTION_EXECUTION_
34 #endif
35
36 /* cli handling */
37 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43
44 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46
47 /* forward declarations */
48 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
49 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
50 int arm926ejs_quit(void);
51 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
52
53 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
54 static int arm926ejs_mmu(struct target_s *target, int *enabled);
55
56 target_type_t arm926ejs_target =
57 {
58 .name = "arm926ejs",
59
60 .poll = arm7_9_poll,
61 .arch_state = arm926ejs_arch_state,
62
63 .target_request_data = arm7_9_target_request_data,
64
65 .halt = arm7_9_halt,
66 .resume = arm7_9_resume,
67 .step = arm7_9_step,
68
69 .assert_reset = arm7_9_assert_reset,
70 .deassert_reset = arm7_9_deassert_reset,
71 .soft_reset_halt = arm926ejs_soft_reset_halt,
72
73 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
74
75 .read_memory = arm7_9_read_memory,
76 .write_memory = arm926ejs_write_memory,
77 .bulk_write_memory = arm7_9_bulk_write_memory,
78 .checksum_memory = arm7_9_checksum_memory,
79 .blank_check_memory = arm7_9_blank_check_memory,
80
81 .run_algorithm = armv4_5_run_algorithm,
82
83 .add_breakpoint = arm7_9_add_breakpoint,
84 .remove_breakpoint = arm7_9_remove_breakpoint,
85 .add_watchpoint = arm7_9_add_watchpoint,
86 .remove_watchpoint = arm7_9_remove_watchpoint,
87
88 .register_commands = arm926ejs_register_commands,
89 .target_create = arm926ejs_target_create,
90 .init_target = arm926ejs_init_target,
91 .examine = arm9tdmi_examine,
92 .quit = arm926ejs_quit,
93 .virt2phys = arm926ejs_virt2phys,
94 .mmu = arm926ejs_mmu
95 };
96
97 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
98 {
99 /* The ARM926EJ-S' instruction register is 4 bits wide */
100 u8 t = *captured & 0xf;
101 u8 t2 = *field->in_check_value & 0xf;
102 if (t == t2)
103 {
104 return ERROR_OK;
105 }
106 else if ((t == 0x0f) || (t == 0x00))
107 {
108 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
109 return ERROR_OK;
110 }
111 return ERROR_JTAG_QUEUE_FAILED;;
112 }
113
114 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
115
116 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
117 {
118 int retval = ERROR_OK;
119 armv4_5_common_t *armv4_5 = target->arch_info;
120 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
121 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
122 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
123 scan_field_t fields[4];
124 u8 address_buf[2];
125 u8 nr_w_buf = 0;
126 u8 access = 1;
127
128 buf_set_u32(address_buf, 0, 14, address);
129
130 jtag_add_end_state(TAP_IDLE);
131 if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
132 {
133 return retval;
134 }
135 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
136
137 fields[0].tap = jtag_info->tap;
138 fields[0].num_bits = 32;
139 fields[0].out_value = NULL;
140
141 fields[0].in_value = NULL;
142 fields[0].in_check_value = NULL;
143 fields[0].in_check_mask = NULL;
144 fields[0].in_handler = NULL;
145 fields[0].in_handler_priv = NULL;
146
147 fields[1].tap = jtag_info->tap;
148 fields[1].num_bits = 1;
149 fields[1].out_value = &access;
150
151 fields[1].in_value = &access;
152 fields[1].in_check_value = NULL;
153 fields[1].in_check_mask = NULL;
154 fields[1].in_handler = NULL;
155 fields[1].in_handler_priv = NULL;
156
157 fields[2].tap = jtag_info->tap;
158 fields[2].num_bits = 14;
159 fields[2].out_value = address_buf;
160
161 fields[2].in_value = NULL;
162 fields[2].in_check_value = NULL;
163 fields[2].in_check_mask = NULL;
164 fields[2].in_handler = NULL;
165 fields[2].in_handler_priv = NULL;
166
167 fields[3].tap = jtag_info->tap;
168 fields[3].num_bits = 1;
169 fields[3].out_value = &nr_w_buf;
170
171 fields[3].in_value = NULL;
172 fields[3].in_check_value = NULL;
173 fields[3].in_check_mask = NULL;
174 fields[3].in_handler = NULL;
175 fields[3].in_handler_priv = NULL;
176
177 jtag_add_dr_scan(4, fields, TAP_INVALID);
178
179 fields[0].in_handler_priv = value;
180 fields[0].in_handler = arm_jtag_buf_to_u32; /* deprecated! invoke this from user code! */
181
182 /*TODO: add timeout*/
183 do
184 {
185 /* rescan with NOP, to wait for the access to complete */
186 access = 0;
187 nr_w_buf = 0;
188 jtag_add_dr_scan(4, fields, TAP_INVALID);
189 if((retval = jtag_execute_queue()) != ERROR_OK)
190 {
191 return retval;
192 }
193 } while (buf_get_u32(&access, 0, 1) != 1);
194
195 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
196 LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
197 #endif
198
199 arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
200
201 return ERROR_OK;
202 }
203
204 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
205 {
206 int retval = ERROR_OK;
207 armv4_5_common_t *armv4_5 = target->arch_info;
208 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
209 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
210 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
211 scan_field_t fields[4];
212 u8 value_buf[4];
213 u8 address_buf[2];
214 u8 nr_w_buf = 1;
215 u8 access = 1;
216
217 buf_set_u32(address_buf, 0, 14, address);
218 buf_set_u32(value_buf, 0, 32, value);
219
220 jtag_add_end_state(TAP_IDLE);
221 if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
222 {
223 return retval;
224 }
225 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
226
227 fields[0].tap = jtag_info->tap;
228 fields[0].num_bits = 32;
229 fields[0].out_value = value_buf;
230
231 fields[0].in_value = NULL;
232 fields[0].in_check_value = NULL;
233 fields[0].in_check_mask = NULL;
234 fields[0].in_handler = NULL;
235 fields[0].in_handler_priv = NULL;
236
237 fields[1].tap = jtag_info->tap;
238 fields[1].num_bits = 1;
239 fields[1].out_value = &access;
240
241 fields[1].in_value = &access;
242 fields[1].in_check_value = NULL;
243 fields[1].in_check_mask = NULL;
244 fields[1].in_handler = NULL;
245 fields[1].in_handler_priv = NULL;
246
247 fields[2].tap = jtag_info->tap;
248 fields[2].num_bits = 14;
249 fields[2].out_value = address_buf;
250
251 fields[2].in_value = NULL;
252 fields[2].in_check_value = NULL;
253 fields[2].in_check_mask = NULL;
254 fields[2].in_handler = NULL;
255 fields[2].in_handler_priv = NULL;
256
257 fields[3].tap = jtag_info->tap;
258 fields[3].num_bits = 1;
259 fields[3].out_value = &nr_w_buf;
260
261 fields[3].in_value = NULL;
262 fields[3].in_check_value = NULL;
263 fields[3].in_check_mask = NULL;
264 fields[3].in_handler = NULL;
265 fields[3].in_handler_priv = NULL;
266
267 jtag_add_dr_scan(4, fields, TAP_INVALID);
268 /*TODO: add timeout*/
269 do
270 {
271 /* rescan with NOP, to wait for the access to complete */
272 access = 0;
273 nr_w_buf = 0;
274 jtag_add_dr_scan(4, fields, TAP_INVALID);
275 if((retval = jtag_execute_queue()) != ERROR_OK)
276 {
277 return retval;
278 }
279 } while (buf_get_u32(&access, 0, 1) != 1);
280
281 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
282 LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
283 #endif
284
285 arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
286
287 return ERROR_OK;
288 }
289
290 int arm926ejs_examine_debug_reason(target_t *target)
291 {
292 armv4_5_common_t *armv4_5 = target->arch_info;
293 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
294 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
295 int debug_reason;
296 int retval;
297
298 embeddedice_read_reg(dbg_stat);
299 if ((retval = jtag_execute_queue()) != ERROR_OK)
300 return retval;
301
302 debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
303
304 switch (debug_reason)
305 {
306 case 1:
307 LOG_DEBUG("breakpoint from EICE unit 0");
308 target->debug_reason = DBG_REASON_BREAKPOINT;
309 break;
310 case 2:
311 LOG_DEBUG("breakpoint from EICE unit 1");
312 target->debug_reason = DBG_REASON_BREAKPOINT;
313 break;
314 case 3:
315 LOG_DEBUG("soft breakpoint (BKPT instruction)");
316 target->debug_reason = DBG_REASON_BREAKPOINT;
317 break;
318 case 4:
319 LOG_DEBUG("vector catch breakpoint");
320 target->debug_reason = DBG_REASON_BREAKPOINT;
321 break;
322 case 5:
323 LOG_DEBUG("external breakpoint");
324 target->debug_reason = DBG_REASON_BREAKPOINT;
325 break;
326 case 6:
327 LOG_DEBUG("watchpoint from EICE unit 0");
328 target->debug_reason = DBG_REASON_WATCHPOINT;
329 break;
330 case 7:
331 LOG_DEBUG("watchpoint from EICE unit 1");
332 target->debug_reason = DBG_REASON_WATCHPOINT;
333 break;
334 case 8:
335 LOG_DEBUG("external watchpoint");
336 target->debug_reason = DBG_REASON_WATCHPOINT;
337 break;
338 case 9:
339 LOG_DEBUG("internal debug request");
340 target->debug_reason = DBG_REASON_DBGRQ;
341 break;
342 case 10:
343 LOG_DEBUG("external debug request");
344 target->debug_reason = DBG_REASON_DBGRQ;
345 break;
346 case 11:
347 LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
348 break;
349 case 12:
350 /* FIX!!!! here be dragons!!! We need to fail here so
351 * the target will interpreted as halted but we won't
352 * try to talk to it right now... a resume + halt seems
353 * to sync things up again. Please send an email to
354 * openocd development mailing list if you have hardware
355 * to donate to look into this problem....
356 */
357 LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
358 target->debug_reason = DBG_REASON_DBGRQ;
359 retval = ERROR_TARGET_FAILURE;
360 break;
361 default:
362 LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
363 target->debug_reason = DBG_REASON_DBGRQ;
364 /* if we fail here, we won't talk to the target and it will
365 * be reported to be in the halted state */
366 retval = ERROR_TARGET_FAILURE;
367 break;
368 }
369
370 return retval;
371 }
372
373 u32 arm926ejs_get_ttb(target_t *target)
374 {
375 armv4_5_common_t *armv4_5 = target->arch_info;
376 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
377 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
378 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
379 int retval;
380 u32 ttb = 0x0;
381
382 if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
383 return retval;
384
385 return ttb;
386 }
387
388 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
389 {
390 armv4_5_common_t *armv4_5 = target->arch_info;
391 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
392 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
393 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
394 u32 cp15_control;
395
396 /* read cp15 control register */
397 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
398 jtag_execute_queue();
399
400 if (mmu)
401 {
402 /* invalidate TLB */
403 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
404
405 cp15_control &= ~0x1U;
406 }
407
408 if (d_u_cache)
409 {
410 u32 debug_override;
411 /* read-modify-write CP15 debug override register
412 * to enable "test and clean all" */
413 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
414 debug_override |= 0x80000;
415 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
416
417 /* clean and invalidate DCache */
418 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
419
420 /* write CP15 debug override register
421 * to disable "test and clean all" */
422 debug_override &= ~0x80000;
423 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
424
425 cp15_control &= ~0x4U;
426 }
427
428 if (i_cache)
429 {
430 /* invalidate ICache */
431 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
432
433 cp15_control &= ~0x1000U;
434 }
435
436 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
437 }
438
439 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
440 {
441 armv4_5_common_t *armv4_5 = target->arch_info;
442 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
443 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
444 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
445 u32 cp15_control;
446
447 /* read cp15 control register */
448 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
449 jtag_execute_queue();
450
451 if (mmu)
452 cp15_control |= 0x1U;
453
454 if (d_u_cache)
455 cp15_control |= 0x4U;
456
457 if (i_cache)
458 cp15_control |= 0x1000U;
459
460 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
461 }
462
463 void arm926ejs_post_debug_entry(target_t *target)
464 {
465 armv4_5_common_t *armv4_5 = target->arch_info;
466 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
467 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
468 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
469
470 /* examine cp15 control reg */
471 arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
472 jtag_execute_queue();
473 LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
474
475 if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
476 {
477 u32 cache_type_reg;
478 /* identify caches */
479 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
480 jtag_execute_queue();
481 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
482 }
483
484 arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
485 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
486 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
487
488 /* save i/d fault status and address register */
489 arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
490 arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
491 arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
492
493 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
494 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
495
496 u32 cache_dbg_ctrl;
497
498 /* read-modify-write CP15 cache debug control register
499 * to disable I/D-cache linefills and force WT */
500 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
501 cache_dbg_ctrl |= 0x7;
502 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
503 }
504
505 void arm926ejs_pre_restore_context(target_t *target)
506 {
507 armv4_5_common_t *armv4_5 = target->arch_info;
508 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
509 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
510 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
511
512 /* restore i/d fault status and address register */
513 arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
514 arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
515 arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
516
517 u32 cache_dbg_ctrl;
518
519 /* read-modify-write CP15 cache debug control register
520 * to reenable I/D-cache linefills and disable WT */
521 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
522 cache_dbg_ctrl &= ~0x7;
523 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
524 }
525
526 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
527 {
528 armv4_5_common_t *armv4_5 = target->arch_info;
529 arm7_9_common_t *arm7_9;
530 arm9tdmi_common_t *arm9tdmi;
531 arm926ejs_common_t *arm926ejs;
532
533 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
534 {
535 return -1;
536 }
537
538 arm7_9 = armv4_5->arch_info;
539 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
540 {
541 return -1;
542 }
543
544 arm9tdmi = arm7_9->arch_info;
545 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
546 {
547 return -1;
548 }
549
550 arm926ejs = arm9tdmi->arch_info;
551 if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
552 {
553 return -1;
554 }
555
556 *armv4_5_p = armv4_5;
557 *arm7_9_p = arm7_9;
558 *arm9tdmi_p = arm9tdmi;
559 *arm926ejs_p = arm926ejs;
560
561 return ERROR_OK;
562 }
563
564 int arm926ejs_arch_state(struct target_s *target)
565 {
566 armv4_5_common_t *armv4_5 = target->arch_info;
567 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
568 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
569 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
570
571 char *state[] =
572 {
573 "disabled", "enabled"
574 };
575
576 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
577 {
578 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
579 exit(-1);
580 }
581
582 LOG_USER(
583 "target halted in %s state due to %s, current mode: %s\n"
584 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
585 "MMU: %s, D-Cache: %s, I-Cache: %s",
586 armv4_5_state_strings[armv4_5->core_state],
587 Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
588 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
589 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
590 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
591 state[arm926ejs->armv4_5_mmu.mmu_enabled],
592 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
593 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
594
595 return ERROR_OK;
596 }
597
598 int arm926ejs_soft_reset_halt(struct target_s *target)
599 {
600 int retval = ERROR_OK;
601 armv4_5_common_t *armv4_5 = target->arch_info;
602 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
603 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
604 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
605 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
606
607 if((retval = target_halt(target)) != ERROR_OK)
608 {
609 return retval;
610 }
611
612 long long then=timeval_ms();
613 int timeout;
614 while (!(timeout=((timeval_ms()-then)>1000)))
615 {
616 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
617 {
618 embeddedice_read_reg(dbg_stat);
619 if((retval = jtag_execute_queue()) != ERROR_OK)
620 {
621 return retval;
622 }
623 } else
624 {
625 break;
626 }
627 if (debug_level>=1)
628 {
629 /* do not eat all CPU, time out after 1 se*/
630 alive_sleep(100);
631 } else
632 {
633 keep_alive();
634 }
635 }
636 if (timeout)
637 {
638 LOG_ERROR("Failed to halt CPU after 1 sec");
639 return ERROR_TARGET_TIMEOUT;
640 }
641
642 target->state = TARGET_HALTED;
643
644 /* SVC, ARM state, IRQ and FIQ disabled */
645 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
646 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
647 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
648
649 /* start fetching from 0x0 */
650 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
651 armv4_5->core_cache->reg_list[15].dirty = 1;
652 armv4_5->core_cache->reg_list[15].valid = 1;
653
654 armv4_5->core_mode = ARMV4_5_MODE_SVC;
655 armv4_5->core_state = ARMV4_5_STATE_ARM;
656
657 arm926ejs_disable_mmu_caches(target, 1, 1, 1);
658 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
659 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
660 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
661
662 return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
663 }
664
665 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
666 {
667 int retval;
668 armv4_5_common_t *armv4_5 = target->arch_info;
669 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
670 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
671 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
672
673 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
674 return retval;
675
676 /* If ICache is enabled, we have to invalidate affected ICache lines
677 * the DCache is forced to write-through, so we don't have to clean it here
678 */
679 if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
680 {
681 if (count <= 1)
682 {
683 /* invalidate ICache single entry with MVA */
684 arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
685 }
686 else
687 {
688 /* invalidate ICache */
689 arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
690 }
691 }
692
693 return retval;
694 }
695
696 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
697 {
698 arm9tdmi_init_target(cmd_ctx, target);
699
700 return ERROR_OK;
701 }
702
703 int arm926ejs_quit(void)
704 {
705 return ERROR_OK;
706 }
707
708 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
709 {
710 arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
711 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
712
713 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
714 */
715 arm9tdmi_init_arch_info(target, arm9tdmi, tap);
716
717 arm9tdmi->arch_info = arm926ejs;
718 arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
719
720 arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
721 arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
722
723 arm926ejs->read_cp15 = arm926ejs_cp15_read;
724 arm926ejs->write_cp15 = arm926ejs_cp15_write;
725 arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
726 arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
727 arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
728 arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
729 arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
730 arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
731 arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
732 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
733
734 arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
735
736 /* The ARM926EJ-S implements the ARMv5TE architecture which
737 * has the BKPT instruction, so we don't have to use a watchpoint comparator
738 */
739 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
740 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
741
742 return ERROR_OK;
743 }
744
745 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
746 {
747 arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
748
749 arm926ejs_init_arch_info(target, arm926ejs, target->tap);
750
751 return ERROR_OK;
752 }
753
754 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
755 {
756 int retval;
757 command_t *arm926ejs_cmd;
758
759
760 retval = arm9tdmi_register_commands(cmd_ctx);
761
762 arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
763
764 register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
765
766 register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
767 register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
768
769 register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
770 register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
771 register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
772
773 register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
774 register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
775 register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
776
777 return retval;
778 }
779
780 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
781 {
782 int retval;
783 target_t *target = get_current_target(cmd_ctx);
784 armv4_5_common_t *armv4_5;
785 arm7_9_common_t *arm7_9;
786 arm9tdmi_common_t *arm9tdmi;
787 arm926ejs_common_t *arm926ejs;
788 int opcode_1;
789 int opcode_2;
790 int CRn;
791 int CRm;
792
793 if ((argc < 4) || (argc > 5))
794 {
795 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
796 return ERROR_OK;
797 }
798
799 opcode_1 = strtoul(args[0], NULL, 0);
800 opcode_2 = strtoul(args[1], NULL, 0);
801 CRn = strtoul(args[2], NULL, 0);
802 CRm = strtoul(args[3], NULL, 0);
803
804 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
805 {
806 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
807 return ERROR_OK;
808 }
809
810 if (target->state != TARGET_HALTED)
811 {
812 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
813 return ERROR_OK;
814 }
815
816 if (argc == 4)
817 {
818 u32 value;
819 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
820 {
821 command_print(cmd_ctx, "couldn't access register");
822 return ERROR_OK;
823 }
824 if((retval = jtag_execute_queue()) != ERROR_OK)
825 {
826 return retval;
827 }
828
829 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
830 }
831 else
832 {
833 u32 value = strtoul(args[4], NULL, 0);
834 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
835 {
836 command_print(cmd_ctx, "couldn't access register");
837 return ERROR_OK;
838 }
839 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
840 }
841
842 return ERROR_OK;
843 }
844
845 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
846 {
847 target_t *target = get_current_target(cmd_ctx);
848 armv4_5_common_t *armv4_5;
849 arm7_9_common_t *arm7_9;
850 arm9tdmi_common_t *arm9tdmi;
851 arm926ejs_common_t *arm926ejs;
852
853 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
854 {
855 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
856 return ERROR_OK;
857 }
858
859 return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
860 }
861
862 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
863 {
864 target_t *target = get_current_target(cmd_ctx);
865 armv4_5_common_t *armv4_5;
866 arm7_9_common_t *arm7_9;
867 arm9tdmi_common_t *arm9tdmi;
868 arm926ejs_common_t *arm926ejs;
869 arm_jtag_t *jtag_info;
870
871 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
872 {
873 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
874 return ERROR_OK;
875 }
876
877 jtag_info = &arm7_9->jtag_info;
878
879 if (target->state != TARGET_HALTED)
880 {
881 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
882 return ERROR_OK;
883 }
884
885 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
886 }
887
888 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
889 {
890 target_t *target = get_current_target(cmd_ctx);
891 armv4_5_common_t *armv4_5;
892 arm7_9_common_t *arm7_9;
893 arm9tdmi_common_t *arm9tdmi;
894 arm926ejs_common_t *arm926ejs;
895 arm_jtag_t *jtag_info;
896
897 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
898 {
899 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
900 return ERROR_OK;
901 }
902
903 jtag_info = &arm7_9->jtag_info;
904
905 if (target->state != TARGET_HALTED)
906 {
907 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
908 return ERROR_OK;
909 }
910
911 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
912 }
913
914 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
915 {
916 target_t *target = get_current_target(cmd_ctx);
917 armv4_5_common_t *armv4_5;
918 arm7_9_common_t *arm7_9;
919 arm9tdmi_common_t *arm9tdmi;
920 arm926ejs_common_t *arm926ejs;
921 arm_jtag_t *jtag_info;
922
923 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
924 {
925 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
926 return ERROR_OK;
927 }
928
929 jtag_info = &arm7_9->jtag_info;
930
931 if (target->state != TARGET_HALTED)
932 {
933 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
934 return ERROR_OK;
935 }
936
937 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
938 }
939
940 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
941 {
942 int retval;
943 int type;
944 u32 cb;
945 int domain;
946 u32 ap;
947
948 armv4_5_common_t *armv4_5;
949 arm7_9_common_t *arm7_9;
950 arm9tdmi_common_t *arm9tdmi;
951 arm926ejs_common_t *arm926ejs;
952 retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
953 if (retval != ERROR_OK)
954 {
955 return retval;
956 }
957 u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
958 if (type == -1)
959 {
960 return ret;
961 }
962 *physical = ret;
963 return ERROR_OK;
964 }
965
966 static int arm926ejs_mmu(struct target_s *target, int *enabled)
967 {
968 armv4_5_common_t *armv4_5 = target->arch_info;
969 arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
970
971 if (target->state != TARGET_HALTED)
972 {
973 LOG_ERROR("Target not halted");
974 return ERROR_TARGET_INVALID;
975 }
976 *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
977 return ERROR_OK;
978 }
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