src/target/arm926ejs.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm926ejs.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27 #include "time_support.h"
  28
  29 #include <stdlib.h>
  30 #include <string.h>
  31
  32 #if 0
  33 #define _DEBUG_INSTRUCTION_EXECUTION_
  34 #endif
  35
  36 /* cli handling */
  37 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  38 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43
  44 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  45 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46
  47 /* forward declarations */
  48 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
  49 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  50 int arm926ejs_quit(void);
  51 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  52
  53 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
  54 static int arm926ejs_mmu(struct target_s *target, int *enabled);
  55
  56 target_type_t arm926ejs_target =
  57 {
  58         .name = "arm926ejs",
  59
  60         .poll = arm7_9_poll,
  61         .arch_state = arm926ejs_arch_state,
  62
  63         .target_request_data = arm7_9_target_request_data,
  64
  65         .halt = arm7_9_halt,
  66         .resume = arm7_9_resume,
  67         .step = arm7_9_step,
  68
  69         .assert_reset = arm7_9_assert_reset,
  70         .deassert_reset = arm7_9_deassert_reset,
  71         .soft_reset_halt = arm926ejs_soft_reset_halt,
  72
  73         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  74
  75         .read_memory = arm7_9_read_memory,
  76         .write_memory = arm926ejs_write_memory,
  77         .bulk_write_memory = arm7_9_bulk_write_memory,
  78         .checksum_memory = arm7_9_checksum_memory,
  79         .blank_check_memory = arm7_9_blank_check_memory,
  80
  81         .run_algorithm = armv4_5_run_algorithm,
  82
  83         .add_breakpoint = arm7_9_add_breakpoint,
  84         .remove_breakpoint = arm7_9_remove_breakpoint,
  85         .add_watchpoint = arm7_9_add_watchpoint,
  86         .remove_watchpoint = arm7_9_remove_watchpoint,
  87
  88         .register_commands = arm926ejs_register_commands,
  89         .target_create = arm926ejs_target_create,
  90         .init_target = arm926ejs_init_target,
  91         .examine = arm9tdmi_examine,
  92         .quit = arm926ejs_quit,
  93         .virt2phys = arm926ejs_virt2phys,
  94         .mmu = arm926ejs_mmu
  95 };
  96
  97 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
  98 {
  99         /* The ARM926EJ-S' instruction register is 4 bits wide */
 100         u8 t = *captured & 0xf;
 101         u8 t2 = *field->in_check_value & 0xf;
 102         if (t == t2)
 103         {
 104                 return ERROR_OK;
 105         }
 106         else if ((t == 0x0f) || (t == 0x00))
 107         {
 108                 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
 109                 return ERROR_OK;
 110         }
 111         return ERROR_JTAG_QUEUE_FAILED;;
 112 }
 113
 114 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
 115
 116 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
 117 {
 118         int retval = ERROR_OK;
 119         armv4_5_common_t *armv4_5 = target->arch_info;
 120         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 121         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 122         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 123         scan_field_t fields[4];
 124         u8 address_buf[2];
 125         u8 nr_w_buf = 0;
 126         u8 access = 1;
 127
 128         buf_set_u32(address_buf, 0, 14, address);
 129
 130         jtag_add_end_state(TAP_IDLE);
 131         if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 132         {
 133                 return retval;
 134         }
 135         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 136
 137         fields[0].tap = jtag_info->tap;
 138         fields[0].num_bits = 32;
 139         fields[0].out_value = NULL;
 140         u8 tmp[4];
 141         fields[0].in_value = tmp;
 142         fields[0].in_handler = NULL;
 143
 144         fields[1].tap = jtag_info->tap;
 145         fields[1].num_bits = 1;
 146         fields[1].out_value = &access;
 147         fields[1].in_value = &access;
 148         fields[1].in_handler = NULL;
 149
 150         fields[2].tap = jtag_info->tap;
 151         fields[2].num_bits = 14;
 152         fields[2].out_value = address_buf;
 153         fields[2].in_value = NULL;
 154         fields[2].in_handler = NULL;
 155
 156
 157         fields[3].tap = jtag_info->tap;
 158         fields[3].num_bits = 1;
 159         fields[3].out_value = &nr_w_buf;
 160         fields[3].in_value = NULL;
 161         fields[3].in_handler = NULL;
 162
 163         jtag_add_dr_scan(4, fields, TAP_INVALID);
 164
 165         /*TODO: add timeout*/
 166         do
 167         {
 168                 /* rescan with NOP, to wait for the access to complete */
 169                 access = 0;
 170                 nr_w_buf = 0;
 171                 jtag_add_dr_scan_now(4, fields, TAP_INVALID);
 172
 173                 *value=le_to_h_u32(tmp);
 174
 175                 if((retval = jtag_execute_queue()) != ERROR_OK)
 176                 {
 177                         return retval;
 178                 }
 179         } while (buf_get_u32(&access, 0, 1) != 1);
 180
 181 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 182         LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 183 #endif
 184
 185         arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
 186
 187         return ERROR_OK;
 188 }
 189
 190 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
 191 {
 192         int retval = ERROR_OK;
 193         armv4_5_common_t *armv4_5 = target->arch_info;
 194         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 195         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 196         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 197         scan_field_t fields[4];
 198         u8 value_buf[4];
 199         u8 address_buf[2];
 200         u8 nr_w_buf = 1;
 201         u8 access = 1;
 202
 203         buf_set_u32(address_buf, 0, 14, address);
 204         buf_set_u32(value_buf, 0, 32, value);
 205
 206         jtag_add_end_state(TAP_IDLE);
 207         if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 208         {
 209                 return retval;
 210         }
 211         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 212
 213         fields[0].tap = jtag_info->tap;
 214         fields[0].num_bits = 32;
 215         fields[0].out_value = value_buf;
 216
 217         fields[0].in_value = NULL;
 218
 219
 220         fields[0].in_handler = NULL;
 221
 222
 223         fields[1].tap = jtag_info->tap;
 224         fields[1].num_bits = 1;
 225         fields[1].out_value = &access;
 226
 227         fields[1].in_value = &access;
 228
 229
 230         fields[1].in_handler = NULL;
 231
 232
 233         fields[2].tap = jtag_info->tap;
 234         fields[2].num_bits = 14;
 235         fields[2].out_value = address_buf;
 236
 237         fields[2].in_value = NULL;
 238
 239
 240         fields[2].in_handler = NULL;
 241
 242
 243         fields[3].tap = jtag_info->tap;
 244         fields[3].num_bits = 1;
 245         fields[3].out_value = &nr_w_buf;
 246
 247         fields[3].in_value = NULL;
 248
 249
 250         fields[3].in_handler = NULL;
 251
 252
 253         jtag_add_dr_scan(4, fields, TAP_INVALID);
 254         /*TODO: add timeout*/
 255         do
 256         {
 257                 /* rescan with NOP, to wait for the access to complete */
 258                 access = 0;
 259                 nr_w_buf = 0;
 260                 jtag_add_dr_scan(4, fields, TAP_INVALID);
 261                 if((retval = jtag_execute_queue()) != ERROR_OK)
 262                 {
 263                         return retval;
 264                 }
 265         } while (buf_get_u32(&access, 0, 1) != 1);
 266
 267 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 268         LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 269 #endif
 270
 271         arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
 272
 273         return ERROR_OK;
 274 }
 275
 276 int arm926ejs_examine_debug_reason(target_t *target)
 277 {
 278         armv4_5_common_t *armv4_5 = target->arch_info;
 279         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 280         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 281         int debug_reason;
 282         int retval;
 283
 284         embeddedice_read_reg(dbg_stat);
 285         if ((retval = jtag_execute_queue()) != ERROR_OK)
 286                 return retval;
 287
 288         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
 289
 290         switch (debug_reason)
 291         {
 292                 case 1:
 293                         LOG_DEBUG("breakpoint from EICE unit 0");
 294                         target->debug_reason = DBG_REASON_BREAKPOINT;
 295                         break;
 296                 case 2:
 297                         LOG_DEBUG("breakpoint from EICE unit 1");
 298                         target->debug_reason = DBG_REASON_BREAKPOINT;
 299                         break;
 300                 case 3:
 301                         LOG_DEBUG("soft breakpoint (BKPT instruction)");
 302                         target->debug_reason = DBG_REASON_BREAKPOINT;
 303                         break;
 304                 case 4:
 305                         LOG_DEBUG("vector catch breakpoint");
 306                         target->debug_reason = DBG_REASON_BREAKPOINT;
 307                         break;
 308                 case 5:
 309                         LOG_DEBUG("external breakpoint");
 310                         target->debug_reason = DBG_REASON_BREAKPOINT;
 311                         break;
 312                 case 6:
 313                         LOG_DEBUG("watchpoint from EICE unit 0");
 314                         target->debug_reason = DBG_REASON_WATCHPOINT;
 315                         break;
 316                 case 7:
 317                         LOG_DEBUG("watchpoint from EICE unit 1");
 318                         target->debug_reason = DBG_REASON_WATCHPOINT;
 319                         break;
 320                 case 8:
 321                         LOG_DEBUG("external watchpoint");
 322                         target->debug_reason = DBG_REASON_WATCHPOINT;
 323                         break;
 324                 case 9:
 325                         LOG_DEBUG("internal debug request");
 326                         target->debug_reason = DBG_REASON_DBGRQ;
 327                         break;
 328                 case 10:
 329                         LOG_DEBUG("external debug request");
 330                         target->debug_reason = DBG_REASON_DBGRQ;
 331                         break;
 332                 case 11:
 333                         LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
 334                         break;
 335                 case 12:
 336                         /* FIX!!!! here be dragons!!! We need to fail here so
 337                          * the target will interpreted as halted but we won't
 338                          * try to talk to it right now... a resume + halt seems
 339                          * to sync things up again. Please send an email to
 340                          * openocd development mailing list if you have hardware
 341                          * to donate to look into this problem....
 342                          */
 343                         LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
 344                         target->debug_reason = DBG_REASON_DBGRQ;
 345                         retval = ERROR_TARGET_FAILURE;
 346                         break;
 347                 default:
 348                         LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
 349                         target->debug_reason = DBG_REASON_DBGRQ;
 350                         /* if we fail here, we won't talk to the target and it will
 351                          * be reported to be in the halted state */
 352                         retval = ERROR_TARGET_FAILURE;
 353                         break;
 354         }
 355
 356         return retval;
 357 }
 358
 359 u32 arm926ejs_get_ttb(target_t *target)
 360 {
 361         armv4_5_common_t *armv4_5 = target->arch_info;
 362         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 363         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 364         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 365         int retval;
 366         u32 ttb = 0x0;
 367
 368         if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
 369                 return retval;
 370
 371         return ttb;
 372 }
 373
 374 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 375 {
 376         armv4_5_common_t *armv4_5 = target->arch_info;
 377         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 378         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 379         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 380         u32 cp15_control;
 381
 382         /* read cp15 control register */
 383         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 384         jtag_execute_queue();
 385
 386         if (mmu)
 387         {
 388                 /* invalidate TLB */
 389                 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
 390
 391                 cp15_control &= ~0x1U;
 392         }
 393
 394         if (d_u_cache)
 395         {
 396                 u32 debug_override;
 397                 /* read-modify-write CP15 debug override register
 398                  * to enable "test and clean all" */
 399                 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
 400                 debug_override |= 0x80000;
 401                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 402
 403                 /* clean and invalidate DCache */
 404                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 405
 406                 /* write CP15 debug override register
 407                  * to disable "test and clean all" */
 408                 debug_override &= ~0x80000;
 409                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 410
 411                 cp15_control &= ~0x4U;
 412         }
 413
 414         if (i_cache)
 415         {
 416                 /* invalidate ICache */
 417                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 418
 419                 cp15_control &= ~0x1000U;
 420         }
 421
 422         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 423 }
 424
 425 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 426 {
 427         armv4_5_common_t *armv4_5 = target->arch_info;
 428         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 429         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 430         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 431         u32 cp15_control;
 432
 433         /* read cp15 control register */
 434         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 435         jtag_execute_queue();
 436
 437         if (mmu)
 438                 cp15_control |= 0x1U;
 439
 440         if (d_u_cache)
 441                 cp15_control |= 0x4U;
 442
 443         if (i_cache)
 444                 cp15_control |= 0x1000U;
 445
 446         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 447 }
 448
 449 void arm926ejs_post_debug_entry(target_t *target)
 450 {
 451         armv4_5_common_t *armv4_5 = target->arch_info;
 452         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 453         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 454         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 455
 456         /* examine cp15 control reg */
 457         arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
 458         jtag_execute_queue();
 459         LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
 460
 461         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 462         {
 463                 u32 cache_type_reg;
 464                 /* identify caches */
 465                 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
 466                 jtag_execute_queue();
 467                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 468         }
 469
 470         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
 471         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
 472         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 473
 474         /* save i/d fault status and address register */
 475         arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
 476         arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
 477         arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
 478
 479         LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
 480                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 481
 482         u32 cache_dbg_ctrl;
 483
 484         /* read-modify-write CP15 cache debug control register
 485          * to disable I/D-cache linefills and force WT */
 486         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 487         cache_dbg_ctrl |= 0x7;
 488         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 489 }
 490
 491 void arm926ejs_pre_restore_context(target_t *target)
 492 {
 493         armv4_5_common_t *armv4_5 = target->arch_info;
 494         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 495         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 496         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 497
 498         /* restore i/d fault status and address register */
 499         arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
 500         arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
 501         arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
 502
 503         u32 cache_dbg_ctrl;
 504
 505         /* read-modify-write CP15 cache debug control register
 506          * to reenable I/D-cache linefills and disable WT */
 507         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 508         cache_dbg_ctrl &= ~0x7;
 509         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 510 }
 511
 512 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
 513 {
 514         armv4_5_common_t *armv4_5 = target->arch_info;
 515         arm7_9_common_t *arm7_9;
 516         arm9tdmi_common_t *arm9tdmi;
 517         arm926ejs_common_t *arm926ejs;
 518
 519         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 520         {
 521                 return -1;
 522         }
 523
 524         arm7_9 = armv4_5->arch_info;
 525         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 526         {
 527                 return -1;
 528         }
 529
 530         arm9tdmi = arm7_9->arch_info;
 531         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 532         {
 533                 return -1;
 534         }
 535
 536         arm926ejs = arm9tdmi->arch_info;
 537         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
 538         {
 539                 return -1;
 540         }
 541
 542         *armv4_5_p = armv4_5;
 543         *arm7_9_p = arm7_9;
 544         *arm9tdmi_p = arm9tdmi;
 545         *arm926ejs_p = arm926ejs;
 546
 547         return ERROR_OK;
 548 }
 549
 550 int arm926ejs_arch_state(struct target_s *target)
 551 {
 552         armv4_5_common_t *armv4_5 = target->arch_info;
 553         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 554         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 555         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 556
 557         char *state[] =
 558         {
 559                 "disabled", "enabled"
 560         };
 561
 562         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 563         {
 564                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 565                 exit(-1);
 566         }
 567
 568         LOG_USER(
 569                         "target halted in %s state due to %s, current mode: %s\n"
 570                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 571                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 572                          armv4_5_state_strings[armv4_5->core_state],
 573                          Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
 574                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 575                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 576                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 577                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
 578                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 579                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 580
 581         return ERROR_OK;
 582 }
 583
 584 int arm926ejs_soft_reset_halt(struct target_s *target)
 585 {
 586         int retval = ERROR_OK;
 587         armv4_5_common_t *armv4_5 = target->arch_info;
 588         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 589         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 590         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 591         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 592
 593         if((retval = target_halt(target)) != ERROR_OK)
 594         {
 595                 return retval;
 596         }
 597
 598         long long then=timeval_ms();
 599         int timeout;
 600         while (!(timeout=((timeval_ms()-then)>1000)))
 601         {
 602                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 603                 {
 604                         embeddedice_read_reg(dbg_stat);
 605                         if((retval = jtag_execute_queue()) != ERROR_OK)
 606                         {
 607                                 return retval;
 608                         }
 609                 }  else
 610                 {
 611                         break;
 612                 }
 613                 if (debug_level>=1)
 614                 {
 615                         /* do not eat all CPU, time out after 1 se*/
 616                         alive_sleep(100);
 617                 } else
 618                 {
 619                         keep_alive();
 620                 }
 621         }
 622         if (timeout)
 623         {
 624                 LOG_ERROR("Failed to halt CPU after 1 sec");
 625                 return ERROR_TARGET_TIMEOUT;
 626         }
 627
 628         target->state = TARGET_HALTED;
 629
 630         /* SVC, ARM state, IRQ and FIQ disabled */
 631         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 632         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 633         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 634
 635         /* start fetching from 0x0 */
 636         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 637         armv4_5->core_cache->reg_list[15].dirty = 1;
 638         armv4_5->core_cache->reg_list[15].valid = 1;
 639
 640         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 641         armv4_5->core_state = ARMV4_5_STATE_ARM;
 642
 643         arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 644         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 645         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 646         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 647
 648         return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 649 }
 650
 651 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 652 {
 653         int retval;
 654         armv4_5_common_t *armv4_5 = target->arch_info;
 655         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 656         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 657         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 658
 659         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 660                 return retval;
 661
 662         /* If ICache is enabled, we have to invalidate affected ICache lines
 663          * the DCache is forced to write-through, so we don't have to clean it here
 664          */
 665         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 666         {
 667                 if (count <= 1)
 668                 {
 669                         /* invalidate ICache single entry with MVA */
 670                         arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
 671                 }
 672                 else
 673                 {
 674                         /* invalidate ICache */
 675                         arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
 676                 }
 677         }
 678
 679         return retval;
 680 }
 681
 682 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 683 {
 684         arm9tdmi_init_target(cmd_ctx, target);
 685
 686         return ERROR_OK;
 687 }
 688
 689 int arm926ejs_quit(void)
 690 {
 691         return ERROR_OK;
 692 }
 693
 694 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
 695 {
 696         arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 697         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 698
 699         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 700          */
 701         arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 702
 703         arm9tdmi->arch_info = arm926ejs;
 704         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
 705
 706         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
 707         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
 708
 709         arm926ejs->read_cp15 = arm926ejs_cp15_read;
 710         arm926ejs->write_cp15 = arm926ejs_cp15_write;
 711         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
 712         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
 713         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
 714         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
 715         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
 716         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
 717         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
 718         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 719
 720         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
 721
 722         /* The ARM926EJ-S implements the ARMv5TE architecture which
 723          * has the BKPT instruction, so we don't have to use a watchpoint comparator
 724          */
 725         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
 726         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 727
 728         return ERROR_OK;
 729 }
 730
 731 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
 732 {
 733         arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
 734
 735         arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 736
 737         return ERROR_OK;
 738 }
 739
 740 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
 741 {
 742         int retval;
 743         command_t *arm926ejs_cmd;
 744
 745
 746         retval = arm9tdmi_register_commands(cmd_ctx);
 747
 748         arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
 749
 750         register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 751
 752         register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 753         register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 754
 755         register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 756         register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 757         register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 758
 759         register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 760         register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 761         register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 762
 763         return retval;
 764 }
 765
 766 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 767 {
 768         int retval;
 769         target_t *target = get_current_target(cmd_ctx);
 770         armv4_5_common_t *armv4_5;
 771         arm7_9_common_t *arm7_9;
 772         arm9tdmi_common_t *arm9tdmi;
 773         arm926ejs_common_t *arm926ejs;
 774         int opcode_1;
 775         int opcode_2;
 776         int CRn;
 777         int CRm;
 778
 779         if ((argc < 4) || (argc > 5))
 780         {
 781                 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 782                 return ERROR_OK;
 783         }
 784
 785         opcode_1 = strtoul(args[0], NULL, 0);
 786         opcode_2 = strtoul(args[1], NULL, 0);
 787         CRn = strtoul(args[2], NULL, 0);
 788         CRm = strtoul(args[3], NULL, 0);
 789
 790         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 791         {
 792                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 793                 return ERROR_OK;
 794         }
 795
 796         if (target->state != TARGET_HALTED)
 797         {
 798                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 799                 return ERROR_OK;
 800         }
 801
 802         if (argc == 4)
 803         {
 804                 u32 value;
 805                 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
 806                 {
 807                         command_print(cmd_ctx, "couldn't access register");
 808                         return ERROR_OK;
 809                 }
 810                 if((retval = jtag_execute_queue()) != ERROR_OK)
 811                 {
 812                         return retval;
 813                 }
 814
 815                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 816         }
 817         else
 818         {
 819                 u32 value = strtoul(args[4], NULL, 0);
 820                 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
 821                 {
 822                         command_print(cmd_ctx, "couldn't access register");
 823                         return ERROR_OK;
 824                 }
 825                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 826         }
 827
 828         return ERROR_OK;
 829 }
 830
 831 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 832 {
 833         target_t *target = get_current_target(cmd_ctx);
 834         armv4_5_common_t *armv4_5;
 835         arm7_9_common_t *arm7_9;
 836         arm9tdmi_common_t *arm9tdmi;
 837         arm926ejs_common_t *arm926ejs;
 838
 839         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 840         {
 841                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 842                 return ERROR_OK;
 843         }
 844
 845         return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 846 }
 847
 848 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 849 {
 850         target_t *target = get_current_target(cmd_ctx);
 851         armv4_5_common_t *armv4_5;
 852         arm7_9_common_t *arm7_9;
 853         arm9tdmi_common_t *arm9tdmi;
 854         arm926ejs_common_t *arm926ejs;
 855         arm_jtag_t *jtag_info;
 856
 857         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 858         {
 859                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 860                 return ERROR_OK;
 861         }
 862
 863         jtag_info = &arm7_9->jtag_info;
 864
 865         if (target->state != TARGET_HALTED)
 866         {
 867                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 868                 return ERROR_OK;
 869         }
 870
 871         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 872 }
 873
 874 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 875 {
 876         target_t *target = get_current_target(cmd_ctx);
 877         armv4_5_common_t *armv4_5;
 878         arm7_9_common_t *arm7_9;
 879         arm9tdmi_common_t *arm9tdmi;
 880         arm926ejs_common_t *arm926ejs;
 881         arm_jtag_t *jtag_info;
 882
 883         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 884         {
 885                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 886                 return ERROR_OK;
 887         }
 888
 889         jtag_info = &arm7_9->jtag_info;
 890
 891         if (target->state != TARGET_HALTED)
 892         {
 893                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 894                 return ERROR_OK;
 895         }
 896
 897         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 898 }
 899
 900 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 901 {
 902         target_t *target = get_current_target(cmd_ctx);
 903         armv4_5_common_t *armv4_5;
 904         arm7_9_common_t *arm7_9;
 905         arm9tdmi_common_t *arm9tdmi;
 906         arm926ejs_common_t *arm926ejs;
 907         arm_jtag_t *jtag_info;
 908
 909         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 910         {
 911                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 912                 return ERROR_OK;
 913         }
 914
 915         jtag_info = &arm7_9->jtag_info;
 916
 917         if (target->state != TARGET_HALTED)
 918         {
 919                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 920                 return ERROR_OK;
 921         }
 922
 923         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 924 }
 925
 926 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
 927 {
 928         int retval;
 929         int type;
 930         u32 cb;
 931         int domain;
 932         u32 ap;
 933
 934         armv4_5_common_t *armv4_5;
 935         arm7_9_common_t *arm7_9;
 936         arm9tdmi_common_t *arm9tdmi;
 937         arm926ejs_common_t *arm926ejs;
 938         retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
 939         if (retval != ERROR_OK)
 940         {
 941                 return retval;
 942         }
 943         u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
 944         if (type == -1)
 945         {
 946                 return ret;
 947         }
 948         *physical = ret;
 949         return ERROR_OK;
 950 }
 951
 952 static int arm926ejs_mmu(struct target_s *target, int *enabled)
 953 {
 954         armv4_5_common_t *armv4_5 = target->arch_info;
 955         arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
 956
 957         if (target->state != TARGET_HALTED)
 958         {
 959                 LOG_ERROR("Target not halted");
 960                 return ERROR_TARGET_INVALID;
 961         }
 962         *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
 963         return ERROR_OK;
 964 }