1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
);
38 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm926ejs_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm926ejs_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm926ejs_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm926ejs_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int arm926ejs_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm926ejs_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 /* forward declarations */
49 int arm926ejs_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
50 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm926ejs_arch_state(struct target_s
*target
, char *buf
, int buf_size
);
53 int arm926ejs_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
54 int arm926ejs_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm926ejs_soft_reset_halt(struct target_s
*target
);
57 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
59 target_type_t arm926ejs_target
=
64 .arch_state
= arm926ejs_arch_state
,
66 .target_request_data
= arm7_9_target_request_data
,
69 .resume
= arm7_9_resume
,
72 .assert_reset
= arm7_9_assert_reset
,
73 .deassert_reset
= arm7_9_deassert_reset
,
74 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
75 .prepare_reset_halt
= arm7_9_prepare_reset_halt
,
77 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
79 .read_memory
= arm7_9_read_memory
,
80 .write_memory
= arm926ejs_write_memory
,
81 .bulk_write_memory
= arm7_9_bulk_write_memory
,
83 .run_algorithm
= armv4_5_run_algorithm
,
85 .add_breakpoint
= arm7_9_add_breakpoint
,
86 .remove_breakpoint
= arm7_9_remove_breakpoint
,
87 .add_watchpoint
= arm7_9_add_watchpoint
,
88 .remove_watchpoint
= arm7_9_remove_watchpoint
,
90 .register_commands
= arm926ejs_register_commands
,
91 .target_command
= arm926ejs_target_command
,
92 .init_target
= arm926ejs_init_target
,
93 .quit
= arm926ejs_quit
96 int arm926ejs_catch_broken_irscan(u8
*in_value
, void *priv
)
98 /* The ARM926EJ-S' instruction register is 4 bits wide */
101 if ((*in_value
== 0x0f) || (*in_value
== 0x00))
103 DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
108 return ERROR_JTAG_QUEUE_FAILED
;
112 int arm926ejs_read_cp15(target_t
*target
, u32 address
, u32
*value
)
114 armv4_5_common_t
*armv4_5
= target
->arch_info
;
115 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
116 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
117 scan_field_t fields
[4];
121 error_handler_t error_handler
;
123 buf_set_u32(address_buf
, 0, 14, address
);
125 jtag_add_end_state(TAP_RTI
);
126 arm_jtag_scann(jtag_info
, 0xf);
127 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
129 fields
[0].device
= jtag_info
->chain_pos
;
130 fields
[0].num_bits
= 32;
131 fields
[0].out_value
= NULL
;
132 fields
[0].out_mask
= NULL
;
133 fields
[0].in_value
= NULL
;
134 fields
[0].in_check_value
= NULL
;
135 fields
[0].in_check_mask
= NULL
;
136 fields
[0].in_handler
= NULL
;
137 fields
[0].in_handler_priv
= NULL
;
139 fields
[1].device
= jtag_info
->chain_pos
;
140 fields
[1].num_bits
= 1;
141 fields
[1].out_value
= &access
;
142 fields
[1].out_mask
= NULL
;
143 fields
[1].in_value
= &access
;
144 fields
[1].in_check_value
= NULL
;
145 fields
[1].in_check_mask
= NULL
;
146 fields
[1].in_handler
= NULL
;
147 fields
[1].in_handler_priv
= NULL
;
149 fields
[2].device
= jtag_info
->chain_pos
;
150 fields
[2].num_bits
= 14;
151 fields
[2].out_value
= address_buf
;
152 fields
[2].out_mask
= NULL
;
153 fields
[2].in_value
= NULL
;
154 fields
[2].in_check_value
= NULL
;
155 fields
[2].in_check_mask
= NULL
;
156 fields
[2].in_handler
= NULL
;
157 fields
[2].in_handler_priv
= NULL
;
159 fields
[3].device
= jtag_info
->chain_pos
;
160 fields
[3].num_bits
= 1;
161 fields
[3].out_value
= &nr_w_buf
;
162 fields
[3].out_mask
= NULL
;
163 fields
[3].in_value
= NULL
;
164 fields
[3].in_check_value
= NULL
;
165 fields
[3].in_check_mask
= NULL
;
166 fields
[3].in_handler
= NULL
;
167 fields
[3].in_handler_priv
= NULL
;
169 jtag_add_dr_scan(4, fields
, -1, NULL
);
171 fields
[0].in_handler_priv
= value
;
172 fields
[0].in_handler
= arm_jtag_buf_to_u32
;
176 /* rescan with NOP, to wait for the access to complete */
179 jtag_add_dr_scan(4, fields
, -1, NULL
);
180 jtag_execute_queue();
181 } while (buf_get_u32(&access
, 0, 1) != 1);
183 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
184 DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
187 error_handler
.error_handler
= arm926ejs_catch_broken_irscan
;
188 error_handler
.error_handler_priv
= NULL
;
190 arm_jtag_set_instr(jtag_info
, 0xc, &error_handler
);
195 int arm926ejs_write_cp15(target_t
*target
, u32 address
, u32 value
)
197 armv4_5_common_t
*armv4_5
= target
->arch_info
;
198 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
199 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
200 scan_field_t fields
[4];
205 error_handler_t error_handler
;
207 buf_set_u32(address_buf
, 0, 14, address
);
208 buf_set_u32(value_buf
, 0, 32, value
);
210 jtag_add_end_state(TAP_RTI
);
211 arm_jtag_scann(jtag_info
, 0xf);
212 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
214 fields
[0].device
= jtag_info
->chain_pos
;
215 fields
[0].num_bits
= 32;
216 fields
[0].out_value
= value_buf
;
217 fields
[0].out_mask
= NULL
;
218 fields
[0].in_value
= NULL
;
219 fields
[0].in_check_value
= NULL
;
220 fields
[0].in_check_mask
= NULL
;
221 fields
[0].in_handler
= NULL
;
222 fields
[0].in_handler_priv
= NULL
;
224 fields
[1].device
= jtag_info
->chain_pos
;
225 fields
[1].num_bits
= 1;
226 fields
[1].out_value
= &access
;
227 fields
[1].out_mask
= NULL
;
228 fields
[1].in_value
= &access
;
229 fields
[1].in_check_value
= NULL
;
230 fields
[1].in_check_mask
= NULL
;
231 fields
[1].in_handler
= NULL
;
232 fields
[1].in_handler_priv
= NULL
;
234 fields
[2].device
= jtag_info
->chain_pos
;
235 fields
[2].num_bits
= 14;
236 fields
[2].out_value
= address_buf
;
237 fields
[2].out_mask
= NULL
;
238 fields
[2].in_value
= NULL
;
239 fields
[2].in_check_value
= NULL
;
240 fields
[2].in_check_mask
= NULL
;
241 fields
[2].in_handler
= NULL
;
242 fields
[2].in_handler_priv
= NULL
;
244 fields
[3].device
= jtag_info
->chain_pos
;
245 fields
[3].num_bits
= 1;
246 fields
[3].out_value
= &nr_w_buf
;
247 fields
[3].out_mask
= NULL
;
248 fields
[3].in_value
= NULL
;
249 fields
[3].in_check_value
= NULL
;
250 fields
[3].in_check_mask
= NULL
;
251 fields
[3].in_handler
= NULL
;
252 fields
[3].in_handler_priv
= NULL
;
254 jtag_add_dr_scan(4, fields
, -1, NULL
);
258 /* rescan with NOP, to wait for the access to complete */
261 jtag_add_dr_scan(4, fields
, -1, NULL
);
262 jtag_execute_queue();
263 } while (buf_get_u32(&access
, 0, 1) != 1);
265 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
266 DEBUG("addr: 0x%x value: %8.8x", address
, value
);
269 error_handler
.error_handler
= arm926ejs_catch_broken_irscan
;
270 error_handler
.error_handler_priv
= NULL
;
272 arm_jtag_set_instr(jtag_info
, 0xf, &error_handler
);
277 int arm926ejs_examine_debug_reason(target_t
*target
)
279 armv4_5_common_t
*armv4_5
= target
->arch_info
;
280 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
281 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
285 embeddedice_read_reg(dbg_stat
);
286 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
289 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
291 switch (debug_reason
)
294 DEBUG("breakpoint from EICE unit 0");
295 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
298 DEBUG("breakpoint from EICE unit 1");
299 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
302 DEBUG("soft breakpoint (BKPT instruction)");
303 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
306 DEBUG("vector catch breakpoint");
307 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
310 DEBUG("external breakpoint");
311 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
314 DEBUG("watchpoint from EICE unit 0");
315 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
318 DEBUG("watchpoint from EICE unit 1");
319 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
322 DEBUG("external watchpoint");
323 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
326 DEBUG("internal debug request");
327 target
->debug_reason
= DBG_REASON_DBGRQ
;
330 DEBUG("external debug request");
331 target
->debug_reason
= DBG_REASON_DBGRQ
;
334 ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
337 ERROR("BUG: unknown debug reason: 0x%x", debug_reason
);
338 target
->debug_reason
= DBG_REASON_DBGRQ
;
344 u32
arm926ejs_get_ttb(target_t
*target
)
349 if ((retval
= arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 2, 0), &ttb
)) != ERROR_OK
)
355 void arm926ejs_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
359 /* read cp15 control register */
360 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control
);
361 jtag_execute_queue();
366 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 8, 7), 0x0);
368 cp15_control
&= ~0x1U
;
374 /* read-modify-write CP15 debug override register
375 * to enable "test and clean all" */
376 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 15, 0), &debug_override
);
377 debug_override
|= 0x80000;
378 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override
);
380 /* clean and invalidate DCache */
381 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
383 /* write CP15 debug override register
384 * to disable "test and clean all" */
385 debug_override
&= ~0x80000;
386 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override
);
388 cp15_control
&= ~0x4U
;
393 /* invalidate ICache */
394 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
396 cp15_control
&= ~0x1000U
;
399 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control
);
402 void arm926ejs_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
406 /* read cp15 control register */
407 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control
);
408 jtag_execute_queue();
411 cp15_control
|= 0x1U
;
414 cp15_control
|= 0x4U
;
417 cp15_control
|= 0x1000U
;
419 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control
);
422 void arm926ejs_post_debug_entry(target_t
*target
)
424 armv4_5_common_t
*armv4_5
= target
->arch_info
;
425 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
426 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
427 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
429 /* examine cp15 control reg */
430 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &arm926ejs
->cp15_control_reg
);
431 jtag_execute_queue();
432 DEBUG("cp15_control_reg: %8.8x", arm926ejs
->cp15_control_reg
);
434 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
437 /* identify caches */
438 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 1, 0, 0), &cache_type_reg
);
439 jtag_execute_queue();
440 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
443 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
444 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
445 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
447 /* save i/d fault status and address register */
448 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 5, 0), &arm926ejs
->d_fsr
);
449 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 1, 5, 0), &arm926ejs
->i_fsr
);
450 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 6, 0), &arm926ejs
->d_far
);
452 DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
453 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
458 /* read-modify-write CP15 cache debug control register
459 * to disable I/D-cache linefills and force WT */
460 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl
);
461 cache_dbg_ctrl
|= 0x7;
462 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl
);
465 void arm926ejs_pre_restore_context(target_t
*target
)
467 armv4_5_common_t
*armv4_5
= target
->arch_info
;
468 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
469 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
470 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
472 /* restore i/d fault status and address register */
473 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 5, 0), arm926ejs
->d_fsr
);
474 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 1, 5, 0), arm926ejs
->i_fsr
);
475 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 6, 0), arm926ejs
->d_far
);
479 /* read-modify-write CP15 cache debug control register
480 * to reenable I/D-cache linefills and disable WT */
481 arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl
);
482 cache_dbg_ctrl
&= ~0x7;
483 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl
);
486 int arm926ejs_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm926ejs_common_t
**arm926ejs_p
)
488 armv4_5_common_t
*armv4_5
= target
->arch_info
;
489 arm7_9_common_t
*arm7_9
;
490 arm9tdmi_common_t
*arm9tdmi
;
491 arm926ejs_common_t
*arm926ejs
;
493 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
498 arm7_9
= armv4_5
->arch_info
;
499 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
504 arm9tdmi
= arm7_9
->arch_info
;
505 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
510 arm926ejs
= arm9tdmi
->arch_info
;
511 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
516 *armv4_5_p
= armv4_5
;
518 *arm9tdmi_p
= arm9tdmi
;
519 *arm926ejs_p
= arm926ejs
;
524 int arm926ejs_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
526 armv4_5_common_t
*armv4_5
= target
->arch_info
;
527 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
528 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
529 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
533 "disabled", "enabled"
536 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
538 ERROR("BUG: called for a non-ARMv4/5 target");
542 snprintf(buf
, buf_size
,
543 "target halted in %s state due to %s, current mode: %s\n"
544 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
545 "MMU: %s, D-Cache: %s, I-Cache: %s",
546 armv4_5_state_strings
[armv4_5
->core_state
],
547 target_debug_reason_strings
[target
->debug_reason
],
548 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
549 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
550 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
551 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
552 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
553 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
558 int arm926ejs_soft_reset_halt(struct target_s
*target
)
560 armv4_5_common_t
*armv4_5
= target
->arch_info
;
561 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
562 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
563 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
564 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
566 if (target
->state
== TARGET_RUNNING
)
568 target
->type
->halt(target
);
571 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
573 embeddedice_read_reg(dbg_stat
);
574 jtag_execute_queue();
577 target
->state
= TARGET_HALTED
;
579 /* SVC, ARM state, IRQ and FIQ disabled */
580 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
581 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
582 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
584 /* start fetching from 0x0 */
585 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
586 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
587 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
589 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
590 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
592 arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
593 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
594 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
595 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
597 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
602 int arm926ejs_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
605 armv4_5_common_t
*armv4_5
= target
->arch_info
;
606 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
607 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
608 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
610 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
613 /* If ICache is enabled, we have to invalidate affected ICache lines
614 * the DCache is forced to write-through, so we don't have to clean it here
616 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
620 /* invalidate ICache single entry with MVA */
621 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 1, 7, 5), address
);
625 /* invalidate ICache */
626 arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(0, 0, 7, 5), address
);
633 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
635 arm9tdmi_init_target(cmd_ctx
, target
);
647 int arm926ejs_init_arch_info(target_t
*target
, arm926ejs_common_t
*arm926ejs
, int chain_pos
, char *variant
)
649 arm9tdmi_common_t
*arm9tdmi
= &arm926ejs
->arm9tdmi_common
;
650 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
652 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
654 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
656 arm9tdmi
->arch_info
= arm926ejs
;
657 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
659 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
660 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
662 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
663 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
664 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
665 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
666 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
667 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
668 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
669 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
671 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
673 /* The ARM926EJ-S implements the ARMv5TE architecture which
674 * has the BKPT instruction, so we don't have to use a watchpoint comparator
676 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
677 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
679 arm7_9
->sw_bkpts_use_wp
= 0;
680 arm7_9
->sw_bkpts_enabled
= 1;
685 int arm926ejs_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
688 char *variant
= NULL
;
689 arm926ejs_common_t
*arm926ejs
= malloc(sizeof(arm926ejs_common_t
));
693 ERROR("'target arm926ejs' requires at least one additional argument");
697 chain_pos
= strtoul(args
[3], NULL
, 0);
702 DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
704 arm926ejs_init_arch_info(target
, arm926ejs
, chain_pos
, variant
);
709 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
)
712 command_t
*arm926ejs_cmd
;
715 retval
= arm9tdmi_register_commands(cmd_ctx
);
717 arm926ejs_cmd
= register_command(cmd_ctx
, NULL
, "arm926ejs", NULL
, COMMAND_ANY
, "arm926ejs specific commands");
719 register_command(cmd_ctx
, arm926ejs_cmd
, "cp15", arm926ejs_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
721 register_command(cmd_ctx
, arm926ejs_cmd
, "cache_info", arm926ejs_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
722 register_command(cmd_ctx
, arm926ejs_cmd
, "virt2phys", arm926ejs_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
724 register_command(cmd_ctx
, arm926ejs_cmd
, "mdw_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
725 register_command(cmd_ctx
, arm926ejs_cmd
, "mdh_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
726 register_command(cmd_ctx
, arm926ejs_cmd
, "mdb_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
728 register_command(cmd_ctx
, arm926ejs_cmd
, "mww_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
729 register_command(cmd_ctx
, arm926ejs_cmd
, "mwh_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
730 register_command(cmd_ctx
, arm926ejs_cmd
, "mwb_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
735 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
738 target_t
*target
= get_current_target(cmd_ctx
);
739 armv4_5_common_t
*armv4_5
;
740 arm7_9_common_t
*arm7_9
;
741 arm9tdmi_common_t
*arm9tdmi
;
742 arm926ejs_common_t
*arm926ejs
;
748 if ((argc
< 4) || (argc
> 5))
750 command_print(cmd_ctx
, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
754 opcode_1
= strtoul(args
[0], NULL
, 0);
755 opcode_2
= strtoul(args
[1], NULL
, 0);
756 CRn
= strtoul(args
[2], NULL
, 0);
757 CRm
= strtoul(args
[3], NULL
, 0);
759 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
761 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
765 if (target
->state
!= TARGET_HALTED
)
767 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
774 if ((retval
= arm926ejs_read_cp15(target
, ARM926EJS_CP15_ADDR(opcode_1
, opcode_2
, CRn
, CRm
), &value
)) != ERROR_OK
)
776 command_print(cmd_ctx
, "couldn't access register");
779 jtag_execute_queue();
781 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
785 u32 value
= strtoul(args
[4], NULL
, 0);
786 if ((retval
= arm926ejs_write_cp15(target
, ARM926EJS_CP15_ADDR(opcode_1
, opcode_2
, CRn
, CRm
), value
)) != ERROR_OK
)
788 command_print(cmd_ctx
, "couldn't access register");
791 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
797 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
799 target_t
*target
= get_current_target(cmd_ctx
);
800 armv4_5_common_t
*armv4_5
;
801 arm7_9_common_t
*arm7_9
;
802 arm9tdmi_common_t
*arm9tdmi
;
803 arm926ejs_common_t
*arm926ejs
;
805 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
807 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
811 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
814 int arm926ejs_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
816 target_t
*target
= get_current_target(cmd_ctx
);
817 armv4_5_common_t
*armv4_5
;
818 arm7_9_common_t
*arm7_9
;
819 arm9tdmi_common_t
*arm9tdmi
;
820 arm926ejs_common_t
*arm926ejs
;
821 arm_jtag_t
*jtag_info
;
823 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
825 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
829 jtag_info
= &arm7_9
->jtag_info
;
831 if (target
->state
!= TARGET_HALTED
)
833 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
837 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
840 int arm926ejs_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
842 target_t
*target
= get_current_target(cmd_ctx
);
843 armv4_5_common_t
*armv4_5
;
844 arm7_9_common_t
*arm7_9
;
845 arm9tdmi_common_t
*arm9tdmi
;
846 arm926ejs_common_t
*arm926ejs
;
847 arm_jtag_t
*jtag_info
;
849 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
851 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
855 jtag_info
= &arm7_9
->jtag_info
;
857 if (target
->state
!= TARGET_HALTED
)
859 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
863 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
866 int arm926ejs_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
868 target_t
*target
= get_current_target(cmd_ctx
);
869 armv4_5_common_t
*armv4_5
;
870 arm7_9_common_t
*arm7_9
;
871 arm9tdmi_common_t
*arm9tdmi
;
872 arm926ejs_common_t
*arm926ejs
;
873 arm_jtag_t
*jtag_info
;
875 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
877 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
881 jtag_info
= &arm7_9
->jtag_info
;
883 if (target
->state
!= TARGET_HALTED
)
885 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
889 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
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