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arm920t: memory writes were broken when MMU was disabled
[openocd.git] / src / target / arm920t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm920t.h"
25 #include "time_support.h"
26 #include "target_type.h"
27
28
29 #if 0
30 #define _DEBUG_INSTRUCTION_EXECUTION_
31 #endif
32
33 /* cli handling */
34 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
38 int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
39
40 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42
43 /* forward declarations */
44 int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
45 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
46 int arm920t_quit(void);
47
48 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
49
50 target_type_t arm920t_target =
51 {
52 .name = "arm920t",
53
54 .poll = arm7_9_poll,
55 .arch_state = arm920t_arch_state,
56
57 .target_request_data = arm7_9_target_request_data,
58
59 .halt = arm7_9_halt,
60 .resume = arm7_9_resume,
61 .step = arm7_9_step,
62
63 .assert_reset = arm7_9_assert_reset,
64 .deassert_reset = arm7_9_deassert_reset,
65 .soft_reset_halt = arm920t_soft_reset_halt,
66
67 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
68
69 .read_memory = arm920t_read_memory,
70 .write_memory = arm920t_write_memory,
71 .read_phys_memory = arm920t_read_phys_memory,
72 .write_phys_memory = arm920t_write_phys_memory,
73 .bulk_write_memory = arm7_9_bulk_write_memory,
74 .checksum_memory = arm7_9_checksum_memory,
75 .blank_check_memory = arm7_9_blank_check_memory,
76
77 .run_algorithm = armv4_5_run_algorithm,
78
79 .add_breakpoint = arm7_9_add_breakpoint,
80 .remove_breakpoint = arm7_9_remove_breakpoint,
81 .add_watchpoint = arm7_9_add_watchpoint,
82 .remove_watchpoint = arm7_9_remove_watchpoint,
83
84 .register_commands = arm920t_register_commands,
85 .target_create = arm920t_target_create,
86 .init_target = arm920t_init_target,
87 .examine = arm9tdmi_examine,
88 .quit = arm920t_quit
89 };
90
91 int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
92 {
93 armv4_5_common_t *armv4_5 = target->arch_info;
94 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
95 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
96 scan_field_t fields[4];
97 uint8_t access_type_buf = 1;
98 uint8_t reg_addr_buf = reg_addr & 0x3f;
99 uint8_t nr_w_buf = 0;
100
101 jtag_set_end_state(TAP_IDLE);
102 arm_jtag_scann(jtag_info, 0xf);
103 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
104
105 fields[0].tap = jtag_info->tap;
106 fields[0].num_bits = 1;
107 fields[0].out_value = &access_type_buf;
108 fields[0].in_value = NULL;
109
110 fields[1].tap = jtag_info->tap;
111 fields[1].num_bits = 32;
112 fields[1].out_value = NULL;
113 fields[1].in_value = NULL;
114
115 fields[2].tap = jtag_info->tap;
116 fields[2].num_bits = 6;
117 fields[2].out_value = &reg_addr_buf;
118 fields[2].in_value = NULL;
119
120 fields[3].tap = jtag_info->tap;
121 fields[3].num_bits = 1;
122 fields[3].out_value = &nr_w_buf;
123 fields[3].in_value = NULL;
124
125 jtag_add_dr_scan(4, fields, jtag_get_end_state());
126
127 fields[1].in_value = (uint8_t *)value;
128
129 jtag_add_dr_scan(4, fields, jtag_get_end_state());
130
131 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
132
133 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
134 jtag_execute_queue();
135 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
136 #endif
137
138 return ERROR_OK;
139 }
140
141 int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value)
142 {
143 armv4_5_common_t *armv4_5 = target->arch_info;
144 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
145 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
146 scan_field_t fields[4];
147 uint8_t access_type_buf = 1;
148 uint8_t reg_addr_buf = reg_addr & 0x3f;
149 uint8_t nr_w_buf = 1;
150 uint8_t value_buf[4];
151
152 buf_set_u32(value_buf, 0, 32, value);
153
154 jtag_set_end_state(TAP_IDLE);
155 arm_jtag_scann(jtag_info, 0xf);
156 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
157
158 fields[0].tap = jtag_info->tap;
159 fields[0].num_bits = 1;
160 fields[0].out_value = &access_type_buf;
161 fields[0].in_value = NULL;
162
163 fields[1].tap = jtag_info->tap;
164 fields[1].num_bits = 32;
165 fields[1].out_value = value_buf;
166 fields[1].in_value = NULL;
167
168 fields[2].tap = jtag_info->tap;
169 fields[2].num_bits = 6;
170 fields[2].out_value = &reg_addr_buf;
171 fields[2].in_value = NULL;
172
173 fields[3].tap = jtag_info->tap;
174 fields[3].num_bits = 1;
175 fields[3].out_value = &nr_w_buf;
176 fields[3].in_value = NULL;
177
178 jtag_add_dr_scan(4, fields, jtag_get_end_state());
179
180 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
181 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
182 #endif
183
184 return ERROR_OK;
185 }
186
187 int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode)
188 {
189 int retval;
190 armv4_5_common_t *armv4_5 = target->arch_info;
191 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
192 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
193 scan_field_t fields[4];
194 uint8_t access_type_buf = 0; /* interpreted access */
195 uint8_t reg_addr_buf = 0x0;
196 uint8_t nr_w_buf = 0;
197 uint8_t cp15_opcode_buf[4];
198
199 jtag_set_end_state(TAP_IDLE);
200 arm_jtag_scann(jtag_info, 0xf);
201 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
202
203 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
204
205 fields[0].tap = jtag_info->tap;
206 fields[0].num_bits = 1;
207 fields[0].out_value = &access_type_buf;
208 fields[0].in_value = NULL;
209
210 fields[1].tap = jtag_info->tap;
211 fields[1].num_bits = 32;
212 fields[1].out_value = cp15_opcode_buf;
213 fields[1].in_value = NULL;
214
215 fields[2].tap = jtag_info->tap;
216 fields[2].num_bits = 6;
217 fields[2].out_value = &reg_addr_buf;
218 fields[2].in_value = NULL;
219
220 fields[3].tap = jtag_info->tap;
221 fields[3].num_bits = 1;
222 fields[3].out_value = &nr_w_buf;
223 fields[3].in_value = NULL;
224
225 jtag_add_dr_scan(4, fields, jtag_get_end_state());
226
227 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
228 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
229 retval = arm7_9_execute_sys_speed(target);
230 if (retval != ERROR_OK)
231 return retval;
232
233 if ((retval = jtag_execute_queue()) != ERROR_OK)
234 {
235 LOG_ERROR("failed executing JTAG queue, exiting");
236 return retval;
237 }
238
239 return ERROR_OK;
240 }
241
242 int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value)
243 {
244 armv4_5_common_t *armv4_5 = target->arch_info;
245 uint32_t* regs_p[1];
246 uint32_t regs[2];
247 uint32_t cp15c15 = 0x0;
248
249 /* load address into R1 */
250 regs[1] = address;
251 arm9tdmi_write_core_regs(target, 0x2, regs);
252
253 /* read-modify-write CP15 test state register
254 * to enable interpreted access mode */
255 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
256 jtag_execute_queue();
257 cp15c15 |= 1; /* set interpret mode */
258 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
259
260 /* execute CP15 instruction and ARM load (reading from coprocessor) */
261 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
262
263 /* disable interpreted access mode */
264 cp15c15 &= ~1U; /* clear interpret mode */
265 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
266
267 /* retrieve value from R0 */
268 regs_p[0] = value;
269 arm9tdmi_read_core_regs(target, 0x1, regs_p);
270 jtag_execute_queue();
271
272 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
273 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
274 #endif
275
276 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
277 return ERROR_FAIL;
278
279 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
280 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
281
282 return ERROR_OK;
283 }
284
285 int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address)
286 {
287 uint32_t cp15c15 = 0x0;
288 armv4_5_common_t *armv4_5 = target->arch_info;
289 uint32_t regs[2];
290
291 /* load value, address into R0, R1 */
292 regs[0] = value;
293 regs[1] = address;
294 arm9tdmi_write_core_regs(target, 0x3, regs);
295
296 /* read-modify-write CP15 test state register
297 * to enable interpreted access mode */
298 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
299 jtag_execute_queue();
300 cp15c15 |= 1; /* set interpret mode */
301 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
302
303 /* execute CP15 instruction and ARM store (writing to coprocessor) */
304 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
305
306 /* disable interpreted access mode */
307 cp15c15 &= ~1U; /* set interpret mode */
308 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
309
310 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
311 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
312 #endif
313
314 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
315 return ERROR_FAIL;
316
317 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
318 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
319
320 return ERROR_OK;
321 }
322
323 uint32_t arm920t_get_ttb(target_t *target)
324 {
325 int retval;
326 uint32_t ttb = 0x0;
327
328 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
329 return retval;
330
331 return ttb;
332 }
333
334 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
335 {
336 uint32_t cp15_control;
337
338 /* read cp15 control register */
339 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
340 jtag_execute_queue();
341
342 if (mmu)
343 cp15_control &= ~0x1U;
344
345 if (d_u_cache)
346 cp15_control &= ~0x4U;
347
348 if (i_cache)
349 cp15_control &= ~0x1000U;
350
351 arm920t_write_cp15_physical(target, 0x2, cp15_control);
352 }
353
354 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
355 {
356 uint32_t cp15_control;
357
358 /* read cp15 control register */
359 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
360 jtag_execute_queue();
361
362 if (mmu)
363 cp15_control |= 0x1U;
364
365 if (d_u_cache)
366 cp15_control |= 0x4U;
367
368 if (i_cache)
369 cp15_control |= 0x1000U;
370
371 arm920t_write_cp15_physical(target, 0x2, cp15_control);
372 }
373
374 void arm920t_post_debug_entry(target_t *target)
375 {
376 uint32_t cp15c15;
377 armv4_5_common_t *armv4_5 = target->arch_info;
378 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
379 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
380 arm920t_common_t *arm920t = arm9tdmi->arch_info;
381
382 /* examine cp15 control reg */
383 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
384 jtag_execute_queue();
385 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
386
387 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
388 {
389 uint32_t cache_type_reg;
390 /* identify caches */
391 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
392 jtag_execute_queue();
393 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
394 }
395
396 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
397 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
398 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
399
400 /* save i/d fault status and address register */
401 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
402 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
403 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
404 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
405
406 LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
407 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
408
409 if (arm920t->preserve_cache)
410 {
411 /* read-modify-write CP15 test state register
412 * to disable I/D-cache linefills */
413 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
414 jtag_execute_queue();
415 cp15c15 |= 0x600;
416 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
417 }
418 }
419
420 void arm920t_pre_restore_context(target_t *target)
421 {
422 uint32_t cp15c15;
423 armv4_5_common_t *armv4_5 = target->arch_info;
424 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
425 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
426 arm920t_common_t *arm920t = arm9tdmi->arch_info;
427
428 /* restore i/d fault status and address register */
429 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
430 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
431 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
432 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
433
434 /* read-modify-write CP15 test state register
435 * to reenable I/D-cache linefills */
436 if (arm920t->preserve_cache)
437 {
438 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
439 jtag_execute_queue();
440 cp15c15 &= ~0x600U;
441 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
442 }
443 }
444
445 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
446 {
447 armv4_5_common_t *armv4_5 = target->arch_info;
448 arm7_9_common_t *arm7_9;
449 arm9tdmi_common_t *arm9tdmi;
450 arm920t_common_t *arm920t;
451
452 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
453 {
454 return -1;
455 }
456
457 arm7_9 = armv4_5->arch_info;
458 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
459 {
460 return -1;
461 }
462
463 arm9tdmi = arm7_9->arch_info;
464 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
465 {
466 return -1;
467 }
468
469 arm920t = arm9tdmi->arch_info;
470 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
471 {
472 return -1;
473 }
474
475 *armv4_5_p = armv4_5;
476 *arm7_9_p = arm7_9;
477 *arm9tdmi_p = arm9tdmi;
478 *arm920t_p = arm920t;
479
480 return ERROR_OK;
481 }
482
483 int arm920t_arch_state(struct target_s *target)
484 {
485 armv4_5_common_t *armv4_5 = target->arch_info;
486 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
487 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
488 arm920t_common_t *arm920t = arm9tdmi->arch_info;
489
490 char *state[] =
491 {
492 "disabled", "enabled"
493 };
494
495 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
496 {
497 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
498 exit(-1);
499 }
500
501 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
502 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
503 "MMU: %s, D-Cache: %s, I-Cache: %s",
504 armv4_5_state_strings[armv4_5->core_state],
505 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
506 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
507 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
508 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
509 state[arm920t->armv4_5_mmu.mmu_enabled],
510 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
511 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
512
513 return ERROR_OK;
514 }
515
516 int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
517 {
518 int retval;
519
520 retval = arm7_9_read_memory(target, address, size, count, buffer);
521
522 return retval;
523 }
524
525
526 int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
527 {
528 armv4_5_common_t *armv4_5 = target->arch_info;
529 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
530 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
531 arm920t_common_t *arm920t = arm9tdmi->arch_info;
532
533 return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
534 }
535
536 int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
537 {
538 armv4_5_common_t *armv4_5 = target->arch_info;
539 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
540 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
541 arm920t_common_t *arm920t = arm9tdmi->arch_info;
542
543 return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
544 }
545
546
547 int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
548 {
549 int retval;
550 armv4_5_common_t *armv4_5 = target->arch_info;
551 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
552 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
553 arm920t_common_t *arm920t = arm9tdmi->arch_info;
554
555 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
556 return retval;
557
558 /* This fn is used to write breakpoints, so we need to make sure that the
559 * datacache is flushed and the instruction cache is invalidated */
560 if (((size == 4) || (size == 2)) && (count == 1))
561 {
562 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
563 {
564 LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
565 /* MCR p15,0,Rd,c7,c10,2 */
566 retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
567 if (retval != ERROR_OK)
568 return retval;
569 }
570
571 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
572 {
573 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
574 retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
575 if (retval != ERROR_OK)
576 return retval;
577 }
578 }
579
580 return retval;
581 }
582
583 int arm920t_soft_reset_halt(struct target_s *target)
584 {
585 int retval = ERROR_OK;
586 armv4_5_common_t *armv4_5 = target->arch_info;
587 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
588 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
589 arm920t_common_t *arm920t = arm9tdmi->arch_info;
590 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
591
592 if ((retval = target_halt(target)) != ERROR_OK)
593 {
594 return retval;
595 }
596
597 long long then = timeval_ms();
598 int timeout;
599 while (!(timeout = ((timeval_ms()-then) > 1000)))
600 {
601 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
602 {
603 embeddedice_read_reg(dbg_stat);
604 if ((retval = jtag_execute_queue()) != ERROR_OK)
605 {
606 return retval;
607 }
608 } else
609 {
610 break;
611 }
612 if (debug_level >= 3)
613 {
614 /* do not eat all CPU, time out after 1 se*/
615 alive_sleep(100);
616 } else
617 {
618 keep_alive();
619 }
620 }
621 if (timeout)
622 {
623 LOG_ERROR("Failed to halt CPU after 1 sec");
624 return ERROR_TARGET_TIMEOUT;
625 }
626
627 target->state = TARGET_HALTED;
628
629 /* SVC, ARM state, IRQ and FIQ disabled */
630 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
631 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
632 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
633
634 /* start fetching from 0x0 */
635 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
636 armv4_5->core_cache->reg_list[15].dirty = 1;
637 armv4_5->core_cache->reg_list[15].valid = 1;
638
639 armv4_5->core_mode = ARMV4_5_MODE_SVC;
640 armv4_5->core_state = ARMV4_5_STATE_ARM;
641
642 arm920t_disable_mmu_caches(target, 1, 1, 1);
643 arm920t->armv4_5_mmu.mmu_enabled = 0;
644 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
645 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
646
647 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
648 {
649 return retval;
650 }
651
652 return ERROR_OK;
653 }
654
655 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
656 {
657 arm9tdmi_init_target(cmd_ctx, target);
658
659 return ERROR_OK;
660 }
661
662 int arm920t_quit(void)
663 {
664 return ERROR_OK;
665 }
666
667 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
668 {
669 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
670 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
671
672 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
673 */
674 arm9tdmi_init_arch_info(target, arm9tdmi, tap);
675
676 arm9tdmi->arch_info = arm920t;
677 arm920t->common_magic = ARM920T_COMMON_MAGIC;
678
679 arm7_9->post_debug_entry = arm920t_post_debug_entry;
680 arm7_9->pre_restore_context = arm920t_pre_restore_context;
681
682 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
683 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
684 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
685 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
686 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
687 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
688 arm920t->armv4_5_mmu.has_tiny_pages = 1;
689 arm920t->armv4_5_mmu.mmu_enabled = 0;
690
691 /* disabling linefills leads to lockups, so keep them enabled for now
692 * this doesn't affect correctness, but might affect timing issues, if
693 * important data is evicted from the cache during the debug session
694 * */
695 arm920t->preserve_cache = 0;
696
697 /* override hw single-step capability from ARM9TDMI */
698 arm7_9->has_single_step = 1;
699
700 return ERROR_OK;
701 }
702
703 int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
704 {
705 arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
706
707 arm920t_init_arch_info(target, arm920t, target->tap);
708
709 return ERROR_OK;
710 }
711
712 int arm920t_register_commands(struct command_context_s *cmd_ctx)
713 {
714 int retval;
715 command_t *arm920t_cmd;
716
717
718 retval = arm9tdmi_register_commands(cmd_ctx);
719
720 arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
721
722 register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
723 register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
724 register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
725
726 register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
727 register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
728
729 return retval;
730 }
731
732 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
733 {
734 int retval = ERROR_OK;
735 target_t *target = get_current_target(cmd_ctx);
736 armv4_5_common_t *armv4_5;
737 arm7_9_common_t *arm7_9;
738 arm9tdmi_common_t *arm9tdmi;
739 arm920t_common_t *arm920t;
740 arm_jtag_t *jtag_info;
741 uint32_t cp15c15;
742 uint32_t cp15_ctrl, cp15_ctrl_saved;
743 uint32_t regs[16];
744 uint32_t *regs_p[16];
745 uint32_t C15_C_D_Ind, C15_C_I_Ind;
746 int i;
747 FILE *output;
748 arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
749 int segment, index;
750
751 if (argc != 1)
752 {
753 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
754 return ERROR_OK;
755 }
756
757 if ((output = fopen(args[0], "w")) == NULL)
758 {
759 LOG_DEBUG("error opening cache content file");
760 return ERROR_OK;
761 }
762
763 for (i = 0; i < 16; i++)
764 regs_p[i] = &regs[i];
765
766 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
767 {
768 command_print(cmd_ctx, "current target isn't an ARM920t target");
769 return ERROR_OK;
770 }
771
772 jtag_info = &arm7_9->jtag_info;
773
774 /* disable MMU and Caches */
775 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
776 if ((retval = jtag_execute_queue()) != ERROR_OK)
777 {
778 return retval;
779 }
780 cp15_ctrl_saved = cp15_ctrl;
781 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
782 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
783
784 /* read CP15 test state register */
785 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
786 jtag_execute_queue();
787
788 /* read DCache content */
789 fprintf(output, "DCache:\n");
790
791 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
792 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
793 {
794 fprintf(output, "\nsegment: %i\n----------", segment);
795
796 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
797 regs[0] = 0x0 | (segment << 5);
798 arm9tdmi_write_core_regs(target, 0x1, regs);
799
800 /* set interpret mode */
801 cp15c15 |= 0x1;
802 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
803
804 /* D CAM Read, loads current victim into C15.C.D.Ind */
805 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
806
807 /* read current victim */
808 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
809
810 /* clear interpret mode */
811 cp15c15 &= ~0x1;
812 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
813
814 for (index = 0; index < 64; index++)
815 {
816 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
817 regs[0] = 0x0 | (segment << 5) | (index << 26);
818 arm9tdmi_write_core_regs(target, 0x1, regs);
819
820 /* set interpret mode */
821 cp15c15 |= 0x1;
822 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
823
824 /* Write DCache victim */
825 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
826
827 /* Read D RAM */
828 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
829
830 /* Read D CAM */
831 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
832
833 /* clear interpret mode */
834 cp15c15 &= ~0x1;
835 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
836
837 /* read D RAM and CAM content */
838 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
839 if ((retval = jtag_execute_queue()) != ERROR_OK)
840 {
841 return retval;
842 }
843
844 d_cache[segment][index].cam = regs[9];
845
846 /* mask LFSR[6] */
847 regs[9] &= 0xfffffffe;
848 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
849
850 for (i = 1; i < 9; i++)
851 {
852 d_cache[segment][index].data[i] = regs[i];
853 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
854 }
855
856 }
857
858 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
859 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
860 arm9tdmi_write_core_regs(target, 0x1, regs);
861
862 /* set interpret mode */
863 cp15c15 |= 0x1;
864 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
865
866 /* Write DCache victim */
867 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
868
869 /* clear interpret mode */
870 cp15c15 &= ~0x1;
871 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
872 }
873
874 /* read ICache content */
875 fprintf(output, "ICache:\n");
876
877 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
878 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
879 {
880 fprintf(output, "segment: %i\n----------", segment);
881
882 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
883 regs[0] = 0x0 | (segment << 5);
884 arm9tdmi_write_core_regs(target, 0x1, regs);
885
886 /* set interpret mode */
887 cp15c15 |= 0x1;
888 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
889
890 /* I CAM Read, loads current victim into C15.C.I.Ind */
891 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
892
893 /* read current victim */
894 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
895
896 /* clear interpret mode */
897 cp15c15 &= ~0x1;
898 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
899
900 for (index = 0; index < 64; index++)
901 {
902 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
903 regs[0] = 0x0 | (segment << 5) | (index << 26);
904 arm9tdmi_write_core_regs(target, 0x1, regs);
905
906 /* set interpret mode */
907 cp15c15 |= 0x1;
908 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
909
910 /* Write ICache victim */
911 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
912
913 /* Read I RAM */
914 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
915
916 /* Read I CAM */
917 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
918
919 /* clear interpret mode */
920 cp15c15 &= ~0x1;
921 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
922
923 /* read I RAM and CAM content */
924 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
925 if ((retval = jtag_execute_queue()) != ERROR_OK)
926 {
927 return retval;
928 }
929
930 i_cache[segment][index].cam = regs[9];
931
932 /* mask LFSR[6] */
933 regs[9] &= 0xfffffffe;
934 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
935
936 for (i = 1; i < 9; i++)
937 {
938 i_cache[segment][index].data[i] = regs[i];
939 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
940 }
941 }
942
943 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
944 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
945 arm9tdmi_write_core_regs(target, 0x1, regs);
946
947 /* set interpret mode */
948 cp15c15 |= 0x1;
949 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
950
951 /* Write ICache victim */
952 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
953
954 /* clear interpret mode */
955 cp15c15 &= ~0x1;
956 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
957 }
958
959 /* restore CP15 MMU and Cache settings */
960 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
961
962 command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
963
964 fclose(output);
965
966 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
967 return ERROR_FAIL;
968
969 /* mark registers dirty. */
970 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
971 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
972 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
973 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
974 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
975 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
976 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
977 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
978 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
979 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
980
981 return ERROR_OK;
982 }
983
984 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
985 {
986 int retval = ERROR_OK;
987 target_t *target = get_current_target(cmd_ctx);
988 armv4_5_common_t *armv4_5;
989 arm7_9_common_t *arm7_9;
990 arm9tdmi_common_t *arm9tdmi;
991 arm920t_common_t *arm920t;
992 arm_jtag_t *jtag_info;
993 uint32_t cp15c15;
994 uint32_t cp15_ctrl, cp15_ctrl_saved;
995 uint32_t regs[16];
996 uint32_t *regs_p[16];
997 int i;
998 FILE *output;
999 uint32_t Dlockdown, Ilockdown;
1000 arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1001 int victim;
1002
1003 if (argc != 1)
1004 {
1005 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1006 return ERROR_OK;
1007 }
1008
1009 if ((output = fopen(args[0], "w")) == NULL)
1010 {
1011 LOG_DEBUG("error opening mmu content file");
1012 return ERROR_OK;
1013 }
1014
1015 for (i = 0; i < 16; i++)
1016 regs_p[i] = &regs[i];
1017
1018 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1019 {
1020 command_print(cmd_ctx, "current target isn't an ARM920t target");
1021 return ERROR_OK;
1022 }
1023
1024 jtag_info = &arm7_9->jtag_info;
1025
1026 /* disable MMU and Caches */
1027 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1028 if ((retval = jtag_execute_queue()) != ERROR_OK)
1029 {
1030 return retval;
1031 }
1032 cp15_ctrl_saved = cp15_ctrl;
1033 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1034 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1035
1036 /* read CP15 test state register */
1037 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1038 if ((retval = jtag_execute_queue()) != ERROR_OK)
1039 {
1040 return retval;
1041 }
1042
1043 /* prepare reading D TLB content
1044 * */
1045
1046 /* set interpret mode */
1047 cp15c15 |= 0x1;
1048 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1049
1050 /* Read D TLB lockdown */
1051 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1052
1053 /* clear interpret mode */
1054 cp15c15 &= ~0x1;
1055 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1056
1057 /* read D TLB lockdown stored to r1 */
1058 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1059 if ((retval = jtag_execute_queue()) != ERROR_OK)
1060 {
1061 return retval;
1062 }
1063 Dlockdown = regs[1];
1064
1065 for (victim = 0; victim < 64; victim += 8)
1066 {
1067 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1068 * base remains unchanged, victim goes through entries 0 to 63 */
1069 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1070 arm9tdmi_write_core_regs(target, 0x2, regs);
1071
1072 /* set interpret mode */
1073 cp15c15 |= 0x1;
1074 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1075
1076 /* Write D TLB lockdown */
1077 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1078
1079 /* Read D TLB CAM */
1080 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1081
1082 /* clear interpret mode */
1083 cp15c15 &= ~0x1;
1084 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1085
1086 /* read D TLB CAM content stored to r2-r9 */
1087 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1088 if ((retval = jtag_execute_queue()) != ERROR_OK)
1089 {
1090 return retval;
1091 }
1092
1093 for (i = 0; i < 8; i++)
1094 d_tlb[victim + i].cam = regs[i + 2];
1095 }
1096
1097 for (victim = 0; victim < 64; victim++)
1098 {
1099 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1100 * base remains unchanged, victim goes through entries 0 to 63 */
1101 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1102 arm9tdmi_write_core_regs(target, 0x2, regs);
1103
1104 /* set interpret mode */
1105 cp15c15 |= 0x1;
1106 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1107
1108 /* Write D TLB lockdown */
1109 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1110
1111 /* Read D TLB RAM1 */
1112 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1113
1114 /* Read D TLB RAM2 */
1115 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1116
1117 /* clear interpret mode */
1118 cp15c15 &= ~0x1;
1119 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1120
1121 /* read D TLB RAM content stored to r2 and r3 */
1122 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1123 if ((retval = jtag_execute_queue()) != ERROR_OK)
1124 {
1125 return retval;
1126 }
1127
1128 d_tlb[victim].ram1 = regs[2];
1129 d_tlb[victim].ram2 = regs[3];
1130 }
1131
1132 /* restore D TLB lockdown */
1133 regs[1] = Dlockdown;
1134 arm9tdmi_write_core_regs(target, 0x2, regs);
1135
1136 /* Write D TLB lockdown */
1137 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1138
1139 /* prepare reading I TLB content
1140 * */
1141
1142 /* set interpret mode */
1143 cp15c15 |= 0x1;
1144 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1145
1146 /* Read I TLB lockdown */
1147 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1148
1149 /* clear interpret mode */
1150 cp15c15 &= ~0x1;
1151 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1152
1153 /* read I TLB lockdown stored to r1 */
1154 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1155 if ((retval = jtag_execute_queue()) != ERROR_OK)
1156 {
1157 return retval;
1158 }
1159 Ilockdown = regs[1];
1160
1161 for (victim = 0; victim < 64; victim += 8)
1162 {
1163 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1164 * base remains unchanged, victim goes through entries 0 to 63 */
1165 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1166 arm9tdmi_write_core_regs(target, 0x2, regs);
1167
1168 /* set interpret mode */
1169 cp15c15 |= 0x1;
1170 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1171
1172 /* Write I TLB lockdown */
1173 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1174
1175 /* Read I TLB CAM */
1176 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1177
1178 /* clear interpret mode */
1179 cp15c15 &= ~0x1;
1180 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1181
1182 /* read I TLB CAM content stored to r2-r9 */
1183 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1184 if ((retval = jtag_execute_queue()) != ERROR_OK)
1185 {
1186 return retval;
1187 }
1188
1189 for (i = 0; i < 8; i++)
1190 i_tlb[i + victim].cam = regs[i + 2];
1191 }
1192
1193 for (victim = 0; victim < 64; victim++)
1194 {
1195 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1196 * base remains unchanged, victim goes through entries 0 to 63 */
1197 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1198 arm9tdmi_write_core_regs(target, 0x2, regs);
1199
1200 /* set interpret mode */
1201 cp15c15 |= 0x1;
1202 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1203
1204 /* Write I TLB lockdown */
1205 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1206
1207 /* Read I TLB RAM1 */
1208 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1209
1210 /* Read I TLB RAM2 */
1211 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1212
1213 /* clear interpret mode */
1214 cp15c15 &= ~0x1;
1215 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1216
1217 /* read I TLB RAM content stored to r2 and r3 */
1218 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1219 if ((retval = jtag_execute_queue()) != ERROR_OK)
1220 {
1221 return retval;
1222 }
1223
1224 i_tlb[victim].ram1 = regs[2];
1225 i_tlb[victim].ram2 = regs[3];
1226 }
1227
1228 /* restore I TLB lockdown */
1229 regs[1] = Ilockdown;
1230 arm9tdmi_write_core_regs(target, 0x2, regs);
1231
1232 /* Write I TLB lockdown */
1233 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1234
1235 /* restore CP15 MMU and Cache settings */
1236 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1237
1238 /* output data to file */
1239 fprintf(output, "D TLB content:\n");
1240 for (i = 0; i < 64; i++)
1241 {
1242 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1243 }
1244
1245 fprintf(output, "\n\nI TLB content:\n");
1246 for (i = 0; i < 64; i++)
1247 {
1248 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1249 }
1250
1251 command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1252
1253 fclose(output);
1254
1255 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1256 return ERROR_FAIL;
1257
1258 /* mark registers dirty */
1259 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1260 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1261 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1262 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1263 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1264 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1265 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1266 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1267 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1268 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1269
1270 return ERROR_OK;
1271 }
1272 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1273 {
1274 int retval;
1275 target_t *target = get_current_target(cmd_ctx);
1276 armv4_5_common_t *armv4_5;
1277 arm7_9_common_t *arm7_9;
1278 arm9tdmi_common_t *arm9tdmi;
1279 arm920t_common_t *arm920t;
1280 arm_jtag_t *jtag_info;
1281
1282 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1283 {
1284 command_print(cmd_ctx, "current target isn't an ARM920t target");
1285 return ERROR_OK;
1286 }
1287
1288 jtag_info = &arm7_9->jtag_info;
1289
1290 if (target->state != TARGET_HALTED)
1291 {
1292 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1293 return ERROR_OK;
1294 }
1295
1296 /* one or more argument, access a single register (write if second argument is given */
1297 if (argc >= 1)
1298 {
1299 int address = strtoul(args[0], NULL, 0);
1300
1301 if (argc == 1)
1302 {
1303 uint32_t value;
1304 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1305 {
1306 command_print(cmd_ctx, "couldn't access reg %i", address);
1307 return ERROR_OK;
1308 }
1309 if ((retval = jtag_execute_queue()) != ERROR_OK)
1310 {
1311 return retval;
1312 }
1313
1314 command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
1315 }
1316 else if (argc == 2)
1317 {
1318 uint32_t value = strtoul(args[1], NULL, 0);
1319 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1320 {
1321 command_print(cmd_ctx, "couldn't access reg %i", address);
1322 return ERROR_OK;
1323 }
1324 command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
1325 }
1326 }
1327
1328 return ERROR_OK;
1329 }
1330
1331 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1332 {
1333 int retval;
1334 target_t *target = get_current_target(cmd_ctx);
1335 armv4_5_common_t *armv4_5;
1336 arm7_9_common_t *arm7_9;
1337 arm9tdmi_common_t *arm9tdmi;
1338 arm920t_common_t *arm920t;
1339 arm_jtag_t *jtag_info;
1340
1341 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1342 {
1343 command_print(cmd_ctx, "current target isn't an ARM920t target");
1344 return ERROR_OK;
1345 }
1346
1347 jtag_info = &arm7_9->jtag_info;
1348
1349 if (target->state != TARGET_HALTED)
1350 {
1351 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1352 return ERROR_OK;
1353 }
1354
1355 /* one or more argument, access a single register (write if second argument is given */
1356 if (argc >= 1)
1357 {
1358 uint32_t opcode = strtoul(args[0], NULL, 0);
1359
1360 if (argc == 1)
1361 {
1362 uint32_t value;
1363 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1364 {
1365 command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
1366 return ERROR_OK;
1367 }
1368
1369 command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1370 }
1371 else if (argc == 2)
1372 {
1373 uint32_t value = strtoul(args[1], NULL, 0);
1374 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1375 {
1376 command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
1377 return ERROR_OK;
1378 }
1379 command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1380 }
1381 else if (argc == 3)
1382 {
1383 uint32_t value = strtoul(args[1], NULL, 0);
1384 uint32_t address = strtoul(args[2], NULL, 0);
1385 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1386 {
1387 command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
1388 return ERROR_OK;
1389 }
1390 command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
1391 }
1392 }
1393 else
1394 {
1395 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1396 }
1397
1398 return ERROR_OK;
1399 }
1400
1401 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1402 {
1403 target_t *target = get_current_target(cmd_ctx);
1404 armv4_5_common_t *armv4_5;
1405 arm7_9_common_t *arm7_9;
1406 arm9tdmi_common_t *arm9tdmi;
1407 arm920t_common_t *arm920t;
1408
1409 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1410 {
1411 command_print(cmd_ctx, "current target isn't an ARM920t target");
1412 return ERROR_OK;
1413 }
1414
1415 return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1416 }
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