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retire obsolete mXY_phys commands. Handled by generic memory read/modify commands...
[openocd.git] / src / target / arm920t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm920t.h"
25 #include "time_support.h"
26 #include "target_type.h"
27
28
29 #if 0
30 #define _DEBUG_INSTRUCTION_EXECUTION_
31 #endif
32
33 /* cli handling */
34 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
38 int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
39
40 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42
43 /* forward declarations */
44 int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
45 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
46 int arm920t_quit(void);
47
48 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
49
50 target_type_t arm920t_target =
51 {
52 .name = "arm920t",
53
54 .poll = arm7_9_poll,
55 .arch_state = arm920t_arch_state,
56
57 .target_request_data = arm7_9_target_request_data,
58
59 .halt = arm7_9_halt,
60 .resume = arm7_9_resume,
61 .step = arm7_9_step,
62
63 .assert_reset = arm7_9_assert_reset,
64 .deassert_reset = arm7_9_deassert_reset,
65 .soft_reset_halt = arm920t_soft_reset_halt,
66
67 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
68
69 .read_memory = arm920t_read_memory,
70 .write_memory = arm920t_write_memory,
71 .read_phys_memory = arm920t_read_phys_memory,
72 .write_phys_memory = arm920t_write_phys_memory,
73 .bulk_write_memory = arm7_9_bulk_write_memory,
74 .checksum_memory = arm7_9_checksum_memory,
75 .blank_check_memory = arm7_9_blank_check_memory,
76
77 .run_algorithm = armv4_5_run_algorithm,
78
79 .add_breakpoint = arm7_9_add_breakpoint,
80 .remove_breakpoint = arm7_9_remove_breakpoint,
81 .add_watchpoint = arm7_9_add_watchpoint,
82 .remove_watchpoint = arm7_9_remove_watchpoint,
83
84 .register_commands = arm920t_register_commands,
85 .target_create = arm920t_target_create,
86 .init_target = arm920t_init_target,
87 .examine = arm9tdmi_examine,
88 .quit = arm920t_quit
89 };
90
91 int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value)
92 {
93 armv4_5_common_t *armv4_5 = target->arch_info;
94 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
95 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
96 scan_field_t fields[4];
97 uint8_t access_type_buf = 1;
98 uint8_t reg_addr_buf = reg_addr & 0x3f;
99 uint8_t nr_w_buf = 0;
100
101 jtag_set_end_state(TAP_IDLE);
102 arm_jtag_scann(jtag_info, 0xf);
103 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
104
105 fields[0].tap = jtag_info->tap;
106 fields[0].num_bits = 1;
107 fields[0].out_value = &access_type_buf;
108 fields[0].in_value = NULL;
109
110 fields[1].tap = jtag_info->tap;
111 fields[1].num_bits = 32;
112 fields[1].out_value = NULL;
113 fields[1].in_value = NULL;
114
115 fields[2].tap = jtag_info->tap;
116 fields[2].num_bits = 6;
117 fields[2].out_value = &reg_addr_buf;
118 fields[2].in_value = NULL;
119
120 fields[3].tap = jtag_info->tap;
121 fields[3].num_bits = 1;
122 fields[3].out_value = &nr_w_buf;
123 fields[3].in_value = NULL;
124
125 jtag_add_dr_scan(4, fields, jtag_get_end_state());
126
127 fields[1].in_value = (uint8_t *)value;
128
129 jtag_add_dr_scan(4, fields, jtag_get_end_state());
130
131 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
132
133 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
134 jtag_execute_queue();
135 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
136 #endif
137
138 return ERROR_OK;
139 }
140
141 int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value)
142 {
143 armv4_5_common_t *armv4_5 = target->arch_info;
144 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
145 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
146 scan_field_t fields[4];
147 uint8_t access_type_buf = 1;
148 uint8_t reg_addr_buf = reg_addr & 0x3f;
149 uint8_t nr_w_buf = 1;
150 uint8_t value_buf[4];
151
152 buf_set_u32(value_buf, 0, 32, value);
153
154 jtag_set_end_state(TAP_IDLE);
155 arm_jtag_scann(jtag_info, 0xf);
156 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
157
158 fields[0].tap = jtag_info->tap;
159 fields[0].num_bits = 1;
160 fields[0].out_value = &access_type_buf;
161 fields[0].in_value = NULL;
162
163 fields[1].tap = jtag_info->tap;
164 fields[1].num_bits = 32;
165 fields[1].out_value = value_buf;
166 fields[1].in_value = NULL;
167
168 fields[2].tap = jtag_info->tap;
169 fields[2].num_bits = 6;
170 fields[2].out_value = &reg_addr_buf;
171 fields[2].in_value = NULL;
172
173 fields[3].tap = jtag_info->tap;
174 fields[3].num_bits = 1;
175 fields[3].out_value = &nr_w_buf;
176 fields[3].in_value = NULL;
177
178 jtag_add_dr_scan(4, fields, jtag_get_end_state());
179
180 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
181 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
182 #endif
183
184 return ERROR_OK;
185 }
186
187 int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode)
188 {
189 int retval;
190 armv4_5_common_t *armv4_5 = target->arch_info;
191 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
192 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
193 scan_field_t fields[4];
194 uint8_t access_type_buf = 0; /* interpreted access */
195 uint8_t reg_addr_buf = 0x0;
196 uint8_t nr_w_buf = 0;
197 uint8_t cp15_opcode_buf[4];
198
199 jtag_set_end_state(TAP_IDLE);
200 arm_jtag_scann(jtag_info, 0xf);
201 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
202
203 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
204
205 fields[0].tap = jtag_info->tap;
206 fields[0].num_bits = 1;
207 fields[0].out_value = &access_type_buf;
208 fields[0].in_value = NULL;
209
210 fields[1].tap = jtag_info->tap;
211 fields[1].num_bits = 32;
212 fields[1].out_value = cp15_opcode_buf;
213 fields[1].in_value = NULL;
214
215 fields[2].tap = jtag_info->tap;
216 fields[2].num_bits = 6;
217 fields[2].out_value = &reg_addr_buf;
218 fields[2].in_value = NULL;
219
220 fields[3].tap = jtag_info->tap;
221 fields[3].num_bits = 1;
222 fields[3].out_value = &nr_w_buf;
223 fields[3].in_value = NULL;
224
225 jtag_add_dr_scan(4, fields, jtag_get_end_state());
226
227 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
228 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
229 retval = arm7_9_execute_sys_speed(target);
230 if (retval != ERROR_OK)
231 return retval;
232
233 if ((retval = jtag_execute_queue()) != ERROR_OK)
234 {
235 LOG_ERROR("failed executing JTAG queue, exiting");
236 return retval;
237 }
238
239 return ERROR_OK;
240 }
241
242 int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value)
243 {
244 armv4_5_common_t *armv4_5 = target->arch_info;
245 uint32_t* regs_p[1];
246 uint32_t regs[2];
247 uint32_t cp15c15 = 0x0;
248
249 /* load address into R1 */
250 regs[1] = address;
251 arm9tdmi_write_core_regs(target, 0x2, regs);
252
253 /* read-modify-write CP15 test state register
254 * to enable interpreted access mode */
255 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
256 jtag_execute_queue();
257 cp15c15 |= 1; /* set interpret mode */
258 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
259
260 /* execute CP15 instruction and ARM load (reading from coprocessor) */
261 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
262
263 /* disable interpreted access mode */
264 cp15c15 &= ~1U; /* clear interpret mode */
265 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
266
267 /* retrieve value from R0 */
268 regs_p[0] = value;
269 arm9tdmi_read_core_regs(target, 0x1, regs_p);
270 jtag_execute_queue();
271
272 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
273 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
274 #endif
275
276 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
277 return ERROR_FAIL;
278
279 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
280 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
281
282 return ERROR_OK;
283 }
284
285 int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address)
286 {
287 uint32_t cp15c15 = 0x0;
288 armv4_5_common_t *armv4_5 = target->arch_info;
289 uint32_t regs[2];
290
291 /* load value, address into R0, R1 */
292 regs[0] = value;
293 regs[1] = address;
294 arm9tdmi_write_core_regs(target, 0x3, regs);
295
296 /* read-modify-write CP15 test state register
297 * to enable interpreted access mode */
298 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
299 jtag_execute_queue();
300 cp15c15 |= 1; /* set interpret mode */
301 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
302
303 /* execute CP15 instruction and ARM store (writing to coprocessor) */
304 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
305
306 /* disable interpreted access mode */
307 cp15c15 &= ~1U; /* set interpret mode */
308 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
309
310 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
311 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
312 #endif
313
314 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
315 return ERROR_FAIL;
316
317 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
318 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
319
320 return ERROR_OK;
321 }
322
323 uint32_t arm920t_get_ttb(target_t *target)
324 {
325 int retval;
326 uint32_t ttb = 0x0;
327
328 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
329 return retval;
330
331 return ttb;
332 }
333
334 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
335 {
336 uint32_t cp15_control;
337
338 /* read cp15 control register */
339 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
340 jtag_execute_queue();
341
342 if (mmu)
343 cp15_control &= ~0x1U;
344
345 if (d_u_cache)
346 cp15_control &= ~0x4U;
347
348 if (i_cache)
349 cp15_control &= ~0x1000U;
350
351 arm920t_write_cp15_physical(target, 0x2, cp15_control);
352 }
353
354 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
355 {
356 uint32_t cp15_control;
357
358 /* read cp15 control register */
359 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
360 jtag_execute_queue();
361
362 if (mmu)
363 cp15_control |= 0x1U;
364
365 if (d_u_cache)
366 cp15_control |= 0x4U;
367
368 if (i_cache)
369 cp15_control |= 0x1000U;
370
371 arm920t_write_cp15_physical(target, 0x2, cp15_control);
372 }
373
374 void arm920t_post_debug_entry(target_t *target)
375 {
376 uint32_t cp15c15;
377 armv4_5_common_t *armv4_5 = target->arch_info;
378 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
379 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
380 arm920t_common_t *arm920t = arm9tdmi->arch_info;
381
382 /* examine cp15 control reg */
383 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
384 jtag_execute_queue();
385 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
386
387 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
388 {
389 uint32_t cache_type_reg;
390 /* identify caches */
391 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
392 jtag_execute_queue();
393 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
394 }
395
396 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
397 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
398 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
399
400 /* save i/d fault status and address register */
401 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
402 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
403 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
404 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
405
406 LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
407 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
408
409 if (arm920t->preserve_cache)
410 {
411 /* read-modify-write CP15 test state register
412 * to disable I/D-cache linefills */
413 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
414 jtag_execute_queue();
415 cp15c15 |= 0x600;
416 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
417 }
418 }
419
420 void arm920t_pre_restore_context(target_t *target)
421 {
422 uint32_t cp15c15;
423 armv4_5_common_t *armv4_5 = target->arch_info;
424 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
425 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
426 arm920t_common_t *arm920t = arm9tdmi->arch_info;
427
428 /* restore i/d fault status and address register */
429 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
430 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
431 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
432 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
433
434 /* read-modify-write CP15 test state register
435 * to reenable I/D-cache linefills */
436 if (arm920t->preserve_cache)
437 {
438 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
439 jtag_execute_queue();
440 cp15c15 &= ~0x600U;
441 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
442 }
443 }
444
445 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
446 {
447 armv4_5_common_t *armv4_5 = target->arch_info;
448 arm7_9_common_t *arm7_9;
449 arm9tdmi_common_t *arm9tdmi;
450 arm920t_common_t *arm920t;
451
452 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
453 {
454 return -1;
455 }
456
457 arm7_9 = armv4_5->arch_info;
458 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
459 {
460 return -1;
461 }
462
463 arm9tdmi = arm7_9->arch_info;
464 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
465 {
466 return -1;
467 }
468
469 arm920t = arm9tdmi->arch_info;
470 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
471 {
472 return -1;
473 }
474
475 *armv4_5_p = armv4_5;
476 *arm7_9_p = arm7_9;
477 *arm9tdmi_p = arm9tdmi;
478 *arm920t_p = arm920t;
479
480 return ERROR_OK;
481 }
482
483 int arm920t_arch_state(struct target_s *target)
484 {
485 armv4_5_common_t *armv4_5 = target->arch_info;
486 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
487 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
488 arm920t_common_t *arm920t = arm9tdmi->arch_info;
489
490 char *state[] =
491 {
492 "disabled", "enabled"
493 };
494
495 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
496 {
497 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
498 exit(-1);
499 }
500
501 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
502 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
503 "MMU: %s, D-Cache: %s, I-Cache: %s",
504 armv4_5_state_strings[armv4_5->core_state],
505 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
506 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
507 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
508 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
509 state[arm920t->armv4_5_mmu.mmu_enabled],
510 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
511 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
512
513 return ERROR_OK;
514 }
515
516 int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
517 {
518 int retval;
519
520 retval = arm7_9_read_memory(target, address, size, count, buffer);
521
522 return retval;
523 }
524
525
526 int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
527 {
528 armv4_5_common_t *armv4_5 = target->arch_info;
529 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
530 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
531 arm920t_common_t *arm920t = arm9tdmi->arch_info;
532
533 return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
534 }
535
536 int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
537 {
538 armv4_5_common_t *armv4_5 = target->arch_info;
539 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
540 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
541 arm920t_common_t *arm920t = arm9tdmi->arch_info;
542
543 return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
544 }
545
546
547 int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
548 {
549 int retval;
550 armv4_5_common_t *armv4_5 = target->arch_info;
551 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
552 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
553 arm920t_common_t *arm920t = arm9tdmi->arch_info;
554
555 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
556 return retval;
557
558 if (((size == 4) || (size == 2)) && (count == 1))
559 {
560 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
561 {
562 LOG_DEBUG("D-Cache enabled, writing through to main memory");
563 uint32_t pa, cb, ap;
564 int type, domain;
565
566 pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
567 if (type == -1)
568 return ERROR_OK;
569 /* cacheable & bufferable means write-back region */
570 if (cb == 3)
571 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
572 }
573
574 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
575 {
576 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
577 arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
578 }
579 }
580
581 return retval;
582 }
583
584 int arm920t_soft_reset_halt(struct target_s *target)
585 {
586 int retval = ERROR_OK;
587 armv4_5_common_t *armv4_5 = target->arch_info;
588 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
589 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
590 arm920t_common_t *arm920t = arm9tdmi->arch_info;
591 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
592
593 if ((retval = target_halt(target)) != ERROR_OK)
594 {
595 return retval;
596 }
597
598 long long then = timeval_ms();
599 int timeout;
600 while (!(timeout = ((timeval_ms()-then) > 1000)))
601 {
602 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
603 {
604 embeddedice_read_reg(dbg_stat);
605 if ((retval = jtag_execute_queue()) != ERROR_OK)
606 {
607 return retval;
608 }
609 } else
610 {
611 break;
612 }
613 if (debug_level >= 3)
614 {
615 /* do not eat all CPU, time out after 1 se*/
616 alive_sleep(100);
617 } else
618 {
619 keep_alive();
620 }
621 }
622 if (timeout)
623 {
624 LOG_ERROR("Failed to halt CPU after 1 sec");
625 return ERROR_TARGET_TIMEOUT;
626 }
627
628 target->state = TARGET_HALTED;
629
630 /* SVC, ARM state, IRQ and FIQ disabled */
631 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
632 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
633 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
634
635 /* start fetching from 0x0 */
636 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
637 armv4_5->core_cache->reg_list[15].dirty = 1;
638 armv4_5->core_cache->reg_list[15].valid = 1;
639
640 armv4_5->core_mode = ARMV4_5_MODE_SVC;
641 armv4_5->core_state = ARMV4_5_STATE_ARM;
642
643 arm920t_disable_mmu_caches(target, 1, 1, 1);
644 arm920t->armv4_5_mmu.mmu_enabled = 0;
645 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
646 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
647
648 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
649 {
650 return retval;
651 }
652
653 return ERROR_OK;
654 }
655
656 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
657 {
658 arm9tdmi_init_target(cmd_ctx, target);
659
660 return ERROR_OK;
661 }
662
663 int arm920t_quit(void)
664 {
665 return ERROR_OK;
666 }
667
668 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
669 {
670 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
671 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
672
673 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
674 */
675 arm9tdmi_init_arch_info(target, arm9tdmi, tap);
676
677 arm9tdmi->arch_info = arm920t;
678 arm920t->common_magic = ARM920T_COMMON_MAGIC;
679
680 arm7_9->post_debug_entry = arm920t_post_debug_entry;
681 arm7_9->pre_restore_context = arm920t_pre_restore_context;
682
683 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
684 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
685 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
686 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
687 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
688 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
689 arm920t->armv4_5_mmu.has_tiny_pages = 1;
690 arm920t->armv4_5_mmu.mmu_enabled = 0;
691
692 /* disabling linefills leads to lockups, so keep them enabled for now
693 * this doesn't affect correctness, but might affect timing issues, if
694 * important data is evicted from the cache during the debug session
695 * */
696 arm920t->preserve_cache = 0;
697
698 /* override hw single-step capability from ARM9TDMI */
699 arm7_9->has_single_step = 1;
700
701 return ERROR_OK;
702 }
703
704 int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
705 {
706 arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
707
708 arm920t_init_arch_info(target, arm920t, target->tap);
709
710 return ERROR_OK;
711 }
712
713 int arm920t_register_commands(struct command_context_s *cmd_ctx)
714 {
715 int retval;
716 command_t *arm920t_cmd;
717
718
719 retval = arm9tdmi_register_commands(cmd_ctx);
720
721 arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
722
723 register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
724 register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
725 register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
726
727 register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
728 register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
729
730 return retval;
731 }
732
733 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
734 {
735 int retval = ERROR_OK;
736 target_t *target = get_current_target(cmd_ctx);
737 armv4_5_common_t *armv4_5;
738 arm7_9_common_t *arm7_9;
739 arm9tdmi_common_t *arm9tdmi;
740 arm920t_common_t *arm920t;
741 arm_jtag_t *jtag_info;
742 uint32_t cp15c15;
743 uint32_t cp15_ctrl, cp15_ctrl_saved;
744 uint32_t regs[16];
745 uint32_t *regs_p[16];
746 uint32_t C15_C_D_Ind, C15_C_I_Ind;
747 int i;
748 FILE *output;
749 arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
750 int segment, index;
751
752 if (argc != 1)
753 {
754 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
755 return ERROR_OK;
756 }
757
758 if ((output = fopen(args[0], "w")) == NULL)
759 {
760 LOG_DEBUG("error opening cache content file");
761 return ERROR_OK;
762 }
763
764 for (i = 0; i < 16; i++)
765 regs_p[i] = &regs[i];
766
767 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
768 {
769 command_print(cmd_ctx, "current target isn't an ARM920t target");
770 return ERROR_OK;
771 }
772
773 jtag_info = &arm7_9->jtag_info;
774
775 /* disable MMU and Caches */
776 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
777 if ((retval = jtag_execute_queue()) != ERROR_OK)
778 {
779 return retval;
780 }
781 cp15_ctrl_saved = cp15_ctrl;
782 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
783 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
784
785 /* read CP15 test state register */
786 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
787 jtag_execute_queue();
788
789 /* read DCache content */
790 fprintf(output, "DCache:\n");
791
792 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
793 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
794 {
795 fprintf(output, "\nsegment: %i\n----------", segment);
796
797 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
798 regs[0] = 0x0 | (segment << 5);
799 arm9tdmi_write_core_regs(target, 0x1, regs);
800
801 /* set interpret mode */
802 cp15c15 |= 0x1;
803 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
804
805 /* D CAM Read, loads current victim into C15.C.D.Ind */
806 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
807
808 /* read current victim */
809 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
810
811 /* clear interpret mode */
812 cp15c15 &= ~0x1;
813 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
814
815 for (index = 0; index < 64; index++)
816 {
817 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
818 regs[0] = 0x0 | (segment << 5) | (index << 26);
819 arm9tdmi_write_core_regs(target, 0x1, regs);
820
821 /* set interpret mode */
822 cp15c15 |= 0x1;
823 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
824
825 /* Write DCache victim */
826 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
827
828 /* Read D RAM */
829 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
830
831 /* Read D CAM */
832 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
833
834 /* clear interpret mode */
835 cp15c15 &= ~0x1;
836 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
837
838 /* read D RAM and CAM content */
839 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
840 if ((retval = jtag_execute_queue()) != ERROR_OK)
841 {
842 return retval;
843 }
844
845 d_cache[segment][index].cam = regs[9];
846
847 /* mask LFSR[6] */
848 regs[9] &= 0xfffffffe;
849 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
850
851 for (i = 1; i < 9; i++)
852 {
853 d_cache[segment][index].data[i] = regs[i];
854 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
855 }
856
857 }
858
859 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
860 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
861 arm9tdmi_write_core_regs(target, 0x1, regs);
862
863 /* set interpret mode */
864 cp15c15 |= 0x1;
865 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
866
867 /* Write DCache victim */
868 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
869
870 /* clear interpret mode */
871 cp15c15 &= ~0x1;
872 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
873 }
874
875 /* read ICache content */
876 fprintf(output, "ICache:\n");
877
878 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
879 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
880 {
881 fprintf(output, "segment: %i\n----------", segment);
882
883 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
884 regs[0] = 0x0 | (segment << 5);
885 arm9tdmi_write_core_regs(target, 0x1, regs);
886
887 /* set interpret mode */
888 cp15c15 |= 0x1;
889 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
890
891 /* I CAM Read, loads current victim into C15.C.I.Ind */
892 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
893
894 /* read current victim */
895 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
896
897 /* clear interpret mode */
898 cp15c15 &= ~0x1;
899 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
900
901 for (index = 0; index < 64; index++)
902 {
903 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
904 regs[0] = 0x0 | (segment << 5) | (index << 26);
905 arm9tdmi_write_core_regs(target, 0x1, regs);
906
907 /* set interpret mode */
908 cp15c15 |= 0x1;
909 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
910
911 /* Write ICache victim */
912 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
913
914 /* Read I RAM */
915 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
916
917 /* Read I CAM */
918 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
919
920 /* clear interpret mode */
921 cp15c15 &= ~0x1;
922 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
923
924 /* read I RAM and CAM content */
925 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
926 if ((retval = jtag_execute_queue()) != ERROR_OK)
927 {
928 return retval;
929 }
930
931 i_cache[segment][index].cam = regs[9];
932
933 /* mask LFSR[6] */
934 regs[9] &= 0xfffffffe;
935 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
936
937 for (i = 1; i < 9; i++)
938 {
939 i_cache[segment][index].data[i] = regs[i];
940 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
941 }
942 }
943
944 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
945 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
946 arm9tdmi_write_core_regs(target, 0x1, regs);
947
948 /* set interpret mode */
949 cp15c15 |= 0x1;
950 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
951
952 /* Write ICache victim */
953 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
954
955 /* clear interpret mode */
956 cp15c15 &= ~0x1;
957 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
958 }
959
960 /* restore CP15 MMU and Cache settings */
961 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
962
963 command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
964
965 fclose(output);
966
967 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
968 return ERROR_FAIL;
969
970 /* mark registers dirty. */
971 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
972 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
973 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
974 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
975 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
976 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
977 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
978 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
979 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
980 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
981
982 return ERROR_OK;
983 }
984
985 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
986 {
987 int retval = ERROR_OK;
988 target_t *target = get_current_target(cmd_ctx);
989 armv4_5_common_t *armv4_5;
990 arm7_9_common_t *arm7_9;
991 arm9tdmi_common_t *arm9tdmi;
992 arm920t_common_t *arm920t;
993 arm_jtag_t *jtag_info;
994 uint32_t cp15c15;
995 uint32_t cp15_ctrl, cp15_ctrl_saved;
996 uint32_t regs[16];
997 uint32_t *regs_p[16];
998 int i;
999 FILE *output;
1000 uint32_t Dlockdown, Ilockdown;
1001 arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1002 int victim;
1003
1004 if (argc != 1)
1005 {
1006 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1007 return ERROR_OK;
1008 }
1009
1010 if ((output = fopen(args[0], "w")) == NULL)
1011 {
1012 LOG_DEBUG("error opening mmu content file");
1013 return ERROR_OK;
1014 }
1015
1016 for (i = 0; i < 16; i++)
1017 regs_p[i] = &regs[i];
1018
1019 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1020 {
1021 command_print(cmd_ctx, "current target isn't an ARM920t target");
1022 return ERROR_OK;
1023 }
1024
1025 jtag_info = &arm7_9->jtag_info;
1026
1027 /* disable MMU and Caches */
1028 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1029 if ((retval = jtag_execute_queue()) != ERROR_OK)
1030 {
1031 return retval;
1032 }
1033 cp15_ctrl_saved = cp15_ctrl;
1034 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1035 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1036
1037 /* read CP15 test state register */
1038 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1039 if ((retval = jtag_execute_queue()) != ERROR_OK)
1040 {
1041 return retval;
1042 }
1043
1044 /* prepare reading D TLB content
1045 * */
1046
1047 /* set interpret mode */
1048 cp15c15 |= 0x1;
1049 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1050
1051 /* Read D TLB lockdown */
1052 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1053
1054 /* clear interpret mode */
1055 cp15c15 &= ~0x1;
1056 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1057
1058 /* read D TLB lockdown stored to r1 */
1059 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1060 if ((retval = jtag_execute_queue()) != ERROR_OK)
1061 {
1062 return retval;
1063 }
1064 Dlockdown = regs[1];
1065
1066 for (victim = 0; victim < 64; victim += 8)
1067 {
1068 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1069 * base remains unchanged, victim goes through entries 0 to 63 */
1070 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1071 arm9tdmi_write_core_regs(target, 0x2, regs);
1072
1073 /* set interpret mode */
1074 cp15c15 |= 0x1;
1075 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1076
1077 /* Write D TLB lockdown */
1078 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1079
1080 /* Read D TLB CAM */
1081 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1082
1083 /* clear interpret mode */
1084 cp15c15 &= ~0x1;
1085 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1086
1087 /* read D TLB CAM content stored to r2-r9 */
1088 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1089 if ((retval = jtag_execute_queue()) != ERROR_OK)
1090 {
1091 return retval;
1092 }
1093
1094 for (i = 0; i < 8; i++)
1095 d_tlb[victim + i].cam = regs[i + 2];
1096 }
1097
1098 for (victim = 0; victim < 64; victim++)
1099 {
1100 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1101 * base remains unchanged, victim goes through entries 0 to 63 */
1102 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1103 arm9tdmi_write_core_regs(target, 0x2, regs);
1104
1105 /* set interpret mode */
1106 cp15c15 |= 0x1;
1107 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1108
1109 /* Write D TLB lockdown */
1110 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1111
1112 /* Read D TLB RAM1 */
1113 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1114
1115 /* Read D TLB RAM2 */
1116 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1117
1118 /* clear interpret mode */
1119 cp15c15 &= ~0x1;
1120 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1121
1122 /* read D TLB RAM content stored to r2 and r3 */
1123 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1124 if ((retval = jtag_execute_queue()) != ERROR_OK)
1125 {
1126 return retval;
1127 }
1128
1129 d_tlb[victim].ram1 = regs[2];
1130 d_tlb[victim].ram2 = regs[3];
1131 }
1132
1133 /* restore D TLB lockdown */
1134 regs[1] = Dlockdown;
1135 arm9tdmi_write_core_regs(target, 0x2, regs);
1136
1137 /* Write D TLB lockdown */
1138 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1139
1140 /* prepare reading I TLB content
1141 * */
1142
1143 /* set interpret mode */
1144 cp15c15 |= 0x1;
1145 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1146
1147 /* Read I TLB lockdown */
1148 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1149
1150 /* clear interpret mode */
1151 cp15c15 &= ~0x1;
1152 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1153
1154 /* read I TLB lockdown stored to r1 */
1155 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1156 if ((retval = jtag_execute_queue()) != ERROR_OK)
1157 {
1158 return retval;
1159 }
1160 Ilockdown = regs[1];
1161
1162 for (victim = 0; victim < 64; victim += 8)
1163 {
1164 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1165 * base remains unchanged, victim goes through entries 0 to 63 */
1166 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1167 arm9tdmi_write_core_regs(target, 0x2, regs);
1168
1169 /* set interpret mode */
1170 cp15c15 |= 0x1;
1171 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1172
1173 /* Write I TLB lockdown */
1174 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1175
1176 /* Read I TLB CAM */
1177 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1178
1179 /* clear interpret mode */
1180 cp15c15 &= ~0x1;
1181 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1182
1183 /* read I TLB CAM content stored to r2-r9 */
1184 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1185 if ((retval = jtag_execute_queue()) != ERROR_OK)
1186 {
1187 return retval;
1188 }
1189
1190 for (i = 0; i < 8; i++)
1191 i_tlb[i + victim].cam = regs[i + 2];
1192 }
1193
1194 for (victim = 0; victim < 64; victim++)
1195 {
1196 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1197 * base remains unchanged, victim goes through entries 0 to 63 */
1198 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1199 arm9tdmi_write_core_regs(target, 0x2, regs);
1200
1201 /* set interpret mode */
1202 cp15c15 |= 0x1;
1203 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1204
1205 /* Write I TLB lockdown */
1206 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1207
1208 /* Read I TLB RAM1 */
1209 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1210
1211 /* Read I TLB RAM2 */
1212 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1213
1214 /* clear interpret mode */
1215 cp15c15 &= ~0x1;
1216 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1217
1218 /* read I TLB RAM content stored to r2 and r3 */
1219 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1220 if ((retval = jtag_execute_queue()) != ERROR_OK)
1221 {
1222 return retval;
1223 }
1224
1225 i_tlb[victim].ram1 = regs[2];
1226 i_tlb[victim].ram2 = regs[3];
1227 }
1228
1229 /* restore I TLB lockdown */
1230 regs[1] = Ilockdown;
1231 arm9tdmi_write_core_regs(target, 0x2, regs);
1232
1233 /* Write I TLB lockdown */
1234 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1235
1236 /* restore CP15 MMU and Cache settings */
1237 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1238
1239 /* output data to file */
1240 fprintf(output, "D TLB content:\n");
1241 for (i = 0; i < 64; i++)
1242 {
1243 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1244 }
1245
1246 fprintf(output, "\n\nI TLB content:\n");
1247 for (i = 0; i < 64; i++)
1248 {
1249 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1250 }
1251
1252 command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1253
1254 fclose(output);
1255
1256 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1257 return ERROR_FAIL;
1258
1259 /* mark registers dirty */
1260 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1261 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1262 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1263 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1264 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1265 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1266 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1267 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1268 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1269 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1270
1271 return ERROR_OK;
1272 }
1273 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1274 {
1275 int retval;
1276 target_t *target = get_current_target(cmd_ctx);
1277 armv4_5_common_t *armv4_5;
1278 arm7_9_common_t *arm7_9;
1279 arm9tdmi_common_t *arm9tdmi;
1280 arm920t_common_t *arm920t;
1281 arm_jtag_t *jtag_info;
1282
1283 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1284 {
1285 command_print(cmd_ctx, "current target isn't an ARM920t target");
1286 return ERROR_OK;
1287 }
1288
1289 jtag_info = &arm7_9->jtag_info;
1290
1291 if (target->state != TARGET_HALTED)
1292 {
1293 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1294 return ERROR_OK;
1295 }
1296
1297 /* one or more argument, access a single register (write if second argument is given */
1298 if (argc >= 1)
1299 {
1300 int address = strtoul(args[0], NULL, 0);
1301
1302 if (argc == 1)
1303 {
1304 uint32_t value;
1305 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1306 {
1307 command_print(cmd_ctx, "couldn't access reg %i", address);
1308 return ERROR_OK;
1309 }
1310 if ((retval = jtag_execute_queue()) != ERROR_OK)
1311 {
1312 return retval;
1313 }
1314
1315 command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
1316 }
1317 else if (argc == 2)
1318 {
1319 uint32_t value = strtoul(args[1], NULL, 0);
1320 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1321 {
1322 command_print(cmd_ctx, "couldn't access reg %i", address);
1323 return ERROR_OK;
1324 }
1325 command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
1326 }
1327 }
1328
1329 return ERROR_OK;
1330 }
1331
1332 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1333 {
1334 int retval;
1335 target_t *target = get_current_target(cmd_ctx);
1336 armv4_5_common_t *armv4_5;
1337 arm7_9_common_t *arm7_9;
1338 arm9tdmi_common_t *arm9tdmi;
1339 arm920t_common_t *arm920t;
1340 arm_jtag_t *jtag_info;
1341
1342 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1343 {
1344 command_print(cmd_ctx, "current target isn't an ARM920t target");
1345 return ERROR_OK;
1346 }
1347
1348 jtag_info = &arm7_9->jtag_info;
1349
1350 if (target->state != TARGET_HALTED)
1351 {
1352 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1353 return ERROR_OK;
1354 }
1355
1356 /* one or more argument, access a single register (write if second argument is given */
1357 if (argc >= 1)
1358 {
1359 uint32_t opcode = strtoul(args[0], NULL, 0);
1360
1361 if (argc == 1)
1362 {
1363 uint32_t value;
1364 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1365 {
1366 command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
1367 return ERROR_OK;
1368 }
1369
1370 command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1371 }
1372 else if (argc == 2)
1373 {
1374 uint32_t value = strtoul(args[1], NULL, 0);
1375 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1376 {
1377 command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
1378 return ERROR_OK;
1379 }
1380 command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1381 }
1382 else if (argc == 3)
1383 {
1384 uint32_t value = strtoul(args[1], NULL, 0);
1385 uint32_t address = strtoul(args[2], NULL, 0);
1386 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1387 {
1388 command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
1389 return ERROR_OK;
1390 }
1391 command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
1392 }
1393 }
1394 else
1395 {
1396 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1397 }
1398
1399 return ERROR_OK;
1400 }
1401
1402 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1403 {
1404 target_t *target = get_current_target(cmd_ctx);
1405 armv4_5_common_t *armv4_5;
1406 arm7_9_common_t *arm7_9;
1407 arm9tdmi_common_t *arm9tdmi;
1408 arm920t_common_t *arm920t;
1409
1410 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1411 {
1412 command_print(cmd_ctx, "current target isn't an ARM920t target");
1413 return ERROR_OK;
1414 }
1415
1416 return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1417 }
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