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[openocd.git] / src / target / arm920t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm920t.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35 /* cli handling */
36 int arm920t_register_commands(struct command_context_s *cmd_ctx);
37
38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44
45 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm920t_quit();
52 int arm920t_arch_state(struct target_s *target);
53 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
54 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm920t_soft_reset_halt(struct target_s *target);
56
57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
58
59 target_type_t arm920t_target =
60 {
61 .name = "arm920t",
62
63 .poll = arm7_9_poll,
64 .arch_state = arm920t_arch_state,
65
66 .target_request_data = arm7_9_target_request_data,
67
68 .halt = arm7_9_halt,
69 .resume = arm7_9_resume,
70 .step = arm7_9_step,
71
72 .assert_reset = arm7_9_assert_reset,
73 .deassert_reset = arm7_9_deassert_reset,
74 .soft_reset_halt = arm920t_soft_reset_halt,
75
76 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
77
78 .read_memory = arm920t_read_memory,
79 .write_memory = arm920t_write_memory,
80 .bulk_write_memory = arm7_9_bulk_write_memory,
81 .checksum_memory = arm7_9_checksum_memory,
82
83 .run_algorithm = armv4_5_run_algorithm,
84
85 .add_breakpoint = arm7_9_add_breakpoint,
86 .remove_breakpoint = arm7_9_remove_breakpoint,
87 .add_watchpoint = arm7_9_add_watchpoint,
88 .remove_watchpoint = arm7_9_remove_watchpoint,
89
90 .register_commands = arm920t_register_commands,
91 .target_command = arm920t_target_command,
92 .init_target = arm920t_init_target,
93 .examine = arm9tdmi_examine,
94 .quit = arm920t_quit
95 };
96
97 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
98 {
99 armv4_5_common_t *armv4_5 = target->arch_info;
100 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
101 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
102 scan_field_t fields[4];
103 u8 access_type_buf = 1;
104 u8 reg_addr_buf = reg_addr & 0x3f;
105 u8 nr_w_buf = 0;
106
107 jtag_add_end_state(TAP_RTI);
108 arm_jtag_scann(jtag_info, 0xf);
109 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
110
111 fields[0].device = jtag_info->chain_pos;
112 fields[0].num_bits = 1;
113 fields[0].out_value = &access_type_buf;
114 fields[0].out_mask = NULL;
115 fields[0].in_value = NULL;
116 fields[0].in_check_value = NULL;
117 fields[0].in_check_mask = NULL;
118 fields[0].in_handler = NULL;
119 fields[0].in_handler_priv = NULL;
120
121 fields[1].device = jtag_info->chain_pos;
122 fields[1].num_bits = 32;
123 fields[1].out_value = NULL;
124 fields[1].out_mask = NULL;
125 fields[1].in_value = NULL;
126 fields[1].in_check_value = NULL;
127 fields[1].in_check_mask = NULL;
128 fields[1].in_handler = NULL;
129 fields[1].in_handler_priv = NULL;
130
131 fields[2].device = jtag_info->chain_pos;
132 fields[2].num_bits = 6;
133 fields[2].out_value = &reg_addr_buf;
134 fields[2].out_mask = NULL;
135 fields[2].in_value = NULL;
136 fields[2].in_check_value = NULL;
137 fields[2].in_check_mask = NULL;
138 fields[2].in_handler = NULL;
139 fields[2].in_handler_priv = NULL;
140
141 fields[3].device = jtag_info->chain_pos;
142 fields[3].num_bits = 1;
143 fields[3].out_value = &nr_w_buf;
144 fields[3].out_mask = NULL;
145 fields[3].in_value = NULL;
146 fields[3].in_check_value = NULL;
147 fields[3].in_check_mask = NULL;
148 fields[3].in_handler = NULL;
149 fields[3].in_handler_priv = NULL;
150
151 jtag_add_dr_scan(4, fields, -1);
152
153 fields[1].in_handler_priv = value;
154 fields[1].in_handler = arm_jtag_buf_to_u32;
155
156 jtag_add_dr_scan(4, fields, -1);
157
158 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
159 jtag_execute_queue();
160 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
161 #endif
162
163 return ERROR_OK;
164 }
165
166 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
167 {
168 armv4_5_common_t *armv4_5 = target->arch_info;
169 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
170 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
171 scan_field_t fields[4];
172 u8 access_type_buf = 1;
173 u8 reg_addr_buf = reg_addr & 0x3f;
174 u8 nr_w_buf = 1;
175 u8 value_buf[4];
176
177 buf_set_u32(value_buf, 0, 32, value);
178
179 jtag_add_end_state(TAP_RTI);
180 arm_jtag_scann(jtag_info, 0xf);
181 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
182
183 fields[0].device = jtag_info->chain_pos;
184 fields[0].num_bits = 1;
185 fields[0].out_value = &access_type_buf;
186 fields[0].out_mask = NULL;
187 fields[0].in_value = NULL;
188 fields[0].in_check_value = NULL;
189 fields[0].in_check_mask = NULL;
190 fields[0].in_handler = NULL;
191 fields[0].in_handler_priv = NULL;
192
193 fields[1].device = jtag_info->chain_pos;
194 fields[1].num_bits = 32;
195 fields[1].out_value = value_buf;
196 fields[1].out_mask = NULL;
197 fields[1].in_value = NULL;
198 fields[1].in_check_value = NULL;
199 fields[1].in_check_mask = NULL;
200 fields[1].in_handler = NULL;
201 fields[1].in_handler_priv = NULL;
202
203 fields[2].device = jtag_info->chain_pos;
204 fields[2].num_bits = 6;
205 fields[2].out_value = &reg_addr_buf;
206 fields[2].out_mask = NULL;
207 fields[2].in_value = NULL;
208 fields[2].in_check_value = NULL;
209 fields[2].in_check_mask = NULL;
210 fields[2].in_handler = NULL;
211 fields[2].in_handler_priv = NULL;
212
213 fields[3].device = jtag_info->chain_pos;
214 fields[3].num_bits = 1;
215 fields[3].out_value = &nr_w_buf;
216 fields[3].out_mask = NULL;
217 fields[3].in_value = NULL;
218 fields[3].in_check_value = NULL;
219 fields[3].in_check_mask = NULL;
220 fields[3].in_handler = NULL;
221 fields[3].in_handler_priv = NULL;
222
223 jtag_add_dr_scan(4, fields, -1);
224
225 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
226 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
227 #endif
228
229 return ERROR_OK;
230 }
231
232 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
233 {
234 armv4_5_common_t *armv4_5 = target->arch_info;
235 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
236 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
237 scan_field_t fields[4];
238 u8 access_type_buf = 0; /* interpreted access */
239 u8 reg_addr_buf = 0x0;
240 u8 nr_w_buf = 0;
241 u8 cp15_opcode_buf[4];
242
243 jtag_add_end_state(TAP_RTI);
244 arm_jtag_scann(jtag_info, 0xf);
245 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
246
247 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
248
249 fields[0].device = jtag_info->chain_pos;
250 fields[0].num_bits = 1;
251 fields[0].out_value = &access_type_buf;
252 fields[0].out_mask = NULL;
253 fields[0].in_value = NULL;
254 fields[0].in_check_value = NULL;
255 fields[0].in_check_mask = NULL;
256 fields[0].in_handler = NULL;
257 fields[0].in_handler_priv = NULL;
258
259 fields[1].device = jtag_info->chain_pos;
260 fields[1].num_bits = 32;
261 fields[1].out_value = cp15_opcode_buf;
262 fields[1].out_mask = NULL;
263 fields[1].in_value = NULL;
264 fields[1].in_check_value = NULL;
265 fields[1].in_check_mask = NULL;
266 fields[1].in_handler = NULL;
267 fields[1].in_handler_priv = NULL;
268
269 fields[2].device = jtag_info->chain_pos;
270 fields[2].num_bits = 6;
271 fields[2].out_value = &reg_addr_buf;
272 fields[2].out_mask = NULL;
273 fields[2].in_value = NULL;
274 fields[2].in_check_value = NULL;
275 fields[2].in_check_mask = NULL;
276 fields[2].in_handler = NULL;
277 fields[2].in_handler_priv = NULL;
278
279 fields[3].device = jtag_info->chain_pos;
280 fields[3].num_bits = 1;
281 fields[3].out_value = &nr_w_buf;
282 fields[3].out_mask = NULL;
283 fields[3].in_value = NULL;
284 fields[3].in_check_value = NULL;
285 fields[3].in_check_mask = NULL;
286 fields[3].in_handler = NULL;
287 fields[3].in_handler_priv = NULL;
288
289 jtag_add_dr_scan(4, fields, -1);
290
291 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
292 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
293 arm7_9_execute_sys_speed(target);
294
295 if (jtag_execute_queue() != ERROR_OK)
296 {
297 LOG_ERROR("failed executing JTAG queue, exiting");
298 exit(-1);
299 }
300
301 return ERROR_OK;
302 }
303
304 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
305 {
306 armv4_5_common_t *armv4_5 = target->arch_info;
307 u32* regs_p[1];
308 u32 regs[2];
309 u32 cp15c15 = 0x0;
310
311 /* load address into R1 */
312 regs[1] = address;
313 arm9tdmi_write_core_regs(target, 0x2, regs);
314
315 /* read-modify-write CP15 test state register
316 * to enable interpreted access mode */
317 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
318 jtag_execute_queue();
319 cp15c15 |= 1; /* set interpret mode */
320 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
321
322 /* execute CP15 instruction and ARM load (reading from coprocessor) */
323 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
324
325 /* disable interpreted access mode */
326 cp15c15 &= ~1U; /* clear interpret mode */
327 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
328
329 /* retrieve value from R0 */
330 regs_p[0] = value;
331 arm9tdmi_read_core_regs(target, 0x1, regs_p);
332 jtag_execute_queue();
333
334 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
335 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
336 #endif
337
338 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
339 return ERROR_FAIL;
340
341 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
342 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
343
344 return ERROR_OK;
345 }
346
347 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
348 {
349 u32 cp15c15 = 0x0;
350 armv4_5_common_t *armv4_5 = target->arch_info;
351 u32 regs[2];
352
353 /* load value, address into R0, R1 */
354 regs[0] = value;
355 regs[1] = address;
356 arm9tdmi_write_core_regs(target, 0x3, regs);
357
358 /* read-modify-write CP15 test state register
359 * to enable interpreted access mode */
360 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
361 jtag_execute_queue();
362 cp15c15 |= 1; /* set interpret mode */
363 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
364
365 /* execute CP15 instruction and ARM store (writing to coprocessor) */
366 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
367
368 /* disable interpreted access mode */
369 cp15c15 &= ~1U; /* set interpret mode */
370 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
371
372 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
373 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
374 #endif
375
376 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
377 return ERROR_FAIL;
378
379 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
380 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
381
382 return ERROR_OK;
383 }
384
385 u32 arm920t_get_ttb(target_t *target)
386 {
387 int retval;
388 u32 ttb = 0x0;
389
390 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
391 return retval;
392
393 return ttb;
394 }
395
396 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
397 {
398 u32 cp15_control;
399
400 /* read cp15 control register */
401 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
402 jtag_execute_queue();
403
404 if (mmu)
405 cp15_control &= ~0x1U;
406
407 if (d_u_cache)
408 cp15_control &= ~0x4U;
409
410 if (i_cache)
411 cp15_control &= ~0x1000U;
412
413 arm920t_write_cp15_physical(target, 0x2, cp15_control);
414 }
415
416 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
417 {
418 u32 cp15_control;
419
420 /* read cp15 control register */
421 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
422 jtag_execute_queue();
423
424 if (mmu)
425 cp15_control |= 0x1U;
426
427 if (d_u_cache)
428 cp15_control |= 0x4U;
429
430 if (i_cache)
431 cp15_control |= 0x1000U;
432
433 arm920t_write_cp15_physical(target, 0x2, cp15_control);
434 }
435
436 void arm920t_post_debug_entry(target_t *target)
437 {
438 u32 cp15c15;
439 armv4_5_common_t *armv4_5 = target->arch_info;
440 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
441 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
442 arm920t_common_t *arm920t = arm9tdmi->arch_info;
443
444 /* examine cp15 control reg */
445 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
446 jtag_execute_queue();
447 LOG_DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
448
449 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
450 {
451 u32 cache_type_reg;
452 /* identify caches */
453 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
454 jtag_execute_queue();
455 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
456 }
457
458 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
459 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
460 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
461
462 /* save i/d fault status and address register */
463 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
464 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
465 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
466 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
467
468 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
469 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
470
471 if (arm920t->preserve_cache)
472 {
473 /* read-modify-write CP15 test state register
474 * to disable I/D-cache linefills */
475 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
476 jtag_execute_queue();
477 cp15c15 |= 0x600;
478 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
479 }
480 }
481
482 void arm920t_pre_restore_context(target_t *target)
483 {
484 u32 cp15c15;
485 armv4_5_common_t *armv4_5 = target->arch_info;
486 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
487 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
488 arm920t_common_t *arm920t = arm9tdmi->arch_info;
489
490 /* restore i/d fault status and address register */
491 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
492 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
493 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
494 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
495
496 /* read-modify-write CP15 test state register
497 * to reenable I/D-cache linefills */
498 if (arm920t->preserve_cache)
499 {
500 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
501 jtag_execute_queue();
502 cp15c15 &= ~0x600U;
503 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
504 }
505 }
506
507 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
508 {
509 armv4_5_common_t *armv4_5 = target->arch_info;
510 arm7_9_common_t *arm7_9;
511 arm9tdmi_common_t *arm9tdmi;
512 arm920t_common_t *arm920t;
513
514 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
515 {
516 return -1;
517 }
518
519 arm7_9 = armv4_5->arch_info;
520 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
521 {
522 return -1;
523 }
524
525 arm9tdmi = arm7_9->arch_info;
526 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
527 {
528 return -1;
529 }
530
531 arm920t = arm9tdmi->arch_info;
532 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
533 {
534 return -1;
535 }
536
537 *armv4_5_p = armv4_5;
538 *arm7_9_p = arm7_9;
539 *arm9tdmi_p = arm9tdmi;
540 *arm920t_p = arm920t;
541
542 return ERROR_OK;
543 }
544
545 int arm920t_arch_state(struct target_s *target)
546 {
547 armv4_5_common_t *armv4_5 = target->arch_info;
548 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
549 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
550 arm920t_common_t *arm920t = arm9tdmi->arch_info;
551
552 char *state[] =
553 {
554 "disabled", "enabled"
555 };
556
557 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
558 {
559 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
560 exit(-1);
561 }
562
563 LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
564 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
565 "MMU: %s, D-Cache: %s, I-Cache: %s",
566 armv4_5_state_strings[armv4_5->core_state],
567 target_debug_reason_strings[target->debug_reason],
568 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
569 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
570 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
571 state[arm920t->armv4_5_mmu.mmu_enabled],
572 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
573 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
574
575 return ERROR_OK;
576 }
577
578 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
579 {
580 int retval;
581
582 retval = arm7_9_read_memory(target, address, size, count, buffer);
583
584 return retval;
585 }
586
587 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
588 {
589 int retval;
590 armv4_5_common_t *armv4_5 = target->arch_info;
591 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
592 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
593 arm920t_common_t *arm920t = arm9tdmi->arch_info;
594
595 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
596 return retval;
597
598 if (((size == 4) || (size == 2)) && (count == 1))
599 {
600 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
601 {
602 LOG_DEBUG("D-Cache enabled, writing through to main memory");
603 u32 pa, cb, ap;
604 int type, domain;
605
606 pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
607 if (type == -1)
608 return ERROR_OK;
609 /* cacheable & bufferable means write-back region */
610 if (cb == 3)
611 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
612 }
613
614 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
615 {
616 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
617 arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
618 }
619 }
620
621 return retval;
622 }
623
624 int arm920t_soft_reset_halt(struct target_s *target)
625 {
626 armv4_5_common_t *armv4_5 = target->arch_info;
627 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
628 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
629 arm920t_common_t *arm920t = arm9tdmi->arch_info;
630 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
631 int i;
632
633 target_halt(target);
634
635 for (i=0; i<10; i++)
636 {
637 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
638 {
639 embeddedice_read_reg(dbg_stat);
640 jtag_execute_queue();
641 } else
642 {
643 break;
644 }
645 /* do not eat all CPU, time out after 1 se*/
646 usleep(100*1000);
647 }
648 if (i==10)
649 {
650 LOG_ERROR("Failed to halt CPU after 1 sec");
651 return ERROR_TARGET_TIMEOUT;
652 }
653
654 target->state = TARGET_HALTED;
655
656 /* SVC, ARM state, IRQ and FIQ disabled */
657 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
658 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
659 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
660
661 /* start fetching from 0x0 */
662 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
663 armv4_5->core_cache->reg_list[15].dirty = 1;
664 armv4_5->core_cache->reg_list[15].valid = 1;
665
666 armv4_5->core_mode = ARMV4_5_MODE_SVC;
667 armv4_5->core_state = ARMV4_5_STATE_ARM;
668
669 arm920t_disable_mmu_caches(target, 1, 1, 1);
670 arm920t->armv4_5_mmu.mmu_enabled = 0;
671 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
672 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
673
674 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
675
676 return ERROR_OK;
677 }
678
679 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
680 {
681 arm9tdmi_init_target(cmd_ctx, target);
682
683 return ERROR_OK;
684
685 }
686
687 int arm920t_quit()
688 {
689
690 return ERROR_OK;
691 }
692
693 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)
694 {
695 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
696 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
697
698 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
699 */
700 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
701
702 arm9tdmi->arch_info = arm920t;
703 arm920t->common_magic = ARM920T_COMMON_MAGIC;
704
705 arm7_9->post_debug_entry = arm920t_post_debug_entry;
706 arm7_9->pre_restore_context = arm920t_pre_restore_context;
707
708 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
709 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
710 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
711 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
712 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
713 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
714 arm920t->armv4_5_mmu.has_tiny_pages = 1;
715 arm920t->armv4_5_mmu.mmu_enabled = 0;
716
717 /* disabling linefills leads to lockups, so keep them enabled for now
718 * this doesn't affect correctness, but might affect timing issues, if
719 * important data is evicted from the cache during the debug session
720 * */
721 arm920t->preserve_cache = 0;
722
723 /* override hw single-step capability from ARM9TDMI */
724 arm7_9->has_single_step = 1;
725
726 return ERROR_OK;
727 }
728
729 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
730 {
731 int chain_pos;
732 char *variant = NULL;
733 arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
734 memset(arm920t, 0, sizeof(*arm920t));
735
736 if (argc < 4)
737 {
738 LOG_ERROR("'target arm920t' requires at least one additional argument");
739 exit(-1);
740 }
741
742 chain_pos = strtoul(args[3], NULL, 0);
743
744 if (argc >= 5)
745 variant = args[4];
746
747 LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
748
749 arm920t_init_arch_info(target, arm920t, chain_pos, variant);
750
751 return ERROR_OK;
752 }
753
754 int arm920t_register_commands(struct command_context_s *cmd_ctx)
755 {
756 int retval;
757 command_t *arm920t_cmd;
758
759
760 retval = arm9tdmi_register_commands(cmd_ctx);
761
762 arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
763
764 register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
765 register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
766 register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
767 register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
768
769 register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
770 register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
771 register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
772
773 register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
774 register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
775 register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
776
777 register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
778 register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
779
780 return ERROR_OK;
781 }
782
783 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
784 {
785 target_t *target = get_current_target(cmd_ctx);
786 armv4_5_common_t *armv4_5;
787 arm7_9_common_t *arm7_9;
788 arm9tdmi_common_t *arm9tdmi;
789 arm920t_common_t *arm920t;
790 arm_jtag_t *jtag_info;
791 u32 cp15c15;
792 u32 cp15_ctrl, cp15_ctrl_saved;
793 u32 regs[16];
794 u32 *regs_p[16];
795 u32 C15_C_D_Ind, C15_C_I_Ind;
796 int i;
797 FILE *output;
798 arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
799 int segment, index;
800
801 if (argc != 1)
802 {
803 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
804 return ERROR_OK;
805 }
806
807 if ((output = fopen(args[0], "w")) == NULL)
808 {
809 LOG_DEBUG("error opening cache content file");
810 return ERROR_OK;
811 }
812
813 for (i = 0; i < 16; i++)
814 regs_p[i] = &regs[i];
815
816 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
817 {
818 command_print(cmd_ctx, "current target isn't an ARM920t target");
819 return ERROR_OK;
820 }
821
822 jtag_info = &arm7_9->jtag_info;
823
824 /* disable MMU and Caches */
825 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
826 jtag_execute_queue();
827 cp15_ctrl_saved = cp15_ctrl;
828 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
829 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
830
831 /* read CP15 test state register */
832 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
833 jtag_execute_queue();
834
835 /* read DCache content */
836 fprintf(output, "DCache:\n");
837
838 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
839 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
840 {
841 fprintf(output, "\nsegment: %i\n----------", segment);
842
843 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
844 regs[0] = 0x0 | (segment << 5);
845 arm9tdmi_write_core_regs(target, 0x1, regs);
846
847 /* set interpret mode */
848 cp15c15 |= 0x1;
849 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
850
851 /* D CAM Read, loads current victim into C15.C.D.Ind */
852 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
853
854 /* read current victim */
855 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
856
857 /* clear interpret mode */
858 cp15c15 &= ~0x1;
859 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
860
861 for (index = 0; index < 64; index++)
862 {
863 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
864 regs[0] = 0x0 | (segment << 5) | (index << 26);
865 arm9tdmi_write_core_regs(target, 0x1, regs);
866
867 /* set interpret mode */
868 cp15c15 |= 0x1;
869 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
870
871 /* Write DCache victim */
872 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
873
874 /* Read D RAM */
875 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
876
877 /* Read D CAM */
878 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
879
880 /* clear interpret mode */
881 cp15c15 &= ~0x1;
882 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
883
884 /* read D RAM and CAM content */
885 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
886 jtag_execute_queue();
887
888 d_cache[segment][index].cam = regs[9];
889
890 /* mask LFSR[6] */
891 regs[9] &= 0xfffffffe;
892 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
893
894 for (i = 1; i < 9; i++)
895 {
896 d_cache[segment][index].data[i] = regs[i];
897 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
898 }
899
900 }
901
902 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
903 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
904 arm9tdmi_write_core_regs(target, 0x1, regs);
905
906 /* set interpret mode */
907 cp15c15 |= 0x1;
908 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
909
910 /* Write DCache victim */
911 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
912
913 /* clear interpret mode */
914 cp15c15 &= ~0x1;
915 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
916 }
917
918 /* read ICache content */
919 fprintf(output, "ICache:\n");
920
921 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
922 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
923 {
924 fprintf(output, "segment: %i\n----------", segment);
925
926 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
927 regs[0] = 0x0 | (segment << 5);
928 arm9tdmi_write_core_regs(target, 0x1, regs);
929
930 /* set interpret mode */
931 cp15c15 |= 0x1;
932 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
933
934 /* I CAM Read, loads current victim into C15.C.I.Ind */
935 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
936
937 /* read current victim */
938 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
939
940 /* clear interpret mode */
941 cp15c15 &= ~0x1;
942 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
943
944 for (index = 0; index < 64; index++)
945 {
946 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
947 regs[0] = 0x0 | (segment << 5) | (index << 26);
948 arm9tdmi_write_core_regs(target, 0x1, regs);
949
950 /* set interpret mode */
951 cp15c15 |= 0x1;
952 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
953
954 /* Write ICache victim */
955 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
956
957 /* Read I RAM */
958 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
959
960 /* Read I CAM */
961 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
962
963 /* clear interpret mode */
964 cp15c15 &= ~0x1;
965 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
966
967 /* read I RAM and CAM content */
968 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
969 jtag_execute_queue();
970
971 i_cache[segment][index].cam = regs[9];
972
973 /* mask LFSR[6] */
974 regs[9] &= 0xfffffffe;
975 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
976
977 for (i = 1; i < 9; i++)
978 {
979 i_cache[segment][index].data[i] = regs[i];
980 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
981 }
982
983 }
984
985
986 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
987 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
988 arm9tdmi_write_core_regs(target, 0x1, regs);
989
990 /* set interpret mode */
991 cp15c15 |= 0x1;
992 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
993
994 /* Write ICache victim */
995 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
996
997 /* clear interpret mode */
998 cp15c15 &= ~0x1;
999 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1000 }
1001
1002 /* restore CP15 MMU and Cache settings */
1003 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1004
1005 command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
1006
1007 fclose(output);
1008
1009 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1010 return ERROR_FAIL;
1011
1012 /* mark registers dirty. */
1013 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1014 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1015 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1016 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1017 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1018 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1019 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1020 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1021 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1022 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1023
1024 return ERROR_OK;
1025 }
1026
1027 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1028 {
1029 target_t *target = get_current_target(cmd_ctx);
1030 armv4_5_common_t *armv4_5;
1031 arm7_9_common_t *arm7_9;
1032 arm9tdmi_common_t *arm9tdmi;
1033 arm920t_common_t *arm920t;
1034 arm_jtag_t *jtag_info;
1035 u32 cp15c15;
1036 u32 cp15_ctrl, cp15_ctrl_saved;
1037 u32 regs[16];
1038 u32 *regs_p[16];
1039 int i;
1040 FILE *output;
1041 u32 Dlockdown, Ilockdown;
1042 arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1043 int victim;
1044
1045 if (argc != 1)
1046 {
1047 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1048 return ERROR_OK;
1049 }
1050
1051 if ((output = fopen(args[0], "w")) == NULL)
1052 {
1053 LOG_DEBUG("error opening mmu content file");
1054 return ERROR_OK;
1055 }
1056
1057 for (i = 0; i < 16; i++)
1058 regs_p[i] = &regs[i];
1059
1060 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1061 {
1062 command_print(cmd_ctx, "current target isn't an ARM920t target");
1063 return ERROR_OK;
1064 }
1065
1066 jtag_info = &arm7_9->jtag_info;
1067
1068 /* disable MMU and Caches */
1069 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1070 jtag_execute_queue();
1071 cp15_ctrl_saved = cp15_ctrl;
1072 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1073 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1074
1075 /* read CP15 test state register */
1076 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1077 jtag_execute_queue();
1078
1079 /* prepare reading D TLB content
1080 * */
1081
1082 /* set interpret mode */
1083 cp15c15 |= 0x1;
1084 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1085
1086 /* Read D TLB lockdown */
1087 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1088
1089 /* clear interpret mode */
1090 cp15c15 &= ~0x1;
1091 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1092
1093 /* read D TLB lockdown stored to r1 */
1094 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1095 jtag_execute_queue();
1096 Dlockdown = regs[1];
1097
1098 for (victim = 0; victim < 64; victim += 8)
1099 {
1100 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1101 * base remains unchanged, victim goes through entries 0 to 63 */
1102 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1103 arm9tdmi_write_core_regs(target, 0x2, regs);
1104
1105 /* set interpret mode */
1106 cp15c15 |= 0x1;
1107 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1108
1109 /* Write D TLB lockdown */
1110 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1111
1112 /* Read D TLB CAM */
1113 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1114
1115 /* clear interpret mode */
1116 cp15c15 &= ~0x1;
1117 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1118
1119 /* read D TLB CAM content stored to r2-r9 */
1120 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1121 jtag_execute_queue();
1122
1123 for (i = 0; i < 8; i++)
1124 d_tlb[victim + i].cam = regs[i + 2];
1125 }
1126
1127 for (victim = 0; victim < 64; victim++)
1128 {
1129 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1130 * base remains unchanged, victim goes through entries 0 to 63 */
1131 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1132 arm9tdmi_write_core_regs(target, 0x2, regs);
1133
1134 /* set interpret mode */
1135 cp15c15 |= 0x1;
1136 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1137
1138 /* Write D TLB lockdown */
1139 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1140
1141 /* Read D TLB RAM1 */
1142 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1143
1144 /* Read D TLB RAM2 */
1145 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1146
1147 /* clear interpret mode */
1148 cp15c15 &= ~0x1;
1149 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1150
1151 /* read D TLB RAM content stored to r2 and r3 */
1152 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1153 jtag_execute_queue();
1154
1155 d_tlb[victim].ram1 = regs[2];
1156 d_tlb[victim].ram2 = regs[3];
1157 }
1158
1159 /* restore D TLB lockdown */
1160 regs[1] = Dlockdown;
1161 arm9tdmi_write_core_regs(target, 0x2, regs);
1162
1163 /* Write D TLB lockdown */
1164 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1165
1166 /* prepare reading I TLB content
1167 * */
1168
1169 /* set interpret mode */
1170 cp15c15 |= 0x1;
1171 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1172
1173 /* Read I TLB lockdown */
1174 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1175
1176 /* clear interpret mode */
1177 cp15c15 &= ~0x1;
1178 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1179
1180 /* read I TLB lockdown stored to r1 */
1181 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1182 jtag_execute_queue();
1183 Ilockdown = regs[1];
1184
1185 for (victim = 0; victim < 64; victim += 8)
1186 {
1187 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1188 * base remains unchanged, victim goes through entries 0 to 63 */
1189 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1190 arm9tdmi_write_core_regs(target, 0x2, regs);
1191
1192 /* set interpret mode */
1193 cp15c15 |= 0x1;
1194 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1195
1196 /* Write I TLB lockdown */
1197 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1198
1199 /* Read I TLB CAM */
1200 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1201
1202 /* clear interpret mode */
1203 cp15c15 &= ~0x1;
1204 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1205
1206 /* read I TLB CAM content stored to r2-r9 */
1207 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1208 jtag_execute_queue();
1209
1210 for (i = 0; i < 8; i++)
1211 i_tlb[i + victim].cam = regs[i + 2];
1212 }
1213
1214 for (victim = 0; victim < 64; victim++)
1215 {
1216 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1217 * base remains unchanged, victim goes through entries 0 to 63 */
1218 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1219 arm9tdmi_write_core_regs(target, 0x2, regs);
1220
1221 /* set interpret mode */
1222 cp15c15 |= 0x1;
1223 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1224
1225 /* Write I TLB lockdown */
1226 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1227
1228 /* Read I TLB RAM1 */
1229 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1230
1231 /* Read I TLB RAM2 */
1232 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1233
1234 /* clear interpret mode */
1235 cp15c15 &= ~0x1;
1236 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1237
1238 /* read I TLB RAM content stored to r2 and r3 */
1239 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1240 jtag_execute_queue();
1241
1242 i_tlb[victim].ram1 = regs[2];
1243 i_tlb[victim].ram2 = regs[3];
1244 }
1245
1246 /* restore I TLB lockdown */
1247 regs[1] = Ilockdown;
1248 arm9tdmi_write_core_regs(target, 0x2, regs);
1249
1250 /* Write I TLB lockdown */
1251 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1252
1253 /* restore CP15 MMU and Cache settings */
1254 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1255
1256 /* output data to file */
1257 fprintf(output, "D TLB content:\n");
1258 for (i = 0; i < 64; i++)
1259 {
1260 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1261 }
1262
1263 fprintf(output, "\n\nI TLB content:\n");
1264 for (i = 0; i < 64; i++)
1265 {
1266 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1267 }
1268
1269 command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1270
1271 fclose(output);
1272
1273 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1274 return ERROR_FAIL;
1275
1276 /* mark registers dirty */
1277 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1278 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1279 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1280 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1281 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1282 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1283 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1284 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1285 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1286 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1287
1288 return ERROR_OK;
1289 }
1290 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1291 {
1292 int retval;
1293 target_t *target = get_current_target(cmd_ctx);
1294 armv4_5_common_t *armv4_5;
1295 arm7_9_common_t *arm7_9;
1296 arm9tdmi_common_t *arm9tdmi;
1297 arm920t_common_t *arm920t;
1298 arm_jtag_t *jtag_info;
1299
1300 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1301 {
1302 command_print(cmd_ctx, "current target isn't an ARM920t target");
1303 return ERROR_OK;
1304 }
1305
1306 jtag_info = &arm7_9->jtag_info;
1307
1308 if (target->state != TARGET_HALTED)
1309 {
1310 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1311 return ERROR_OK;
1312 }
1313
1314 /* one or more argument, access a single register (write if second argument is given */
1315 if (argc >= 1)
1316 {
1317 int address = strtoul(args[0], NULL, 0);
1318
1319 if (argc == 1)
1320 {
1321 u32 value;
1322 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1323 {
1324 command_print(cmd_ctx, "couldn't access reg %i", address);
1325 return ERROR_OK;
1326 }
1327 jtag_execute_queue();
1328
1329 command_print(cmd_ctx, "%i: %8.8x", address, value);
1330 }
1331 else if (argc == 2)
1332 {
1333 u32 value = strtoul(args[1], NULL, 0);
1334 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1335 {
1336 command_print(cmd_ctx, "couldn't access reg %i", address);
1337 return ERROR_OK;
1338 }
1339 command_print(cmd_ctx, "%i: %8.8x", address, value);
1340 }
1341 }
1342
1343 return ERROR_OK;
1344 }
1345
1346 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1347 {
1348 int retval;
1349 target_t *target = get_current_target(cmd_ctx);
1350 armv4_5_common_t *armv4_5;
1351 arm7_9_common_t *arm7_9;
1352 arm9tdmi_common_t *arm9tdmi;
1353 arm920t_common_t *arm920t;
1354 arm_jtag_t *jtag_info;
1355
1356 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1357 {
1358 command_print(cmd_ctx, "current target isn't an ARM920t target");
1359 return ERROR_OK;
1360 }
1361
1362 jtag_info = &arm7_9->jtag_info;
1363
1364 if (target->state != TARGET_HALTED)
1365 {
1366 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1367 return ERROR_OK;
1368 }
1369
1370 /* one or more argument, access a single register (write if second argument is given */
1371 if (argc >= 1)
1372 {
1373 u32 opcode = strtoul(args[0], NULL, 0);
1374
1375 if (argc == 1)
1376 {
1377 u32 value;
1378 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1379 {
1380 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1381 return ERROR_OK;
1382 }
1383
1384 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1385 }
1386 else if (argc == 2)
1387 {
1388 u32 value = strtoul(args[1], NULL, 0);
1389 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1390 {
1391 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1392 return ERROR_OK;
1393 }
1394 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1395 }
1396 else if (argc == 3)
1397 {
1398 u32 value = strtoul(args[1], NULL, 0);
1399 u32 address = strtoul(args[2], NULL, 0);
1400 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1401 {
1402 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1403 return ERROR_OK;
1404 }
1405 command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1406 }
1407 }
1408 else
1409 {
1410 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1411 }
1412
1413 return ERROR_OK;
1414 }
1415
1416 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1417 {
1418 target_t *target = get_current_target(cmd_ctx);
1419 armv4_5_common_t *armv4_5;
1420 arm7_9_common_t *arm7_9;
1421 arm9tdmi_common_t *arm9tdmi;
1422 arm920t_common_t *arm920t;
1423
1424 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1425 {
1426 command_print(cmd_ctx, "current target isn't an ARM920t target");
1427 return ERROR_OK;
1428 }
1429
1430 return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1431 }
1432
1433 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1434 {
1435 target_t *target = get_current_target(cmd_ctx);
1436 armv4_5_common_t *armv4_5;
1437 arm7_9_common_t *arm7_9;
1438 arm9tdmi_common_t *arm9tdmi;
1439 arm920t_common_t *arm920t;
1440 arm_jtag_t *jtag_info;
1441
1442 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1443 {
1444 command_print(cmd_ctx, "current target isn't an ARM920t target");
1445 return ERROR_OK;
1446 }
1447
1448 jtag_info = &arm7_9->jtag_info;
1449
1450 if (target->state != TARGET_HALTED)
1451 {
1452 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1453 return ERROR_OK;
1454 }
1455
1456 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1457 }
1458
1459 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1460 {
1461 target_t *target = get_current_target(cmd_ctx);
1462 armv4_5_common_t *armv4_5;
1463 arm7_9_common_t *arm7_9;
1464 arm9tdmi_common_t *arm9tdmi;
1465 arm920t_common_t *arm920t;
1466 arm_jtag_t *jtag_info;
1467
1468 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1469 {
1470 command_print(cmd_ctx, "current target isn't an ARM920t target");
1471 return ERROR_OK;
1472 }
1473
1474 jtag_info = &arm7_9->jtag_info;
1475
1476 if (target->state != TARGET_HALTED)
1477 {
1478 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1479 return ERROR_OK;
1480 }
1481
1482 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1483 }
1484
1485 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1486 {
1487 target_t *target = get_current_target(cmd_ctx);
1488 armv4_5_common_t *armv4_5;
1489 arm7_9_common_t *arm7_9;
1490 arm9tdmi_common_t *arm9tdmi;
1491 arm920t_common_t *arm920t;
1492 arm_jtag_t *jtag_info;
1493
1494 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1495 {
1496 command_print(cmd_ctx, "current target isn't an ARM920t target");
1497 return ERROR_OK;
1498 }
1499
1500 jtag_info = &arm7_9->jtag_info;
1501
1502 if (target->state != TARGET_HALTED)
1503 {
1504 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1505 return ERROR_OK;
1506 }
1507
1508 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1509 }
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