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- rename log functions to stop conflicts under win32 (wingdi)
[openocd.git] / src / target / arm920t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm920t.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35 /* cli handling */
36 int arm920t_register_commands(struct command_context_s *cmd_ctx);
37
38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44
45 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm920t_quit();
52 int arm920t_arch_state(struct target_s *target);
53 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
54 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm920t_soft_reset_halt(struct target_s *target);
56
57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
58
59 target_type_t arm920t_target =
60 {
61 .name = "arm920t",
62
63 .poll = arm7_9_poll,
64 .arch_state = arm920t_arch_state,
65
66 .target_request_data = arm7_9_target_request_data,
67
68 .halt = arm7_9_halt,
69 .resume = arm7_9_resume,
70 .step = arm7_9_step,
71
72 .assert_reset = arm7_9_assert_reset,
73 .deassert_reset = arm7_9_deassert_reset,
74 .soft_reset_halt = arm920t_soft_reset_halt,
75 .prepare_reset_halt = arm7_9_prepare_reset_halt,
76
77 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
78
79 .read_memory = arm920t_read_memory,
80 .write_memory = arm920t_write_memory,
81 .bulk_write_memory = arm7_9_bulk_write_memory,
82 .checksum_memory = arm7_9_checksum_memory,
83
84 .run_algorithm = armv4_5_run_algorithm,
85
86 .add_breakpoint = arm7_9_add_breakpoint,
87 .remove_breakpoint = arm7_9_remove_breakpoint,
88 .add_watchpoint = arm7_9_add_watchpoint,
89 .remove_watchpoint = arm7_9_remove_watchpoint,
90
91 .register_commands = arm920t_register_commands,
92 .target_command = arm920t_target_command,
93 .init_target = arm920t_init_target,
94 .quit = arm920t_quit
95 };
96
97 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
98 {
99 armv4_5_common_t *armv4_5 = target->arch_info;
100 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
101 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
102 scan_field_t fields[4];
103 u8 access_type_buf = 1;
104 u8 reg_addr_buf = reg_addr & 0x3f;
105 u8 nr_w_buf = 0;
106
107 jtag_add_end_state(TAP_RTI);
108 arm_jtag_scann(jtag_info, 0xf);
109 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
110
111 fields[0].device = jtag_info->chain_pos;
112 fields[0].num_bits = 1;
113 fields[0].out_value = &access_type_buf;
114 fields[0].out_mask = NULL;
115 fields[0].in_value = NULL;
116 fields[0].in_check_value = NULL;
117 fields[0].in_check_mask = NULL;
118 fields[0].in_handler = NULL;
119 fields[0].in_handler_priv = NULL;
120
121 fields[1].device = jtag_info->chain_pos;
122 fields[1].num_bits = 32;
123 fields[1].out_value = NULL;
124 fields[1].out_mask = NULL;
125 fields[1].in_value = NULL;
126 fields[1].in_check_value = NULL;
127 fields[1].in_check_mask = NULL;
128 fields[1].in_handler = NULL;
129 fields[1].in_handler_priv = NULL;
130
131 fields[2].device = jtag_info->chain_pos;
132 fields[2].num_bits = 6;
133 fields[2].out_value = &reg_addr_buf;
134 fields[2].out_mask = NULL;
135 fields[2].in_value = NULL;
136 fields[2].in_check_value = NULL;
137 fields[2].in_check_mask = NULL;
138 fields[2].in_handler = NULL;
139 fields[2].in_handler_priv = NULL;
140
141 fields[3].device = jtag_info->chain_pos;
142 fields[3].num_bits = 1;
143 fields[3].out_value = &nr_w_buf;
144 fields[3].out_mask = NULL;
145 fields[3].in_value = NULL;
146 fields[3].in_check_value = NULL;
147 fields[3].in_check_mask = NULL;
148 fields[3].in_handler = NULL;
149 fields[3].in_handler_priv = NULL;
150
151 jtag_add_dr_scan(4, fields, -1);
152
153 fields[1].in_handler_priv = value;
154 fields[1].in_handler = arm_jtag_buf_to_u32;
155
156 jtag_add_dr_scan(4, fields, -1);
157
158 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
159 jtag_execute_queue();
160 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
161 #endif
162
163 return ERROR_OK;
164 }
165
166 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
167 {
168 armv4_5_common_t *armv4_5 = target->arch_info;
169 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
170 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
171 scan_field_t fields[4];
172 u8 access_type_buf = 1;
173 u8 reg_addr_buf = reg_addr & 0x3f;
174 u8 nr_w_buf = 1;
175 u8 value_buf[4];
176
177 buf_set_u32(value_buf, 0, 32, value);
178
179 jtag_add_end_state(TAP_RTI);
180 arm_jtag_scann(jtag_info, 0xf);
181 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
182
183 fields[0].device = jtag_info->chain_pos;
184 fields[0].num_bits = 1;
185 fields[0].out_value = &access_type_buf;
186 fields[0].out_mask = NULL;
187 fields[0].in_value = NULL;
188 fields[0].in_check_value = NULL;
189 fields[0].in_check_mask = NULL;
190 fields[0].in_handler = NULL;
191 fields[0].in_handler_priv = NULL;
192
193 fields[1].device = jtag_info->chain_pos;
194 fields[1].num_bits = 32;
195 fields[1].out_value = value_buf;
196 fields[1].out_mask = NULL;
197 fields[1].in_value = NULL;
198 fields[1].in_check_value = NULL;
199 fields[1].in_check_mask = NULL;
200 fields[1].in_handler = NULL;
201 fields[1].in_handler_priv = NULL;
202
203 fields[2].device = jtag_info->chain_pos;
204 fields[2].num_bits = 6;
205 fields[2].out_value = &reg_addr_buf;
206 fields[2].out_mask = NULL;
207 fields[2].in_value = NULL;
208 fields[2].in_check_value = NULL;
209 fields[2].in_check_mask = NULL;
210 fields[2].in_handler = NULL;
211 fields[2].in_handler_priv = NULL;
212
213 fields[3].device = jtag_info->chain_pos;
214 fields[3].num_bits = 1;
215 fields[3].out_value = &nr_w_buf;
216 fields[3].out_mask = NULL;
217 fields[3].in_value = NULL;
218 fields[3].in_check_value = NULL;
219 fields[3].in_check_mask = NULL;
220 fields[3].in_handler = NULL;
221 fields[3].in_handler_priv = NULL;
222
223 jtag_add_dr_scan(4, fields, -1);
224
225 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
226 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
227 #endif
228
229 return ERROR_OK;
230 }
231
232 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
233 {
234 armv4_5_common_t *armv4_5 = target->arch_info;
235 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
236 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
237 scan_field_t fields[4];
238 u8 access_type_buf = 0; /* interpreted access */
239 u8 reg_addr_buf = 0x0;
240 u8 nr_w_buf = 0;
241 u8 cp15_opcode_buf[4];
242
243 jtag_add_end_state(TAP_RTI);
244 arm_jtag_scann(jtag_info, 0xf);
245 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
246
247 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
248
249 fields[0].device = jtag_info->chain_pos;
250 fields[0].num_bits = 1;
251 fields[0].out_value = &access_type_buf;
252 fields[0].out_mask = NULL;
253 fields[0].in_value = NULL;
254 fields[0].in_check_value = NULL;
255 fields[0].in_check_mask = NULL;
256 fields[0].in_handler = NULL;
257 fields[0].in_handler_priv = NULL;
258
259 fields[1].device = jtag_info->chain_pos;
260 fields[1].num_bits = 32;
261 fields[1].out_value = cp15_opcode_buf;
262 fields[1].out_mask = NULL;
263 fields[1].in_value = NULL;
264 fields[1].in_check_value = NULL;
265 fields[1].in_check_mask = NULL;
266 fields[1].in_handler = NULL;
267 fields[1].in_handler_priv = NULL;
268
269 fields[2].device = jtag_info->chain_pos;
270 fields[2].num_bits = 6;
271 fields[2].out_value = &reg_addr_buf;
272 fields[2].out_mask = NULL;
273 fields[2].in_value = NULL;
274 fields[2].in_check_value = NULL;
275 fields[2].in_check_mask = NULL;
276 fields[2].in_handler = NULL;
277 fields[2].in_handler_priv = NULL;
278
279 fields[3].device = jtag_info->chain_pos;
280 fields[3].num_bits = 1;
281 fields[3].out_value = &nr_w_buf;
282 fields[3].out_mask = NULL;
283 fields[3].in_value = NULL;
284 fields[3].in_check_value = NULL;
285 fields[3].in_check_mask = NULL;
286 fields[3].in_handler = NULL;
287 fields[3].in_handler_priv = NULL;
288
289 jtag_add_dr_scan(4, fields, -1);
290
291 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
292 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
293 arm7_9_execute_sys_speed(target);
294
295 if (jtag_execute_queue() != ERROR_OK)
296 {
297 LOG_ERROR("failed executing JTAG queue, exiting");
298 exit(-1);
299 }
300
301 return ERROR_OK;
302 }
303
304 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
305 {
306 armv4_5_common_t *armv4_5 = target->arch_info;
307 u32* regs_p[1];
308 u32 regs[2];
309 u32 cp15c15 = 0x0;
310
311 /* load address into R1 */
312 regs[1] = address;
313 arm9tdmi_write_core_regs(target, 0x2, regs);
314
315 /* read-modify-write CP15 test state register
316 * to enable interpreted access mode */
317 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
318 jtag_execute_queue();
319 cp15c15 |= 1; /* set interpret mode */
320 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
321
322 /* execute CP15 instruction and ARM load (reading from coprocessor) */
323 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
324
325 /* disable interpreted access mode */
326 cp15c15 &= ~1U; /* clear interpret mode */
327 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
328
329 /* retrieve value from R0 */
330 regs_p[0] = value;
331 arm9tdmi_read_core_regs(target, 0x1, regs_p);
332 jtag_execute_queue();
333
334 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
335 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
336 #endif
337
338 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
339 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
340
341 return ERROR_OK;
342 }
343
344 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
345 {
346 u32 cp15c15 = 0x0;
347 armv4_5_common_t *armv4_5 = target->arch_info;
348 u32 regs[2];
349
350 /* load value, address into R0, R1 */
351 regs[0] = value;
352 regs[1] = address;
353 arm9tdmi_write_core_regs(target, 0x3, regs);
354
355 /* read-modify-write CP15 test state register
356 * to enable interpreted access mode */
357 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
358 jtag_execute_queue();
359 cp15c15 |= 1; /* set interpret mode */
360 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
361
362 /* execute CP15 instruction and ARM store (writing to coprocessor) */
363 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
364
365 /* disable interpreted access mode */
366 cp15c15 &= ~1U; /* set interpret mode */
367 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
368
369 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
370 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
371 #endif
372
373 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
374 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
375
376 return ERROR_OK;
377 }
378
379 u32 arm920t_get_ttb(target_t *target)
380 {
381 int retval;
382 u32 ttb = 0x0;
383
384 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
385 return retval;
386
387 return ttb;
388 }
389
390 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
391 {
392 u32 cp15_control;
393
394 /* read cp15 control register */
395 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
396 jtag_execute_queue();
397
398 if (mmu)
399 cp15_control &= ~0x1U;
400
401 if (d_u_cache)
402 cp15_control &= ~0x4U;
403
404 if (i_cache)
405 cp15_control &= ~0x1000U;
406
407 arm920t_write_cp15_physical(target, 0x2, cp15_control);
408 }
409
410 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
411 {
412 u32 cp15_control;
413
414 /* read cp15 control register */
415 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
416 jtag_execute_queue();
417
418 if (mmu)
419 cp15_control |= 0x1U;
420
421 if (d_u_cache)
422 cp15_control |= 0x4U;
423
424 if (i_cache)
425 cp15_control |= 0x1000U;
426
427 arm920t_write_cp15_physical(target, 0x2, cp15_control);
428 }
429
430 void arm920t_post_debug_entry(target_t *target)
431 {
432 u32 cp15c15;
433 armv4_5_common_t *armv4_5 = target->arch_info;
434 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
435 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
436 arm920t_common_t *arm920t = arm9tdmi->arch_info;
437
438 /* examine cp15 control reg */
439 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
440 jtag_execute_queue();
441 LOG_DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
442
443 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
444 {
445 u32 cache_type_reg;
446 /* identify caches */
447 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
448 jtag_execute_queue();
449 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
450 }
451
452 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
453 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
454 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
455
456 /* save i/d fault status and address register */
457 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
458 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
459 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
460 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
461
462 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
463 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
464
465 if (arm920t->preserve_cache)
466 {
467 /* read-modify-write CP15 test state register
468 * to disable I/D-cache linefills */
469 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
470 jtag_execute_queue();
471 cp15c15 |= 0x600;
472 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
473 }
474 }
475
476 void arm920t_pre_restore_context(target_t *target)
477 {
478 u32 cp15c15;
479 armv4_5_common_t *armv4_5 = target->arch_info;
480 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
481 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
482 arm920t_common_t *arm920t = arm9tdmi->arch_info;
483
484 /* restore i/d fault status and address register */
485 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
486 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
487 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
488 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
489
490 /* read-modify-write CP15 test state register
491 * to reenable I/D-cache linefills */
492 if (arm920t->preserve_cache)
493 {
494 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
495 jtag_execute_queue();
496 cp15c15 &= ~0x600U;
497 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
498 }
499 }
500
501 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
502 {
503 armv4_5_common_t *armv4_5 = target->arch_info;
504 arm7_9_common_t *arm7_9;
505 arm9tdmi_common_t *arm9tdmi;
506 arm920t_common_t *arm920t;
507
508 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
509 {
510 return -1;
511 }
512
513 arm7_9 = armv4_5->arch_info;
514 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
515 {
516 return -1;
517 }
518
519 arm9tdmi = arm7_9->arch_info;
520 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
521 {
522 return -1;
523 }
524
525 arm920t = arm9tdmi->arch_info;
526 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
527 {
528 return -1;
529 }
530
531 *armv4_5_p = armv4_5;
532 *arm7_9_p = arm7_9;
533 *arm9tdmi_p = arm9tdmi;
534 *arm920t_p = arm920t;
535
536 return ERROR_OK;
537 }
538
539 int arm920t_arch_state(struct target_s *target)
540 {
541 armv4_5_common_t *armv4_5 = target->arch_info;
542 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
543 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
544 arm920t_common_t *arm920t = arm9tdmi->arch_info;
545
546 char *state[] =
547 {
548 "disabled", "enabled"
549 };
550
551 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
552 {
553 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
554 exit(-1);
555 }
556
557 LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
558 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
559 "MMU: %s, D-Cache: %s, I-Cache: %s",
560 armv4_5_state_strings[armv4_5->core_state],
561 target_debug_reason_strings[target->debug_reason],
562 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
563 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
564 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
565 state[arm920t->armv4_5_mmu.mmu_enabled],
566 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
567 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
568
569 return ERROR_OK;
570 }
571
572 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
573 {
574 int retval;
575
576 retval = arm7_9_read_memory(target, address, size, count, buffer);
577
578 return retval;
579 }
580
581 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
582 {
583 int retval;
584 armv4_5_common_t *armv4_5 = target->arch_info;
585 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
586 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
587 arm920t_common_t *arm920t = arm9tdmi->arch_info;
588
589 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
590 return retval;
591
592 if (((size == 4) || (size == 2)) && (count == 1))
593 {
594 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
595 {
596 LOG_DEBUG("D-Cache enabled, writing through to main memory");
597 u32 pa, cb, ap;
598 int type, domain;
599
600 pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
601 if (type == -1)
602 return ERROR_OK;
603 /* cacheable & bufferable means write-back region */
604 if (cb == 3)
605 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
606 }
607
608 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
609 {
610 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
611 arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
612 }
613 }
614
615 return retval;
616 }
617
618 int arm920t_soft_reset_halt(struct target_s *target)
619 {
620 armv4_5_common_t *armv4_5 = target->arch_info;
621 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
622 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
623 arm920t_common_t *arm920t = arm9tdmi->arch_info;
624 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
625
626 target->type->halt(target);
627
628 while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
629 {
630 embeddedice_read_reg(dbg_stat);
631 jtag_execute_queue();
632 }
633
634 target->state = TARGET_HALTED;
635
636 /* SVC, ARM state, IRQ and FIQ disabled */
637 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
638 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
639 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
640
641 /* start fetching from 0x0 */
642 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
643 armv4_5->core_cache->reg_list[15].dirty = 1;
644 armv4_5->core_cache->reg_list[15].valid = 1;
645
646 armv4_5->core_mode = ARMV4_5_MODE_SVC;
647 armv4_5->core_state = ARMV4_5_STATE_ARM;
648
649 arm920t_disable_mmu_caches(target, 1, 1, 1);
650 arm920t->armv4_5_mmu.mmu_enabled = 0;
651 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
652 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
653
654 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
655
656 return ERROR_OK;
657 }
658
659 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
660 {
661 arm9tdmi_init_target(cmd_ctx, target);
662
663 return ERROR_OK;
664
665 }
666
667 int arm920t_quit()
668 {
669
670 return ERROR_OK;
671 }
672
673 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)
674 {
675 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
676 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
677
678 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
679 */
680 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
681
682 arm9tdmi->arch_info = arm920t;
683 arm920t->common_magic = ARM920T_COMMON_MAGIC;
684
685 arm7_9->post_debug_entry = arm920t_post_debug_entry;
686 arm7_9->pre_restore_context = arm920t_pre_restore_context;
687
688 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
689 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
690 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
691 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
692 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
693 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
694 arm920t->armv4_5_mmu.has_tiny_pages = 1;
695 arm920t->armv4_5_mmu.mmu_enabled = 0;
696
697 /* disabling linefills leads to lockups, so keep them enabled for now
698 * this doesn't affect correctness, but might affect timing issues, if
699 * important data is evicted from the cache during the debug session
700 * */
701 arm920t->preserve_cache = 0;
702
703 /* override hw single-step capability from ARM9TDMI */
704 arm7_9->has_single_step = 1;
705
706 return ERROR_OK;
707 }
708
709 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
710 {
711 int chain_pos;
712 char *variant = NULL;
713 arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
714 memset(arm920t, 0, sizeof(*arm920t));
715
716 if (argc < 4)
717 {
718 LOG_ERROR("'target arm920t' requires at least one additional argument");
719 exit(-1);
720 }
721
722 chain_pos = strtoul(args[3], NULL, 0);
723
724 if (argc >= 5)
725 variant = args[4];
726
727 LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
728
729 arm920t_init_arch_info(target, arm920t, chain_pos, variant);
730
731 return ERROR_OK;
732 }
733
734 int arm920t_register_commands(struct command_context_s *cmd_ctx)
735 {
736 int retval;
737 command_t *arm920t_cmd;
738
739
740 retval = arm9tdmi_register_commands(cmd_ctx);
741
742 arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
743
744 register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
745 register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
746 register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
747 register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
748
749 register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
750 register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
751 register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
752
753 register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
754 register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
755 register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
756
757 register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
758 register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
759
760 return ERROR_OK;
761 }
762
763 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
764 {
765 target_t *target = get_current_target(cmd_ctx);
766 armv4_5_common_t *armv4_5;
767 arm7_9_common_t *arm7_9;
768 arm9tdmi_common_t *arm9tdmi;
769 arm920t_common_t *arm920t;
770 arm_jtag_t *jtag_info;
771 u32 cp15c15;
772 u32 cp15_ctrl, cp15_ctrl_saved;
773 u32 regs[16];
774 u32 *regs_p[16];
775 u32 C15_C_D_Ind, C15_C_I_Ind;
776 int i;
777 FILE *output;
778 arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
779 int segment, index;
780
781 if (argc != 1)
782 {
783 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
784 return ERROR_OK;
785 }
786
787 if ((output = fopen(args[0], "w")) == NULL)
788 {
789 LOG_DEBUG("error opening cache content file");
790 return ERROR_OK;
791 }
792
793 for (i = 0; i < 16; i++)
794 regs_p[i] = &regs[i];
795
796 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
797 {
798 command_print(cmd_ctx, "current target isn't an ARM920t target");
799 return ERROR_OK;
800 }
801
802 jtag_info = &arm7_9->jtag_info;
803
804 /* disable MMU and Caches */
805 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
806 jtag_execute_queue();
807 cp15_ctrl_saved = cp15_ctrl;
808 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
809 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
810
811 /* read CP15 test state register */
812 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
813 jtag_execute_queue();
814
815 /* read DCache content */
816 fprintf(output, "DCache:\n");
817
818 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
819 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
820 {
821 fprintf(output, "\nsegment: %i\n----------", segment);
822
823 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
824 regs[0] = 0x0 | (segment << 5);
825 arm9tdmi_write_core_regs(target, 0x1, regs);
826
827 /* set interpret mode */
828 cp15c15 |= 0x1;
829 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
830
831 /* D CAM Read, loads current victim into C15.C.D.Ind */
832 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
833
834 /* read current victim */
835 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
836
837 /* clear interpret mode */
838 cp15c15 &= ~0x1;
839 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
840
841 for (index = 0; index < 64; index++)
842 {
843 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
844 regs[0] = 0x0 | (segment << 5) | (index << 26);
845 arm9tdmi_write_core_regs(target, 0x1, regs);
846
847 /* set interpret mode */
848 cp15c15 |= 0x1;
849 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
850
851 /* Write DCache victim */
852 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
853
854 /* Read D RAM */
855 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
856
857 /* Read D CAM */
858 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
859
860 /* clear interpret mode */
861 cp15c15 &= ~0x1;
862 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
863
864 /* read D RAM and CAM content */
865 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
866 jtag_execute_queue();
867
868 d_cache[segment][index].cam = regs[9];
869
870 /* mask LFSR[6] */
871 regs[9] &= 0xfffffffe;
872 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
873
874 for (i = 1; i < 9; i++)
875 {
876 d_cache[segment][index].data[i] = regs[i];
877 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
878 }
879
880 }
881
882 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
883 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
884 arm9tdmi_write_core_regs(target, 0x1, regs);
885
886 /* set interpret mode */
887 cp15c15 |= 0x1;
888 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
889
890 /* Write DCache victim */
891 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
892
893 /* clear interpret mode */
894 cp15c15 &= ~0x1;
895 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
896 }
897
898 /* read ICache content */
899 fprintf(output, "ICache:\n");
900
901 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
902 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
903 {
904 fprintf(output, "segment: %i\n----------", segment);
905
906 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
907 regs[0] = 0x0 | (segment << 5);
908 arm9tdmi_write_core_regs(target, 0x1, regs);
909
910 /* set interpret mode */
911 cp15c15 |= 0x1;
912 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
913
914 /* I CAM Read, loads current victim into C15.C.I.Ind */
915 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
916
917 /* read current victim */
918 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
919
920 /* clear interpret mode */
921 cp15c15 &= ~0x1;
922 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
923
924 for (index = 0; index < 64; index++)
925 {
926 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
927 regs[0] = 0x0 | (segment << 5) | (index << 26);
928 arm9tdmi_write_core_regs(target, 0x1, regs);
929
930 /* set interpret mode */
931 cp15c15 |= 0x1;
932 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
933
934 /* Write ICache victim */
935 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
936
937 /* Read I RAM */
938 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
939
940 /* Read I CAM */
941 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
942
943 /* clear interpret mode */
944 cp15c15 &= ~0x1;
945 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
946
947 /* read I RAM and CAM content */
948 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
949 jtag_execute_queue();
950
951 i_cache[segment][index].cam = regs[9];
952
953 /* mask LFSR[6] */
954 regs[9] &= 0xfffffffe;
955 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
956
957 for (i = 1; i < 9; i++)
958 {
959 i_cache[segment][index].data[i] = regs[i];
960 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
961 }
962
963 }
964
965
966 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
967 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
968 arm9tdmi_write_core_regs(target, 0x1, regs);
969
970 /* set interpret mode */
971 cp15c15 |= 0x1;
972 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
973
974 /* Write ICache victim */
975 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
976
977 /* clear interpret mode */
978 cp15c15 &= ~0x1;
979 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
980 }
981
982 /* restore CP15 MMU and Cache settings */
983 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
984
985 command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
986
987 fclose(output);
988
989 /* mark registers dirty. */
990 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
991 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
992 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
993 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
994 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
995 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
996 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
997 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
998 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
999 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1000
1001 return ERROR_OK;
1002 }
1003
1004 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1005 {
1006 target_t *target = get_current_target(cmd_ctx);
1007 armv4_5_common_t *armv4_5;
1008 arm7_9_common_t *arm7_9;
1009 arm9tdmi_common_t *arm9tdmi;
1010 arm920t_common_t *arm920t;
1011 arm_jtag_t *jtag_info;
1012 u32 cp15c15;
1013 u32 cp15_ctrl, cp15_ctrl_saved;
1014 u32 regs[16];
1015 u32 *regs_p[16];
1016 int i;
1017 FILE *output;
1018 u32 Dlockdown, Ilockdown;
1019 arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1020 int victim;
1021
1022 if (argc != 1)
1023 {
1024 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1025 return ERROR_OK;
1026 }
1027
1028 if ((output = fopen(args[0], "w")) == NULL)
1029 {
1030 LOG_DEBUG("error opening mmu content file");
1031 return ERROR_OK;
1032 }
1033
1034 for (i = 0; i < 16; i++)
1035 regs_p[i] = &regs[i];
1036
1037 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1038 {
1039 command_print(cmd_ctx, "current target isn't an ARM920t target");
1040 return ERROR_OK;
1041 }
1042
1043 jtag_info = &arm7_9->jtag_info;
1044
1045 /* disable MMU and Caches */
1046 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1047 jtag_execute_queue();
1048 cp15_ctrl_saved = cp15_ctrl;
1049 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1050 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1051
1052 /* read CP15 test state register */
1053 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1054 jtag_execute_queue();
1055
1056 /* prepare reading D TLB content
1057 * */
1058
1059 /* set interpret mode */
1060 cp15c15 |= 0x1;
1061 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1062
1063 /* Read D TLB lockdown */
1064 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1065
1066 /* clear interpret mode */
1067 cp15c15 &= ~0x1;
1068 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1069
1070 /* read D TLB lockdown stored to r1 */
1071 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1072 jtag_execute_queue();
1073 Dlockdown = regs[1];
1074
1075 for (victim = 0; victim < 64; victim += 8)
1076 {
1077 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1078 * base remains unchanged, victim goes through entries 0 to 63 */
1079 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1080 arm9tdmi_write_core_regs(target, 0x2, regs);
1081
1082 /* set interpret mode */
1083 cp15c15 |= 0x1;
1084 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1085
1086 /* Write D TLB lockdown */
1087 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1088
1089 /* Read D TLB CAM */
1090 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1091
1092 /* clear interpret mode */
1093 cp15c15 &= ~0x1;
1094 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1095
1096 /* read D TLB CAM content stored to r2-r9 */
1097 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1098 jtag_execute_queue();
1099
1100 for (i = 0; i < 8; i++)
1101 d_tlb[victim + i].cam = regs[i + 2];
1102 }
1103
1104 for (victim = 0; victim < 64; victim++)
1105 {
1106 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1107 * base remains unchanged, victim goes through entries 0 to 63 */
1108 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1109 arm9tdmi_write_core_regs(target, 0x2, regs);
1110
1111 /* set interpret mode */
1112 cp15c15 |= 0x1;
1113 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1114
1115 /* Write D TLB lockdown */
1116 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1117
1118 /* Read D TLB RAM1 */
1119 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1120
1121 /* Read D TLB RAM2 */
1122 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1123
1124 /* clear interpret mode */
1125 cp15c15 &= ~0x1;
1126 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1127
1128 /* read D TLB RAM content stored to r2 and r3 */
1129 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1130 jtag_execute_queue();
1131
1132 d_tlb[victim].ram1 = regs[2];
1133 d_tlb[victim].ram2 = regs[3];
1134 }
1135
1136 /* restore D TLB lockdown */
1137 regs[1] = Dlockdown;
1138 arm9tdmi_write_core_regs(target, 0x2, regs);
1139
1140 /* Write D TLB lockdown */
1141 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1142
1143 /* prepare reading I TLB content
1144 * */
1145
1146 /* set interpret mode */
1147 cp15c15 |= 0x1;
1148 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1149
1150 /* Read I TLB lockdown */
1151 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1152
1153 /* clear interpret mode */
1154 cp15c15 &= ~0x1;
1155 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1156
1157 /* read I TLB lockdown stored to r1 */
1158 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1159 jtag_execute_queue();
1160 Ilockdown = regs[1];
1161
1162 for (victim = 0; victim < 64; victim += 8)
1163 {
1164 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1165 * base remains unchanged, victim goes through entries 0 to 63 */
1166 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1167 arm9tdmi_write_core_regs(target, 0x2, regs);
1168
1169 /* set interpret mode */
1170 cp15c15 |= 0x1;
1171 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1172
1173 /* Write I TLB lockdown */
1174 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1175
1176 /* Read I TLB CAM */
1177 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1178
1179 /* clear interpret mode */
1180 cp15c15 &= ~0x1;
1181 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1182
1183 /* read I TLB CAM content stored to r2-r9 */
1184 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1185 jtag_execute_queue();
1186
1187 for (i = 0; i < 8; i++)
1188 i_tlb[i + victim].cam = regs[i + 2];
1189 }
1190
1191 for (victim = 0; victim < 64; victim++)
1192 {
1193 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1194 * base remains unchanged, victim goes through entries 0 to 63 */
1195 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1196 arm9tdmi_write_core_regs(target, 0x2, regs);
1197
1198 /* set interpret mode */
1199 cp15c15 |= 0x1;
1200 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1201
1202 /* Write I TLB lockdown */
1203 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1204
1205 /* Read I TLB RAM1 */
1206 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1207
1208 /* Read I TLB RAM2 */
1209 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1210
1211 /* clear interpret mode */
1212 cp15c15 &= ~0x1;
1213 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1214
1215 /* read I TLB RAM content stored to r2 and r3 */
1216 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1217 jtag_execute_queue();
1218
1219 i_tlb[victim].ram1 = regs[2];
1220 i_tlb[victim].ram2 = regs[3];
1221 }
1222
1223 /* restore I TLB lockdown */
1224 regs[1] = Ilockdown;
1225 arm9tdmi_write_core_regs(target, 0x2, regs);
1226
1227 /* Write I TLB lockdown */
1228 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1229
1230 /* restore CP15 MMU and Cache settings */
1231 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1232
1233 /* output data to file */
1234 fprintf(output, "D TLB content:\n");
1235 for (i = 0; i < 64; i++)
1236 {
1237 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1238 }
1239
1240 fprintf(output, "\n\nI TLB content:\n");
1241 for (i = 0; i < 64; i++)
1242 {
1243 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1244 }
1245
1246 command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1247
1248 fclose(output);
1249
1250 /* mark registers dirty */
1251 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1252 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1253 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1254 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1255 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1256 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1257 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1258 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1259 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1260 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1261
1262 return ERROR_OK;
1263 }
1264 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1265 {
1266 int retval;
1267 target_t *target = get_current_target(cmd_ctx);
1268 armv4_5_common_t *armv4_5;
1269 arm7_9_common_t *arm7_9;
1270 arm9tdmi_common_t *arm9tdmi;
1271 arm920t_common_t *arm920t;
1272 arm_jtag_t *jtag_info;
1273
1274 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1275 {
1276 command_print(cmd_ctx, "current target isn't an ARM920t target");
1277 return ERROR_OK;
1278 }
1279
1280 jtag_info = &arm7_9->jtag_info;
1281
1282 if (target->state != TARGET_HALTED)
1283 {
1284 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1285 return ERROR_OK;
1286 }
1287
1288 /* one or more argument, access a single register (write if second argument is given */
1289 if (argc >= 1)
1290 {
1291 int address = strtoul(args[0], NULL, 0);
1292
1293 if (argc == 1)
1294 {
1295 u32 value;
1296 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1297 {
1298 command_print(cmd_ctx, "couldn't access reg %i", address);
1299 return ERROR_OK;
1300 }
1301 jtag_execute_queue();
1302
1303 command_print(cmd_ctx, "%i: %8.8x", address, value);
1304 }
1305 else if (argc == 2)
1306 {
1307 u32 value = strtoul(args[1], NULL, 0);
1308 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1309 {
1310 command_print(cmd_ctx, "couldn't access reg %i", address);
1311 return ERROR_OK;
1312 }
1313 command_print(cmd_ctx, "%i: %8.8x", address, value);
1314 }
1315 }
1316
1317 return ERROR_OK;
1318 }
1319
1320 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1321 {
1322 int retval;
1323 target_t *target = get_current_target(cmd_ctx);
1324 armv4_5_common_t *armv4_5;
1325 arm7_9_common_t *arm7_9;
1326 arm9tdmi_common_t *arm9tdmi;
1327 arm920t_common_t *arm920t;
1328 arm_jtag_t *jtag_info;
1329
1330 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1331 {
1332 command_print(cmd_ctx, "current target isn't an ARM920t target");
1333 return ERROR_OK;
1334 }
1335
1336 jtag_info = &arm7_9->jtag_info;
1337
1338 if (target->state != TARGET_HALTED)
1339 {
1340 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1341 return ERROR_OK;
1342 }
1343
1344 /* one or more argument, access a single register (write if second argument is given */
1345 if (argc >= 1)
1346 {
1347 u32 opcode = strtoul(args[0], NULL, 0);
1348
1349 if (argc == 1)
1350 {
1351 u32 value;
1352 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1353 {
1354 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1355 return ERROR_OK;
1356 }
1357
1358 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1359 }
1360 else if (argc == 2)
1361 {
1362 u32 value = strtoul(args[1], NULL, 0);
1363 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1364 {
1365 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1366 return ERROR_OK;
1367 }
1368 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1369 }
1370 else if (argc == 3)
1371 {
1372 u32 value = strtoul(args[1], NULL, 0);
1373 u32 address = strtoul(args[2], NULL, 0);
1374 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1375 {
1376 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1377 return ERROR_OK;
1378 }
1379 command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1380 }
1381 }
1382 else
1383 {
1384 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1385 }
1386
1387 return ERROR_OK;
1388 }
1389
1390 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1391 {
1392 target_t *target = get_current_target(cmd_ctx);
1393 armv4_5_common_t *armv4_5;
1394 arm7_9_common_t *arm7_9;
1395 arm9tdmi_common_t *arm9tdmi;
1396 arm920t_common_t *arm920t;
1397
1398 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1399 {
1400 command_print(cmd_ctx, "current target isn't an ARM920t target");
1401 return ERROR_OK;
1402 }
1403
1404 return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1405 }
1406
1407 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1408 {
1409 target_t *target = get_current_target(cmd_ctx);
1410 armv4_5_common_t *armv4_5;
1411 arm7_9_common_t *arm7_9;
1412 arm9tdmi_common_t *arm9tdmi;
1413 arm920t_common_t *arm920t;
1414 arm_jtag_t *jtag_info;
1415
1416 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1417 {
1418 command_print(cmd_ctx, "current target isn't an ARM920t target");
1419 return ERROR_OK;
1420 }
1421
1422 jtag_info = &arm7_9->jtag_info;
1423
1424 if (target->state != TARGET_HALTED)
1425 {
1426 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1427 return ERROR_OK;
1428 }
1429
1430 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1431 }
1432
1433 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1434 {
1435 target_t *target = get_current_target(cmd_ctx);
1436 armv4_5_common_t *armv4_5;
1437 arm7_9_common_t *arm7_9;
1438 arm9tdmi_common_t *arm9tdmi;
1439 arm920t_common_t *arm920t;
1440 arm_jtag_t *jtag_info;
1441
1442 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1443 {
1444 command_print(cmd_ctx, "current target isn't an ARM920t target");
1445 return ERROR_OK;
1446 }
1447
1448 jtag_info = &arm7_9->jtag_info;
1449
1450 if (target->state != TARGET_HALTED)
1451 {
1452 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1453 return ERROR_OK;
1454 }
1455
1456 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1457 }
1458
1459 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1460 {
1461 target_t *target = get_current_target(cmd_ctx);
1462 armv4_5_common_t *armv4_5;
1463 arm7_9_common_t *arm7_9;
1464 arm9tdmi_common_t *arm9tdmi;
1465 arm920t_common_t *arm920t;
1466 arm_jtag_t *jtag_info;
1467
1468 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1469 {
1470 command_print(cmd_ctx, "current target isn't an ARM920t target");
1471 return ERROR_OK;
1472 }
1473
1474 jtag_info = &arm7_9->jtag_info;
1475
1476 if (target->state != TARGET_HALTED)
1477 {
1478 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1479 return ERROR_OK;
1480 }
1481
1482 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1483 }
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