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- fix incorrect parsing of whitespace in command.c (thanks to Magnus Lundin)
[openocd.git] / src / target / arm920t.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm920t.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 0
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35 /* cli handling */
36 int arm920t_register_commands(struct command_context_s *cmd_ctx);
37
38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44
45 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm920t_quit();
52 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size);
53 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
54 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm920t_soft_reset_halt(struct target_s *target);
56
57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
58
59 target_type_t arm920t_target =
60 {
61 .name = "arm920t",
62
63 .poll = arm7_9_poll,
64 .arch_state = arm920t_arch_state,
65
66 .halt = arm7_9_halt,
67 .resume = arm7_9_resume,
68 .step = arm7_9_step,
69
70 .assert_reset = arm7_9_assert_reset,
71 .deassert_reset = arm7_9_deassert_reset,
72 .soft_reset_halt = arm920t_soft_reset_halt,
73
74 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
75
76 .read_memory = arm920t_read_memory,
77 .write_memory = arm920t_write_memory,
78 .bulk_write_memory = arm7_9_bulk_write_memory,
79
80 .run_algorithm = armv4_5_run_algorithm,
81
82 .add_breakpoint = arm7_9_add_breakpoint,
83 .remove_breakpoint = arm7_9_remove_breakpoint,
84 .add_watchpoint = arm7_9_add_watchpoint,
85 .remove_watchpoint = arm7_9_remove_watchpoint,
86
87 .register_commands = arm920t_register_commands,
88 .target_command = arm920t_target_command,
89 .init_target = arm920t_init_target,
90 .quit = arm920t_quit
91 };
92
93 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
94 {
95 armv4_5_common_t *armv4_5 = target->arch_info;
96 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
97 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
98 scan_field_t fields[4];
99 u8 access_type_buf = 1;
100 u8 reg_addr_buf = reg_addr & 0x3f;
101 u8 nr_w_buf = 0;
102
103 jtag_add_end_state(TAP_RTI);
104 arm_jtag_scann(jtag_info, 0xf);
105 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
106
107 fields[0].device = jtag_info->chain_pos;
108 fields[0].num_bits = 1;
109 fields[0].out_value = &access_type_buf;
110 fields[0].out_mask = NULL;
111 fields[0].in_value = NULL;
112 fields[0].in_check_value = NULL;
113 fields[0].in_check_mask = NULL;
114 fields[0].in_handler = NULL;
115 fields[0].in_handler_priv = NULL;
116
117 fields[1].device = jtag_info->chain_pos;
118 fields[1].num_bits = 32;
119 fields[1].out_value = NULL;
120 fields[1].out_mask = NULL;
121 fields[1].in_value = NULL;
122 fields[1].in_check_value = NULL;
123 fields[1].in_check_mask = NULL;
124 fields[1].in_handler = NULL;
125 fields[1].in_handler_priv = NULL;
126
127 fields[2].device = jtag_info->chain_pos;
128 fields[2].num_bits = 6;
129 fields[2].out_value = &reg_addr_buf;
130 fields[2].out_mask = NULL;
131 fields[2].in_value = NULL;
132 fields[2].in_check_value = NULL;
133 fields[2].in_check_mask = NULL;
134 fields[2].in_handler = NULL;
135 fields[2].in_handler_priv = NULL;
136
137 fields[3].device = jtag_info->chain_pos;
138 fields[3].num_bits = 1;
139 fields[3].out_value = &nr_w_buf;
140 fields[3].out_mask = NULL;
141 fields[3].in_value = NULL;
142 fields[3].in_check_value = NULL;
143 fields[3].in_check_mask = NULL;
144 fields[3].in_handler = NULL;
145 fields[3].in_handler_priv = NULL;
146
147 jtag_add_dr_scan(4, fields, -1);
148
149 fields[1].in_handler_priv = value;
150 fields[1].in_handler = arm_jtag_buf_to_u32;
151
152 jtag_add_dr_scan(4, fields, -1);
153
154 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
155 jtag_execute_queue();
156 DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
157 #endif
158
159 return ERROR_OK;
160 }
161
162 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
163 {
164 armv4_5_common_t *armv4_5 = target->arch_info;
165 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
166 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
167 scan_field_t fields[4];
168 u8 access_type_buf = 1;
169 u8 reg_addr_buf = reg_addr & 0x3f;
170 u8 nr_w_buf = 1;
171 u8 value_buf[4];
172
173 buf_set_u32(value_buf, 0, 32, value);
174
175 jtag_add_end_state(TAP_RTI);
176 arm_jtag_scann(jtag_info, 0xf);
177 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
178
179 fields[0].device = jtag_info->chain_pos;
180 fields[0].num_bits = 1;
181 fields[0].out_value = &access_type_buf;
182 fields[0].out_mask = NULL;
183 fields[0].in_value = NULL;
184 fields[0].in_check_value = NULL;
185 fields[0].in_check_mask = NULL;
186 fields[0].in_handler = NULL;
187 fields[0].in_handler_priv = NULL;
188
189 fields[1].device = jtag_info->chain_pos;
190 fields[1].num_bits = 32;
191 fields[1].out_value = value_buf;
192 fields[1].out_mask = NULL;
193 fields[1].in_value = NULL;
194 fields[1].in_check_value = NULL;
195 fields[1].in_check_mask = NULL;
196 fields[1].in_handler = NULL;
197 fields[1].in_handler_priv = NULL;
198
199 fields[2].device = jtag_info->chain_pos;
200 fields[2].num_bits = 6;
201 fields[2].out_value = &reg_addr_buf;
202 fields[2].out_mask = NULL;
203 fields[2].in_value = NULL;
204 fields[2].in_check_value = NULL;
205 fields[2].in_check_mask = NULL;
206 fields[2].in_handler = NULL;
207 fields[2].in_handler_priv = NULL;
208
209 fields[3].device = jtag_info->chain_pos;
210 fields[3].num_bits = 1;
211 fields[3].out_value = &nr_w_buf;
212 fields[3].out_mask = NULL;
213 fields[3].in_value = NULL;
214 fields[3].in_check_value = NULL;
215 fields[3].in_check_mask = NULL;
216 fields[3].in_handler = NULL;
217 fields[3].in_handler_priv = NULL;
218
219 jtag_add_dr_scan(4, fields, -1);
220
221 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
222 DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
223 #endif
224
225 return ERROR_OK;
226 }
227
228 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
229 {
230 armv4_5_common_t *armv4_5 = target->arch_info;
231 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
232 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
233 scan_field_t fields[4];
234 u8 access_type_buf = 0; /* interpreted access */
235 u8 reg_addr_buf = 0x0;
236 u8 nr_w_buf = 0;
237 u8 cp15_opcode_buf[4];
238
239 jtag_add_end_state(TAP_RTI);
240 arm_jtag_scann(jtag_info, 0xf);
241 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
242
243 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
244
245 fields[0].device = jtag_info->chain_pos;
246 fields[0].num_bits = 1;
247 fields[0].out_value = &access_type_buf;
248 fields[0].out_mask = NULL;
249 fields[0].in_value = NULL;
250 fields[0].in_check_value = NULL;
251 fields[0].in_check_mask = NULL;
252 fields[0].in_handler = NULL;
253 fields[0].in_handler_priv = NULL;
254
255 fields[1].device = jtag_info->chain_pos;
256 fields[1].num_bits = 32;
257 fields[1].out_value = cp15_opcode_buf;
258 fields[1].out_mask = NULL;
259 fields[1].in_value = NULL;
260 fields[1].in_check_value = NULL;
261 fields[1].in_check_mask = NULL;
262 fields[1].in_handler = NULL;
263 fields[1].in_handler_priv = NULL;
264
265 fields[2].device = jtag_info->chain_pos;
266 fields[2].num_bits = 6;
267 fields[2].out_value = &reg_addr_buf;
268 fields[2].out_mask = NULL;
269 fields[2].in_value = NULL;
270 fields[2].in_check_value = NULL;
271 fields[2].in_check_mask = NULL;
272 fields[2].in_handler = NULL;
273 fields[2].in_handler_priv = NULL;
274
275 fields[3].device = jtag_info->chain_pos;
276 fields[3].num_bits = 1;
277 fields[3].out_value = &nr_w_buf;
278 fields[3].out_mask = NULL;
279 fields[3].in_value = NULL;
280 fields[3].in_check_value = NULL;
281 fields[3].in_check_mask = NULL;
282 fields[3].in_handler = NULL;
283 fields[3].in_handler_priv = NULL;
284
285 jtag_add_dr_scan(4, fields, -1);
286
287 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
288 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
289 arm7_9_execute_sys_speed(target);
290
291 if (jtag_execute_queue() != ERROR_OK)
292 {
293 ERROR("failed executing JTAG queue, exiting");
294 exit(-1);
295 }
296
297 return ERROR_OK;
298 }
299
300 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
301 {
302 armv4_5_common_t *armv4_5 = target->arch_info;
303 u32* regs_p[1];
304 u32 regs[2];
305 u32 cp15c15 = 0x0;
306
307 /* load address into R1 */
308 regs[1] = address;
309 arm9tdmi_write_core_regs(target, 0x2, regs);
310
311 /* read-modify-write CP15 test state register
312 * to enable interpreted access mode */
313 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
314 jtag_execute_queue();
315 cp15c15 |= 1; /* set interpret mode */
316 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
317
318 /* execute CP15 instruction and ARM load (reading from coprocessor) */
319 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
320
321 /* disable interpreted access mode */
322 cp15c15 &= ~1U; /* clear interpret mode */
323 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
324
325 /* retrieve value from R0 */
326 regs_p[0] = value;
327 arm9tdmi_read_core_regs(target, 0x1, regs_p);
328 jtag_execute_queue();
329
330 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
331 DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
332 #endif
333
334 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
335 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
336
337 return ERROR_OK;
338 }
339
340 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
341 {
342 u32 cp15c15 = 0x0;
343 armv4_5_common_t *armv4_5 = target->arch_info;
344 u32 regs[2];
345
346 /* load value, address into R0, R1 */
347 regs[0] = value;
348 regs[1] = address;
349 arm9tdmi_write_core_regs(target, 0x3, regs);
350
351 /* read-modify-write CP15 test state register
352 * to enable interpreted access mode */
353 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
354 jtag_execute_queue();
355 cp15c15 |= 1; /* set interpret mode */
356 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
357
358 /* execute CP15 instruction and ARM store (writing to coprocessor) */
359 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
360
361 /* disable interpreted access mode */
362 cp15c15 &= ~1U; /* set interpret mode */
363 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
364
365 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
366 DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
367 #endif
368
369 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
370 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
371
372 return ERROR_OK;
373 }
374
375 u32 arm920t_get_ttb(target_t *target)
376 {
377 int retval;
378 u32 ttb = 0x0;
379
380 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
381 return retval;
382
383 return ttb;
384 }
385
386 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
387 {
388 u32 cp15_control;
389
390 /* read cp15 control register */
391 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
392 jtag_execute_queue();
393
394 if (mmu)
395 cp15_control &= ~0x1U;
396
397 if (d_u_cache)
398 cp15_control &= ~0x4U;
399
400 if (i_cache)
401 cp15_control &= ~0x1000U;
402
403 arm920t_write_cp15_physical(target, 0x2, cp15_control);
404 }
405
406 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
407 {
408 u32 cp15_control;
409
410 /* read cp15 control register */
411 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
412 jtag_execute_queue();
413
414 if (mmu)
415 cp15_control |= 0x1U;
416
417 if (d_u_cache)
418 cp15_control |= 0x4U;
419
420 if (i_cache)
421 cp15_control |= 0x1000U;
422
423 arm920t_write_cp15_physical(target, 0x2, cp15_control);
424 }
425
426 void arm920t_post_debug_entry(target_t *target)
427 {
428 u32 cp15c15;
429 armv4_5_common_t *armv4_5 = target->arch_info;
430 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
431 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
432 arm920t_common_t *arm920t = arm9tdmi->arch_info;
433
434 /* examine cp15 control reg */
435 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
436 jtag_execute_queue();
437 DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
438
439 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
440 {
441 u32 cache_type_reg;
442 /* identify caches */
443 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
444 jtag_execute_queue();
445 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
446 }
447
448 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
449 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
450 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
451
452 /* save i/d fault status and address register */
453 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
454 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
455 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
456 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
457
458 DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
459 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
460
461 if (arm920t->preserve_cache)
462 {
463 /* read-modify-write CP15 test state register
464 * to disable I/D-cache linefills */
465 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
466 jtag_execute_queue();
467 cp15c15 |= 0x600;
468 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
469 }
470 }
471
472 void arm920t_pre_restore_context(target_t *target)
473 {
474 u32 cp15c15;
475 armv4_5_common_t *armv4_5 = target->arch_info;
476 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
477 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
478 arm920t_common_t *arm920t = arm9tdmi->arch_info;
479
480 /* restore i/d fault status and address register */
481 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
482 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
483 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
484 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
485
486 /* read-modify-write CP15 test state register
487 * to reenable I/D-cache linefills */
488 if (arm920t->preserve_cache)
489 {
490 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
491 jtag_execute_queue();
492 cp15c15 &= ~0x600U;
493 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
494 }
495 }
496
497 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
498 {
499 armv4_5_common_t *armv4_5 = target->arch_info;
500 arm7_9_common_t *arm7_9;
501 arm9tdmi_common_t *arm9tdmi;
502 arm920t_common_t *arm920t;
503
504 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
505 {
506 return -1;
507 }
508
509 arm7_9 = armv4_5->arch_info;
510 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
511 {
512 return -1;
513 }
514
515 arm9tdmi = arm7_9->arch_info;
516 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
517 {
518 return -1;
519 }
520
521 arm920t = arm9tdmi->arch_info;
522 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
523 {
524 return -1;
525 }
526
527 *armv4_5_p = armv4_5;
528 *arm7_9_p = arm7_9;
529 *arm9tdmi_p = arm9tdmi;
530 *arm920t_p = arm920t;
531
532 return ERROR_OK;
533 }
534
535 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size)
536 {
537 armv4_5_common_t *armv4_5 = target->arch_info;
538 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
539 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
540 arm920t_common_t *arm920t = arm9tdmi->arch_info;
541
542 char *state[] =
543 {
544 "disabled", "enabled"
545 };
546
547 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
548 {
549 ERROR("BUG: called for a non-ARMv4/5 target");
550 exit(-1);
551 }
552
553 snprintf(buf, buf_size,
554 "target halted in %s state due to %s, current mode: %s\n"
555 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
556 "MMU: %s, D-Cache: %s, I-Cache: %s",
557 armv4_5_state_strings[armv4_5->core_state],
558 target_debug_reason_strings[target->debug_reason],
559 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
560 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
561 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
562 state[arm920t->armv4_5_mmu.mmu_enabled],
563 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
564 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
565
566 return ERROR_OK;
567 }
568
569 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
570 {
571 int retval;
572
573 retval = arm7_9_read_memory(target, address, size, count, buffer);
574
575 return retval;
576 }
577
578 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
579 {
580 int retval;
581 armv4_5_common_t *armv4_5 = target->arch_info;
582 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
583 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
584 arm920t_common_t *arm920t = arm9tdmi->arch_info;
585
586 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
587 return retval;
588
589 if (((size == 4) || (size == 2)) && (count == 1))
590 {
591 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
592 {
593 DEBUG("D-Cache enabled, writing through to main memory");
594 u32 pa, cb, ap;
595 int type, domain;
596
597 pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
598 if (type == -1)
599 return ERROR_OK;
600 /* cacheable & bufferable means write-back region */
601 if (cb == 3)
602 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
603 }
604
605 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
606 {
607 DEBUG("I-Cache enabled, invalidating affected I-Cache line");
608 arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
609 }
610 }
611
612 return retval;
613 }
614
615 int arm920t_soft_reset_halt(struct target_s *target)
616 {
617 armv4_5_common_t *armv4_5 = target->arch_info;
618 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
619 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
620 arm920t_common_t *arm920t = arm9tdmi->arch_info;
621 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
622
623 if (target->state == TARGET_RUNNING)
624 {
625 target->type->halt(target);
626 }
627
628 while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
629 {
630 embeddedice_read_reg(dbg_stat);
631 jtag_execute_queue();
632 }
633
634 target->state = TARGET_HALTED;
635
636 /* SVC, ARM state, IRQ and FIQ disabled */
637 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
638 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
639 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
640
641 /* start fetching from 0x0 */
642 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
643 armv4_5->core_cache->reg_list[15].dirty = 1;
644 armv4_5->core_cache->reg_list[15].valid = 1;
645
646 armv4_5->core_mode = ARMV4_5_MODE_SVC;
647 armv4_5->core_state = ARMV4_5_STATE_ARM;
648
649 arm920t_disable_mmu_caches(target, 1, 1, 1);
650 arm920t->armv4_5_mmu.mmu_enabled = 0;
651 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
652 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
653
654 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
655
656 return ERROR_OK;
657 }
658
659 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
660 {
661 arm9tdmi_init_target(cmd_ctx, target);
662
663 return ERROR_OK;
664
665 }
666
667 int arm920t_quit()
668 {
669
670 return ERROR_OK;
671 }
672
673 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)
674 {
675 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
676 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
677
678 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
679 */
680 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
681
682 arm9tdmi->arch_info = arm920t;
683 arm920t->common_magic = ARM920T_COMMON_MAGIC;
684
685 arm7_9->post_debug_entry = arm920t_post_debug_entry;
686 arm7_9->pre_restore_context = arm920t_pre_restore_context;
687
688 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
689 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
690 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
691 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
692 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
693 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
694 arm920t->armv4_5_mmu.has_tiny_pages = 1;
695 arm920t->armv4_5_mmu.mmu_enabled = 0;
696
697 /* disabling linefills leads to lockups, so keep them enabled for now
698 * this doesn't affect correctness, but might affect timing issues, if
699 * important data is evicted from the cache during the debug session
700 * */
701 arm920t->preserve_cache = 0;
702
703 /* override hw single-step capability from ARM9TDMI */
704 arm7_9->has_single_step = 1;
705
706 return ERROR_OK;
707 }
708
709 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
710 {
711 int chain_pos;
712 char *variant = NULL;
713 arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
714
715 if (argc < 4)
716 {
717 ERROR("'target arm920t' requires at least one additional argument");
718 exit(-1);
719 }
720
721 chain_pos = strtoul(args[3], NULL, 0);
722
723 if (argc >= 5)
724 variant = args[4];
725
726 DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
727
728 arm920t_init_arch_info(target, arm920t, chain_pos, variant);
729
730 return ERROR_OK;
731 }
732
733 int arm920t_register_commands(struct command_context_s *cmd_ctx)
734 {
735 int retval;
736 command_t *arm920t_cmd;
737
738
739 retval = arm9tdmi_register_commands(cmd_ctx);
740
741 arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
742
743 register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
744 register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
745 register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
746 register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
747
748 register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
749 register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
750 register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
751
752 register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
753 register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
754 register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
755
756 register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
757 register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
758
759 return ERROR_OK;
760 }
761
762 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
763 {
764 target_t *target = get_current_target(cmd_ctx);
765 armv4_5_common_t *armv4_5;
766 arm7_9_common_t *arm7_9;
767 arm9tdmi_common_t *arm9tdmi;
768 arm920t_common_t *arm920t;
769 arm_jtag_t *jtag_info;
770 u32 cp15c15;
771 u32 cp15_ctrl, cp15_ctrl_saved;
772 u32 regs[16];
773 u32 *regs_p[16];
774 u32 C15_C_D_Ind, C15_C_I_Ind;
775 int i;
776 FILE *output;
777 arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
778 int segment, index;
779
780 if (argc != 1)
781 {
782 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
783 return ERROR_OK;
784 }
785
786 if ((output = fopen(args[0], "w")) == NULL)
787 {
788 DEBUG("error opening cache content file");
789 return ERROR_OK;
790 }
791
792 for (i = 0; i < 16; i++)
793 regs_p[i] = &regs[i];
794
795 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
796 {
797 command_print(cmd_ctx, "current target isn't an ARM920t target");
798 return ERROR_OK;
799 }
800
801 jtag_info = &arm7_9->jtag_info;
802
803 /* disable MMU and Caches */
804 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
805 jtag_execute_queue();
806 cp15_ctrl_saved = cp15_ctrl;
807 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
808 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
809
810 /* read CP15 test state register */
811 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
812 jtag_execute_queue();
813
814 /* read DCache content */
815 fprintf(output, "DCache:\n");
816
817 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
818 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
819 {
820 fprintf(output, "\nsegment: %i\n----------", segment);
821
822 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
823 regs[0] = 0x0 | (segment << 5);
824 arm9tdmi_write_core_regs(target, 0x1, regs);
825
826 /* set interpret mode */
827 cp15c15 |= 0x1;
828 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
829
830 /* D CAM Read, loads current victim into C15.C.D.Ind */
831 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
832
833 /* read current victim */
834 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
835
836 /* clear interpret mode */
837 cp15c15 &= ~0x1;
838 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
839
840 for (index = 0; index < 64; index++)
841 {
842 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
843 regs[0] = 0x0 | (segment << 5) | (index << 26);
844 arm9tdmi_write_core_regs(target, 0x1, regs);
845
846 /* set interpret mode */
847 cp15c15 |= 0x1;
848 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
849
850 /* Write DCache victim */
851 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
852
853 /* Read D RAM */
854 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
855
856 /* Read D CAM */
857 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
858
859 /* clear interpret mode */
860 cp15c15 &= ~0x1;
861 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
862
863 /* read D RAM and CAM content */
864 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
865 jtag_execute_queue();
866
867 d_cache[segment][index].cam = regs[9];
868
869 /* mask LFSR[6] */
870 regs[9] &= 0xfffffffe;
871 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
872
873 for (i = 1; i < 9; i++)
874 {
875 d_cache[segment][index].data[i] = regs[i];
876 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
877 }
878
879 }
880
881 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
882 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
883 arm9tdmi_write_core_regs(target, 0x1, regs);
884
885 /* set interpret mode */
886 cp15c15 |= 0x1;
887 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
888
889 /* Write DCache victim */
890 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
891
892 /* clear interpret mode */
893 cp15c15 &= ~0x1;
894 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
895 }
896
897 /* read ICache content */
898 fprintf(output, "ICache:\n");
899
900 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
901 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
902 {
903 fprintf(output, "segment: %i\n----------", segment);
904
905 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
906 regs[0] = 0x0 | (segment << 5);
907 arm9tdmi_write_core_regs(target, 0x1, regs);
908
909 /* set interpret mode */
910 cp15c15 |= 0x1;
911 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
912
913 /* I CAM Read, loads current victim into C15.C.I.Ind */
914 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
915
916 /* read current victim */
917 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
918
919 /* clear interpret mode */
920 cp15c15 &= ~0x1;
921 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
922
923 for (index = 0; index < 64; index++)
924 {
925 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
926 regs[0] = 0x0 | (segment << 5) | (index << 26);
927 arm9tdmi_write_core_regs(target, 0x1, regs);
928
929 /* set interpret mode */
930 cp15c15 |= 0x1;
931 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
932
933 /* Write ICache victim */
934 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
935
936 /* Read I RAM */
937 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
938
939 /* Read I CAM */
940 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
941
942 /* clear interpret mode */
943 cp15c15 &= ~0x1;
944 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
945
946 /* read I RAM and CAM content */
947 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
948 jtag_execute_queue();
949
950 i_cache[segment][index].cam = regs[9];
951
952 /* mask LFSR[6] */
953 regs[9] &= 0xfffffffe;
954 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
955
956 for (i = 1; i < 9; i++)
957 {
958 i_cache[segment][index].data[i] = regs[i];
959 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
960 }
961
962 }
963
964
965 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
966 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
967 arm9tdmi_write_core_regs(target, 0x1, regs);
968
969 /* set interpret mode */
970 cp15c15 |= 0x1;
971 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
972
973 /* Write ICache victim */
974 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
975
976 /* clear interpret mode */
977 cp15c15 &= ~0x1;
978 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
979 }
980
981 /* restore CP15 MMU and Cache settings */
982 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
983
984 command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
985
986 fclose(output);
987
988 /* mark registers dirty */
989 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
990 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
991 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
992 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
993 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
994 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
995 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
996 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
997 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
998 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
999
1000 return ERROR_OK;
1001 }
1002
1003 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1004 {
1005 target_t *target = get_current_target(cmd_ctx);
1006 armv4_5_common_t *armv4_5;
1007 arm7_9_common_t *arm7_9;
1008 arm9tdmi_common_t *arm9tdmi;
1009 arm920t_common_t *arm920t;
1010 arm_jtag_t *jtag_info;
1011 u32 cp15c15;
1012 u32 cp15_ctrl, cp15_ctrl_saved;
1013 u32 regs[16];
1014 u32 *regs_p[16];
1015 int i;
1016 FILE *output;
1017 u32 Dlockdown, Ilockdown;
1018 arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1019 int victim;
1020
1021 if (argc != 1)
1022 {
1023 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1024 return ERROR_OK;
1025 }
1026
1027 if ((output = fopen(args[0], "w")) == NULL)
1028 {
1029 DEBUG("error opening mmu content file");
1030 return ERROR_OK;
1031 }
1032
1033 for (i = 0; i < 16; i++)
1034 regs_p[i] = &regs[i];
1035
1036 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1037 {
1038 command_print(cmd_ctx, "current target isn't an ARM920t target");
1039 return ERROR_OK;
1040 }
1041
1042 jtag_info = &arm7_9->jtag_info;
1043
1044 /* disable MMU and Caches */
1045 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1046 jtag_execute_queue();
1047 cp15_ctrl_saved = cp15_ctrl;
1048 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1049 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1050
1051 /* read CP15 test state register */
1052 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1053 jtag_execute_queue();
1054
1055 /* prepare reading D TLB content
1056 * */
1057
1058 /* set interpret mode */
1059 cp15c15 |= 0x1;
1060 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1061
1062 /* Read D TLB lockdown */
1063 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1064
1065 /* clear interpret mode */
1066 cp15c15 &= ~0x1;
1067 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1068
1069 /* read D TLB lockdown stored to r1 */
1070 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1071 jtag_execute_queue();
1072 Dlockdown = regs[1];
1073
1074 for (victim = 0; victim < 64; victim += 8)
1075 {
1076 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1077 * base remains unchanged, victim goes through entries 0 to 63 */
1078 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1079 arm9tdmi_write_core_regs(target, 0x2, regs);
1080
1081 /* set interpret mode */
1082 cp15c15 |= 0x1;
1083 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1084
1085 /* Write D TLB lockdown */
1086 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1087
1088 /* Read D TLB CAM */
1089 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1090
1091 /* clear interpret mode */
1092 cp15c15 &= ~0x1;
1093 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1094
1095 /* read D TLB CAM content stored to r2-r9 */
1096 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1097 jtag_execute_queue();
1098
1099 for (i = 0; i < 8; i++)
1100 d_tlb[victim + i].cam = regs[i + 2];
1101 }
1102
1103 for (victim = 0; victim < 64; victim++)
1104 {
1105 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1106 * base remains unchanged, victim goes through entries 0 to 63 */
1107 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1108 arm9tdmi_write_core_regs(target, 0x2, regs);
1109
1110 /* set interpret mode */
1111 cp15c15 |= 0x1;
1112 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1113
1114 /* Write D TLB lockdown */
1115 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1116
1117 /* Read D TLB RAM1 */
1118 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1119
1120 /* Read D TLB RAM2 */
1121 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1122
1123 /* clear interpret mode */
1124 cp15c15 &= ~0x1;
1125 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1126
1127 /* read D TLB RAM content stored to r2 and r3 */
1128 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1129 jtag_execute_queue();
1130
1131 d_tlb[victim].ram1 = regs[2];
1132 d_tlb[victim].ram2 = regs[3];
1133 }
1134
1135 /* restore D TLB lockdown */
1136 regs[1] = Dlockdown;
1137 arm9tdmi_write_core_regs(target, 0x2, regs);
1138
1139 /* Write D TLB lockdown */
1140 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1141
1142 /* prepare reading I TLB content
1143 * */
1144
1145 /* set interpret mode */
1146 cp15c15 |= 0x1;
1147 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1148
1149 /* Read I TLB lockdown */
1150 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1151
1152 /* clear interpret mode */
1153 cp15c15 &= ~0x1;
1154 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1155
1156 /* read I TLB lockdown stored to r1 */
1157 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1158 jtag_execute_queue();
1159 Ilockdown = regs[1];
1160
1161 for (victim = 0; victim < 64; victim += 8)
1162 {
1163 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1164 * base remains unchanged, victim goes through entries 0 to 63 */
1165 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1166 arm9tdmi_write_core_regs(target, 0x2, regs);
1167
1168 /* set interpret mode */
1169 cp15c15 |= 0x1;
1170 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1171
1172 /* Write I TLB lockdown */
1173 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1174
1175 /* Read I TLB CAM */
1176 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1177
1178 /* clear interpret mode */
1179 cp15c15 &= ~0x1;
1180 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1181
1182 /* read I TLB CAM content stored to r2-r9 */
1183 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1184 jtag_execute_queue();
1185
1186 for (i = 0; i < 8; i++)
1187 i_tlb[i + victim].cam = regs[i + 2];
1188 }
1189
1190 for (victim = 0; victim < 64; victim++)
1191 {
1192 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1193 * base remains unchanged, victim goes through entries 0 to 63 */
1194 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1195 arm9tdmi_write_core_regs(target, 0x2, regs);
1196
1197 /* set interpret mode */
1198 cp15c15 |= 0x1;
1199 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1200
1201 /* Write I TLB lockdown */
1202 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1203
1204 /* Read I TLB RAM1 */
1205 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1206
1207 /* Read I TLB RAM2 */
1208 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1209
1210 /* clear interpret mode */
1211 cp15c15 &= ~0x1;
1212 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1213
1214 /* read I TLB RAM content stored to r2 and r3 */
1215 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1216 jtag_execute_queue();
1217
1218 i_tlb[victim].ram1 = regs[2];
1219 i_tlb[victim].ram2 = regs[3];
1220 }
1221
1222 /* restore I TLB lockdown */
1223 regs[1] = Ilockdown;
1224 arm9tdmi_write_core_regs(target, 0x2, regs);
1225
1226 /* Write I TLB lockdown */
1227 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1228
1229 /* restore CP15 MMU and Cache settings */
1230 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1231
1232 /* output data to file */
1233 fprintf(output, "D TLB content:\n");
1234 for (i = 0; i < 64; i++)
1235 {
1236 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1237 }
1238
1239 fprintf(output, "\n\nI TLB content:\n");
1240 for (i = 0; i < 64; i++)
1241 {
1242 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1243 }
1244
1245 command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1246
1247 fclose(output);
1248
1249 /* mark registers dirty */
1250 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1251 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
1252 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
1253 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
1254 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
1255 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
1256 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
1257 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
1258 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
1259 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
1260
1261 return ERROR_OK;
1262 }
1263 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1264 {
1265 int retval;
1266 target_t *target = get_current_target(cmd_ctx);
1267 armv4_5_common_t *armv4_5;
1268 arm7_9_common_t *arm7_9;
1269 arm9tdmi_common_t *arm9tdmi;
1270 arm920t_common_t *arm920t;
1271 arm_jtag_t *jtag_info;
1272
1273 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1274 {
1275 command_print(cmd_ctx, "current target isn't an ARM920t target");
1276 return ERROR_OK;
1277 }
1278
1279 jtag_info = &arm7_9->jtag_info;
1280
1281 if (target->state != TARGET_HALTED)
1282 {
1283 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1284 return ERROR_OK;
1285 }
1286
1287 /* one or more argument, access a single register (write if second argument is given */
1288 if (argc >= 1)
1289 {
1290 int address = strtoul(args[0], NULL, 0);
1291
1292 if (argc == 1)
1293 {
1294 u32 value;
1295 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1296 {
1297 command_print(cmd_ctx, "couldn't access reg %i", address);
1298 return ERROR_OK;
1299 }
1300 jtag_execute_queue();
1301
1302 command_print(cmd_ctx, "%i: %8.8x", address, value);
1303 }
1304 else if (argc == 2)
1305 {
1306 u32 value = strtoul(args[1], NULL, 0);
1307 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1308 {
1309 command_print(cmd_ctx, "couldn't access reg %i", address);
1310 return ERROR_OK;
1311 }
1312 command_print(cmd_ctx, "%i: %8.8x", address, value);
1313 }
1314 }
1315
1316 return ERROR_OK;
1317 }
1318
1319 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1320 {
1321 int retval;
1322 target_t *target = get_current_target(cmd_ctx);
1323 armv4_5_common_t *armv4_5;
1324 arm7_9_common_t *arm7_9;
1325 arm9tdmi_common_t *arm9tdmi;
1326 arm920t_common_t *arm920t;
1327 arm_jtag_t *jtag_info;
1328
1329 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1330 {
1331 command_print(cmd_ctx, "current target isn't an ARM920t target");
1332 return ERROR_OK;
1333 }
1334
1335 jtag_info = &arm7_9->jtag_info;
1336
1337 if (target->state != TARGET_HALTED)
1338 {
1339 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1340 return ERROR_OK;
1341 }
1342
1343 /* one or more argument, access a single register (write if second argument is given */
1344 if (argc >= 1)
1345 {
1346 u32 opcode = strtoul(args[0], NULL, 0);
1347
1348 if (argc == 1)
1349 {
1350 u32 value;
1351 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1352 {
1353 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1354 return ERROR_OK;
1355 }
1356
1357 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1358 }
1359 else if (argc == 2)
1360 {
1361 u32 value = strtoul(args[1], NULL, 0);
1362 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1363 {
1364 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1365 return ERROR_OK;
1366 }
1367 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1368 }
1369 else if (argc == 3)
1370 {
1371 u32 value = strtoul(args[1], NULL, 0);
1372 u32 address = strtoul(args[2], NULL, 0);
1373 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1374 {
1375 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1376 return ERROR_OK;
1377 }
1378 command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1379 }
1380 }
1381 else
1382 {
1383 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1384 }
1385
1386 return ERROR_OK;
1387 }
1388
1389 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1390 {
1391 target_t *target = get_current_target(cmd_ctx);
1392 armv4_5_common_t *armv4_5;
1393 arm7_9_common_t *arm7_9;
1394 arm9tdmi_common_t *arm9tdmi;
1395 arm920t_common_t *arm920t;
1396
1397 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1398 {
1399 command_print(cmd_ctx, "current target isn't an ARM920t target");
1400 return ERROR_OK;
1401 }
1402
1403 return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1404 }
1405
1406 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1407 {
1408 target_t *target = get_current_target(cmd_ctx);
1409 armv4_5_common_t *armv4_5;
1410 arm7_9_common_t *arm7_9;
1411 arm9tdmi_common_t *arm9tdmi;
1412 arm920t_common_t *arm920t;
1413 arm_jtag_t *jtag_info;
1414
1415 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1416 {
1417 command_print(cmd_ctx, "current target isn't an ARM920t target");
1418 return ERROR_OK;
1419 }
1420
1421 jtag_info = &arm7_9->jtag_info;
1422
1423 if (target->state != TARGET_HALTED)
1424 {
1425 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1426 return ERROR_OK;
1427 }
1428
1429 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1430 }
1431
1432 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1433 {
1434 target_t *target = get_current_target(cmd_ctx);
1435 armv4_5_common_t *armv4_5;
1436 arm7_9_common_t *arm7_9;
1437 arm9tdmi_common_t *arm9tdmi;
1438 arm920t_common_t *arm920t;
1439 arm_jtag_t *jtag_info;
1440
1441 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1442 {
1443 command_print(cmd_ctx, "current target isn't an ARM920t target");
1444 return ERROR_OK;
1445 }
1446
1447 jtag_info = &arm7_9->jtag_info;
1448
1449 if (target->state != TARGET_HALTED)
1450 {
1451 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1452 return ERROR_OK;
1453 }
1454
1455 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1456 }
1457
1458 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1459 {
1460 target_t *target = get_current_target(cmd_ctx);
1461 armv4_5_common_t *armv4_5;
1462 arm7_9_common_t *arm7_9;
1463 arm9tdmi_common_t *arm9tdmi;
1464 arm920t_common_t *arm920t;
1465 arm_jtag_t *jtag_info;
1466
1467 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1468 {
1469 command_print(cmd_ctx, "current target isn't an ARM920t target");
1470 return ERROR_OK;
1471 }
1472
1473 jtag_info = &arm7_9->jtag_info;
1474
1475 if (target->state != TARGET_HALTED)
1476 {
1477 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1478 return ERROR_OK;
1479 }
1480
1481 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1482 }
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