1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2007,2008 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 #include "target_type.h"
35 #define _DEBUG_INSTRUCTION_EXECUTION_
38 /* forward declarations */
40 int arm7tdmi_target_create(struct target_s
*target
,Jim_Interp
*interp
);
42 /* target function declarations */
43 int arm7tdmi_poll(struct target_s
*target
);
44 int arm7tdmi_halt(target_t
*target
);
46 target_type_t arm7tdmi_target
=
51 .arch_state
= armv4_5_arch_state
,
53 .target_request_data
= arm7_9_target_request_data
,
56 .resume
= arm7_9_resume
,
59 .assert_reset
= arm7_9_assert_reset
,
60 .deassert_reset
= arm7_9_deassert_reset
,
61 .soft_reset_halt
= arm7_9_soft_reset_halt
,
63 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
65 .read_memory
= arm7_9_read_memory
,
66 .write_memory
= arm7_9_write_memory
,
67 .bulk_write_memory
= arm7_9_bulk_write_memory
,
68 .checksum_memory
= arm7_9_checksum_memory
,
69 .blank_check_memory
= arm7_9_blank_check_memory
,
71 .run_algorithm
= armv4_5_run_algorithm
,
73 .add_breakpoint
= arm7_9_add_breakpoint
,
74 .remove_breakpoint
= arm7_9_remove_breakpoint
,
75 .add_watchpoint
= arm7_9_add_watchpoint
,
76 .remove_watchpoint
= arm7_9_remove_watchpoint
,
78 .register_commands
= arm7tdmi_register_commands
,
79 .target_create
= arm7tdmi_target_create
,
80 .init_target
= arm7tdmi_init_target
,
81 .examine
= arm7tdmi_examine
,
84 int arm7tdmi_examine_debug_reason(target_t
*target
)
86 int retval
= ERROR_OK
;
87 /* get pointers to arch-specific information */
88 armv4_5_common_t
*armv4_5
= target
->arch_info
;
89 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
91 /* only check the debug reason if we don't know it already */
92 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
93 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
95 scan_field_t fields
[2];
99 jtag_set_end_state(TAP_DRPAUSE
);
101 fields
[0].tap
= arm7_9
->jtag_info
.tap
;
102 fields
[0].num_bits
= 1;
103 fields
[0].out_value
= NULL
;
104 fields
[0].in_value
= &breakpoint
;
106 fields
[1].tap
= arm7_9
->jtag_info
.tap
;
107 fields
[1].num_bits
= 32;
108 fields
[1].out_value
= NULL
;
109 fields
[1].in_value
= databus
;
111 if ((retval
= arm_jtag_scann(&arm7_9
->jtag_info
, 0x1)) != ERROR_OK
)
115 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, NULL
);
117 jtag_add_dr_scan(2, fields
, jtag_set_end_state(TAP_DRPAUSE
));
118 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
123 fields
[0].in_value
= NULL
;
124 fields
[0].out_value
= &breakpoint
;
125 fields
[1].in_value
= NULL
;
126 fields
[1].out_value
= databus
;
128 jtag_add_dr_scan(2, fields
, jtag_set_end_state(TAP_DRPAUSE
));
131 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
133 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
139 static int arm7tdmi_num_bits
[]={1, 32};
140 static __inline
int arm7tdmi_clock_out_inner(arm_jtag_t
*jtag_info
, uint32_t out
, int breakpoint
)
142 uint32_t values
[2]={breakpoint
, flip_u32(out
, 32)};
144 jtag_add_dr_out(jtag_info
->tap
,
148 jtag_get_end_state());
150 jtag_add_runtest(0, jtag_get_end_state());
155 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
156 static __inline
int arm7tdmi_clock_out(arm_jtag_t
*jtag_info
, uint32_t out
, uint32_t *deprecated
, int breakpoint
)
158 jtag_set_end_state(TAP_DRPAUSE
);
159 arm_jtag_scann(jtag_info
, 0x1);
160 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
162 return arm7tdmi_clock_out_inner(jtag_info
, out
, breakpoint
);
165 /* clock the target, reading the databus */
166 int arm7tdmi_clock_data_in(arm_jtag_t
*jtag_info
, uint32_t *in
)
168 int retval
= ERROR_OK
;
169 scan_field_t fields
[2];
171 jtag_set_end_state(TAP_DRPAUSE
);
172 if ((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
176 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
178 fields
[0].tap
= jtag_info
->tap
;
179 fields
[0].num_bits
= 1;
180 fields
[0].out_value
= NULL
;
181 fields
[0].in_value
= NULL
;
183 fields
[1].tap
= jtag_info
->tap
;
184 fields
[1].num_bits
= 32;
185 fields
[1].out_value
= NULL
;
186 fields
[1].in_value
= (uint8_t *)in
;
188 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
190 jtag_add_callback(arm7flip32
, (jtag_callback_data_t
)in
);
192 jtag_add_runtest(0, jtag_get_end_state());
194 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
196 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
203 LOG_DEBUG("in: 0x%8.8x", *in
);
207 LOG_ERROR("BUG: called with in == NULL");
215 void arm_endianness(uint8_t *tmp
, void *in
, int size
, int be
, int flip
)
217 uint32_t readback
= le_to_h_u32(tmp
);
219 readback
= flip_u32(readback
, 32);
225 h_u32_to_be(((uint8_t*)in
), readback
);
228 h_u32_to_le(((uint8_t*)in
), readback
);
234 h_u16_to_be(((uint8_t*)in
), readback
& 0xffff);
237 h_u16_to_le(((uint8_t*)in
), readback
& 0xffff);
241 *((uint8_t *)in
)= readback
& 0xff;
246 static int arm7endianness(jtag_callback_data_t arg
, jtag_callback_data_t size
, jtag_callback_data_t be
, jtag_callback_data_t captured
)
248 uint8_t *in
= (uint8_t *)arg
;
249 arm_endianness((uint8_t *)captured
, in
, (int)size
, (int)be
, 1);
253 /* clock the target, and read the databus
254 * the *in pointer points to a buffer where elements of 'size' bytes
255 * are stored in big (be == 1) or little (be == 0) endianness
257 int arm7tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
259 int retval
= ERROR_OK
;
260 scan_field_t fields
[2];
262 jtag_set_end_state(TAP_DRPAUSE
);
263 if ((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
267 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
269 fields
[0].tap
= jtag_info
->tap
;
270 fields
[0].num_bits
= 1;
271 fields
[0].out_value
= NULL
;
272 fields
[0].in_value
= NULL
;
274 fields
[1].tap
= jtag_info
->tap
;
275 fields
[1].num_bits
= 32;
276 fields
[1].out_value
= NULL
;
277 jtag_alloc_in_value32(&fields
[1]);
279 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
281 jtag_add_callback4(arm7endianness
, (jtag_callback_data_t
)in
, (jtag_callback_data_t
)size
, (jtag_callback_data_t
)be
, (jtag_callback_data_t
)fields
[1].in_value
);
283 jtag_add_runtest(0, jtag_get_end_state());
285 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
287 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
294 LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in
);
298 LOG_ERROR("BUG: called with in == NULL");
306 void arm7tdmi_change_to_arm(target_t
*target
, uint32_t *r0
, uint32_t *pc
)
308 /* get pointers to arch-specific information */
309 armv4_5_common_t
*armv4_5
= target
->arch_info
;
310 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
311 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
313 /* save r0 before using it and put system in ARM state
314 * to allow common handling of ARM and THUMB debugging */
316 /* fetch STR r0, [r0] */
317 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
318 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
319 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
320 /* nothing fetched, STR r0, [r0] in Execute (2) */
321 arm7tdmi_clock_data_in(jtag_info
, r0
);
323 /* MOV r0, r15 fetched, STR in Decode */
324 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), NULL
, 0);
325 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), NULL
, 0);
326 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
327 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
328 /* nothing fetched, STR r0, [r0] in Execute (2) */
329 arm7tdmi_clock_data_in(jtag_info
, pc
);
331 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
332 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
333 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
334 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
335 /* nothing fetched, data for LDR r0, [PC, #0] */
336 arm7tdmi_clock_out(jtag_info
, 0x0, NULL
, 0);
337 /* nothing fetched, data from previous cycle is written to register */
338 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
341 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), NULL
, 0);
342 /* NOP fetched, BX in Decode, MOV in Execute */
343 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
344 /* NOP fetched, BX in Execute (1) */
345 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
347 jtag_execute_queue();
349 /* fix program counter:
350 * MOV r0, r15 was the 4th instruction (+6)
351 * reading PC in Thumb state gives address of instruction + 4
357 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
358 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
360 * The solution is to arrange for a large out/in scan in this loop and
361 * and convert data afterwards.
363 void arm7tdmi_read_core_regs(target_t
*target
, uint32_t mask
, uint32_t* core_regs
[16])
366 /* get pointers to arch-specific information */
367 armv4_5_common_t
*armv4_5
= target
->arch_info
;
368 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
369 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
371 /* STMIA r0-15, [r0] at debug speed
372 * register values will start to appear on 4th DCLK
374 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
376 /* fetch NOP, STM in DECODE stage */
377 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
378 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
379 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
381 for (i
= 0; i
<= 15; i
++)
384 /* nothing fetched, STM still in EXECUTE (1 + i cycle) */
385 arm7tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
389 void arm7tdmi_read_core_regs_target_buffer(target_t
*target
, uint32_t mask
, void* buffer
, int size
)
392 /* get pointers to arch-specific information */
393 armv4_5_common_t
*armv4_5
= target
->arch_info
;
394 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
395 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
396 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
397 uint32_t *buf_u32
= buffer
;
398 uint16_t *buf_u16
= buffer
;
399 uint8_t *buf_u8
= buffer
;
401 /* STMIA r0-15, [r0] at debug speed
402 * register values will start to appear on 4th DCLK
404 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
406 /* fetch NOP, STM in DECODE stage */
407 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
408 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
409 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
411 for (i
= 0; i
<= 15; i
++)
413 /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */
419 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
422 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
425 arm7tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
432 void arm7tdmi_read_xpsr(target_t
*target
, uint32_t *xpsr
, int spsr
)
434 /* get pointers to arch-specific information */
435 armv4_5_common_t
*armv4_5
= target
->arch_info
;
436 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
437 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
440 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), NULL
, 0);
443 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), NULL
, 0);
444 /* fetch NOP, STR in DECODE stage */
445 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
446 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
447 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
448 /* nothing fetched, STR still in EXECUTE (2nd cycle) */
449 arm7tdmi_clock_data_in(jtag_info
, xpsr
);
452 void arm7tdmi_write_xpsr(target_t
*target
, uint32_t xpsr
, int spsr
)
454 /* get pointers to arch-specific information */
455 armv4_5_common_t
*armv4_5
= target
->arch_info
;
456 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
457 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
459 LOG_DEBUG("xpsr: %8.8" PRIx32
", spsr: %i", xpsr
, spsr
);
462 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), NULL
, 0);
463 /* MSR2 fetched, MSR1 in DECODE */
464 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), NULL
, 0);
465 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
466 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), NULL
, 0);
467 /* nothing fetched, MSR1 in EXECUTE (2) */
468 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
469 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
470 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), NULL
, 0);
471 /* nothing fetched, MSR2 in EXECUTE (2) */
472 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
473 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
474 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
475 /* nothing fetched, MSR3 in EXECUTE (2) */
476 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
477 /* NOP fetched, MSR4 in EXECUTE (1) */
478 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
479 /* nothing fetched, MSR4 in EXECUTE (2) */
480 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
483 void arm7tdmi_write_xpsr_im8(target_t
*target
, uint8_t xpsr_im
, int rot
, int spsr
)
485 /* get pointers to arch-specific information */
486 armv4_5_common_t
*armv4_5
= target
->arch_info
;
487 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
488 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
490 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
493 arm7tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), NULL
, 0);
494 /* NOP fetched, MSR in DECODE */
495 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
496 /* NOP fetched, MSR in EXECUTE (1) */
497 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
498 /* nothing fetched, MSR in EXECUTE (2) */
499 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
502 void arm7tdmi_write_core_regs(target_t
*target
, uint32_t mask
, uint32_t core_regs
[16])
505 /* get pointers to arch-specific information */
506 armv4_5_common_t
*armv4_5
= target
->arch_info
;
507 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
508 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
510 /* LDMIA r0-15, [r0] at debug speed
511 * register values will start to appear on 4th DCLK
513 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), NULL
, 0);
515 /* fetch NOP, LDM in DECODE stage */
516 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
517 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
518 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
520 for (i
= 0; i
<= 15; i
++)
523 /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
524 arm7tdmi_clock_out_inner(jtag_info
, core_regs
[i
], 0);
526 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
529 void arm7tdmi_load_word_regs(target_t
*target
, uint32_t mask
)
531 /* get pointers to arch-specific information */
532 armv4_5_common_t
*armv4_5
= target
->arch_info
;
533 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
534 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
536 /* put system-speed load-multiple into the pipeline */
537 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
538 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
539 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), NULL
, 0);
542 void arm7tdmi_load_hword_reg(target_t
*target
, int num
)
544 /* get pointers to arch-specific information */
545 armv4_5_common_t
*armv4_5
= target
->arch_info
;
546 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
547 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
549 /* put system-speed load half-word into the pipeline */
550 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
551 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
552 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), NULL
, 0);
555 void arm7tdmi_load_byte_reg(target_t
*target
, int num
)
557 /* get pointers to arch-specific information */
558 armv4_5_common_t
*armv4_5
= target
->arch_info
;
559 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
560 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
562 /* put system-speed load byte into the pipeline */
563 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
564 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
565 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), NULL
, 0);
568 void arm7tdmi_store_word_regs(target_t
*target
, uint32_t mask
)
570 /* get pointers to arch-specific information */
571 armv4_5_common_t
*armv4_5
= target
->arch_info
;
572 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
573 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
575 /* put system-speed store-multiple into the pipeline */
576 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
577 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
578 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), NULL
, 0);
581 void arm7tdmi_store_hword_reg(target_t
*target
, int num
)
583 /* get pointers to arch-specific information */
584 armv4_5_common_t
*armv4_5
= target
->arch_info
;
585 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
586 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
588 /* put system-speed store half-word into the pipeline */
589 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
590 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
591 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), NULL
, 0);
594 void arm7tdmi_store_byte_reg(target_t
*target
, int num
)
596 /* get pointers to arch-specific information */
597 armv4_5_common_t
*armv4_5
= target
->arch_info
;
598 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
599 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
601 /* put system-speed store byte into the pipeline */
602 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
603 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
604 arm7tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), NULL
, 0);
607 void arm7tdmi_write_pc(target_t
*target
, uint32_t pc
)
609 /* get pointers to arch-specific information */
610 armv4_5_common_t
*armv4_5
= target
->arch_info
;
611 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
612 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
614 /* LDMIA r0-15, [r0] at debug speed
615 * register values will start to appear on 4th DCLK
617 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL
, 0);
618 /* fetch NOP, LDM in DECODE stage */
619 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
620 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
621 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
622 /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
623 arm7tdmi_clock_out_inner(jtag_info
, pc
, 0);
624 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
625 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
626 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
627 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
628 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
629 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
630 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
631 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_NOP
, 0);
634 void arm7tdmi_branch_resume(target_t
*target
)
636 /* get pointers to arch-specific information */
637 armv4_5_common_t
*armv4_5
= target
->arch_info
;
638 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
639 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
641 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 1);
642 arm7tdmi_clock_out_inner(jtag_info
, ARMV4_5_B(0xfffffa, 0), 0);
645 void arm7tdmi_branch_resume_thumb(target_t
*target
)
649 /* get pointers to arch-specific information */
650 armv4_5_common_t
*armv4_5
= target
->arch_info
;
651 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
652 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
653 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
655 /* LDMIA r0, [r0] at debug speed
656 * register values will start to appear on 4th DCLK
658 arm7tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL
, 0);
660 /* fetch NOP, LDM in DECODE stage */
661 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
662 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
663 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
664 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
665 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
666 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
667 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
669 /* Branch and eXchange */
670 arm7tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), NULL
, 0);
672 embeddedice_read_reg(dbg_stat
);
674 /* fetch NOP, BX in DECODE stage */
675 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
677 /* target is now in Thumb state */
678 embeddedice_read_reg(dbg_stat
);
680 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
681 arm7tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, NULL
, 0);
683 /* target is now in Thumb state */
684 embeddedice_read_reg(dbg_stat
);
687 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), NULL
, 0);
688 /* fetch NOP, LDR in Decode */
689 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
690 /* fetch NOP, LDR in Execute */
691 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
692 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
693 arm7tdmi_clock_out(jtag_info
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
694 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
695 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
697 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
698 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 0);
700 embeddedice_read_reg(dbg_stat
);
702 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, NULL
, 1);
703 arm7tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f8), NULL
, 0);
706 void arm7tdmi_build_reg_cache(target_t
*target
)
708 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
709 /* get pointers to arch-specific information */
710 armv4_5_common_t
*armv4_5
= target
->arch_info
;
712 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
713 armv4_5
->core_cache
= (*cache_p
);
716 int arm7tdmi_examine(struct target_s
*target
)
719 armv4_5_common_t
*armv4_5
= target
->arch_info
;
720 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
721 if (!target_was_examined(target
))
723 /* get pointers to arch-specific information */
724 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
725 reg_cache_t
*t
= embeddedice_build_reg_cache(target
, arm7_9
);
730 arm7_9
->eice_cache
= (*cache_p
);
734 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
735 (*cache_p
)->next
= etm_build_reg_cache(target
, jtag_info
, arm7_9
->etm_ctx
);
736 arm7_9
->etm_ctx
->reg_cache
= (*cache_p
)->next
;
738 target_set_examined(target
);
740 if ((retval
= embeddedice_setup(target
)) != ERROR_OK
)
742 if ((retval
= arm7_9_setup(target
)) != ERROR_OK
)
746 if ((retval
= etm_setup(target
)) != ERROR_OK
)
752 int arm7tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
754 arm7tdmi_build_reg_cache(target
);
759 int arm7tdmi_init_arch_info(target_t
*target
, arm7tdmi_common_t
*arm7tdmi
, jtag_tap_t
*tap
)
761 armv4_5_common_t
*armv4_5
;
762 arm7_9_common_t
*arm7_9
;
764 arm7_9
= &arm7tdmi
->arm7_9_common
;
765 armv4_5
= &arm7_9
->armv4_5_common
;
767 /* prepare JTAG information for the new target */
768 arm7_9
->jtag_info
.tap
= tap
;
769 arm7_9
->jtag_info
.scann_size
= 4;
771 /* register arch-specific functions */
772 arm7_9
->examine_debug_reason
= arm7tdmi_examine_debug_reason
;
773 arm7_9
->change_to_arm
= arm7tdmi_change_to_arm
;
774 arm7_9
->read_core_regs
= arm7tdmi_read_core_regs
;
775 arm7_9
->read_core_regs_target_buffer
= arm7tdmi_read_core_regs_target_buffer
;
776 arm7_9
->read_xpsr
= arm7tdmi_read_xpsr
;
778 arm7_9
->write_xpsr
= arm7tdmi_write_xpsr
;
779 arm7_9
->write_xpsr_im8
= arm7tdmi_write_xpsr_im8
;
780 arm7_9
->write_core_regs
= arm7tdmi_write_core_regs
;
782 arm7_9
->load_word_regs
= arm7tdmi_load_word_regs
;
783 arm7_9
->load_hword_reg
= arm7tdmi_load_hword_reg
;
784 arm7_9
->load_byte_reg
= arm7tdmi_load_byte_reg
;
786 arm7_9
->store_word_regs
= arm7tdmi_store_word_regs
;
787 arm7_9
->store_hword_reg
= arm7tdmi_store_hword_reg
;
788 arm7_9
->store_byte_reg
= arm7tdmi_store_byte_reg
;
790 arm7_9
->write_pc
= arm7tdmi_write_pc
;
791 arm7_9
->branch_resume
= arm7tdmi_branch_resume
;
792 arm7_9
->branch_resume_thumb
= arm7tdmi_branch_resume_thumb
;
794 arm7_9
->enable_single_step
= arm7_9_enable_eice_step
;
795 arm7_9
->disable_single_step
= arm7_9_disable_eice_step
;
797 arm7_9
->post_debug_entry
= NULL
;
799 arm7_9
->pre_restore_context
= NULL
;
800 arm7_9
->post_restore_context
= NULL
;
802 /* initialize arch-specific breakpoint handling */
803 arm7_9
->arm_bkpt
= 0xdeeedeee;
804 arm7_9
->thumb_bkpt
= 0xdeee;
806 arm7_9
->dbgreq_adjust_pc
= 2;
807 arm7_9
->arch_info
= arm7tdmi
;
809 arm7tdmi
->arch_info
= NULL
;
810 arm7tdmi
->common_magic
= ARM7TDMI_COMMON_MAGIC
;
812 arm7_9_init_arch_info(target
, arm7_9
);
817 int arm7tdmi_target_create(struct target_s
*target
, Jim_Interp
*interp
)
819 arm7tdmi_common_t
*arm7tdmi
;
821 arm7tdmi
= calloc(1,sizeof(arm7tdmi_common_t
));
822 arm7tdmi_init_arch_info(target
, arm7tdmi
, target
->tap
);
823 arm7tdmi
->arm7_9_common
.armv4_5_common
.is_armv4
= true;
828 int arm7tdmi_register_commands(struct command_context_s
*cmd_ctx
)
832 retval
= arm7_9_register_commands(cmd_ctx
);
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