- split fileio handling into fileio part and image handling
[openocd.git] / src / target / arm7_9_common.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifndef ARM7_9_COMMON_H
21 #define ARM7_9_COMMON_H
22
23 #include "armv4_5.h"
24 #include "arm_jtag.h"
25 #include "breakpoints.h"
26 #include "target.h"
27
28 #include "etm.h"
29
30 #define ARM7_9_COMMON_MAGIC 0x0a790a79
31
32 typedef struct arm7_9_common_s
33 {
34 int common_magic;
35
36 arm_jtag_t jtag_info;
37 reg_cache_t *eice_cache;
38
39 u32 arm_bkpt;
40 u16 thumb_bkpt;
41 int sw_bkpts_use_wp;
42 int wp_available;
43 int wp0_used;
44 int wp1_used;
45 int sw_bkpts_enabled;
46 int force_hw_bkpts;
47 int dbgreq_adjust_pc;
48 int use_dbgrq;
49
50 etm_context_t *etm_ctx;
51
52 int has_single_step;
53 int has_monitor_mode;
54 int has_vector_catch;
55
56 int reinit_embeddedice;
57 int debug_entry_from_reset;
58
59 struct working_area_s *dcc_working_area;
60
61 int fast_memory_access;
62 int dcc_downloads;
63
64 int (*examine_debug_reason)(target_t *target);
65
66 void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
67
68 void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
69 void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
70 void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr);
71
72 void (*write_xpsr)(target_t *target, u32 xpsr, int spsr);
73 void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
74 void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
75
76 void (*load_word_regs)(target_t *target, u32 mask);
77 void (*load_hword_reg)(target_t *target, int num);
78 void (*load_byte_reg)(target_t *target, int num);
79
80 void (*store_word_regs)(target_t *target, u32 mask);
81 void (*store_hword_reg)(target_t *target, int num);
82 void (*store_byte_reg)(target_t *target, int num);
83
84 void (*write_pc)(target_t *target, u32 pc);
85 void (*branch_resume)(target_t *target);
86 void (*branch_resume_thumb)(target_t *target);
87
88 void (*enable_single_step)(target_t *target);
89 void (*disable_single_step)(target_t *target);
90
91 void (*pre_debug_entry)(target_t *target);
92 void (*post_debug_entry)(target_t *target);
93
94 void (*pre_restore_context)(target_t *target);
95 void (*post_restore_context)(target_t *target);
96
97 armv4_5_common_t armv4_5_common;
98 void *arch_info;
99
100 } arm7_9_common_t;
101
102 int arm7_9_register_commands(struct command_context_s *cmd_ctx);
103
104 enum target_state arm7_9_poll(target_t *target);
105
106 int arm7_9_assert_reset(target_t *target);
107 int arm7_9_deassert_reset(target_t *target);
108 int arm7_9_reset_request_halt(target_t *target);
109 int arm7_9_early_halt(target_t *target);
110 int arm7_9_soft_reset_halt(struct target_s *target);
111 int arm7_9_prepare_reset_halt(struct target_s *target);
112
113 int arm7_9_halt(target_t *target);
114 int arm7_9_debug_entry(target_t *target);
115 int arm7_9_full_context(target_t *target);
116 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
117 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
118 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
119 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
120 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
121 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
122
123 int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, u32 entry_point, void *arch_info);
124
125 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
126 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
127 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
128 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
129
130 void arm7_9_enable_eice_step(target_t *target);
131 void arm7_9_disable_eice_step(target_t *target);
132
133 int arm7_9_execute_sys_speed(struct target_s *target);
134
135 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
136 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
137
138
139 #endif /* ARM7_9_COMMON_H */