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- changed jtag_add_reset errors to warnings
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "embeddedice.h"
27 #include "target.h"
28 #include "target_request.h"
29 #include "armv4_5.h"
30 #include "arm_jtag.h"
31 #include "jtag.h"
32 #include "log.h"
33 #include "arm7_9_common.h"
34 #include "breakpoints.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38 #include <unistd.h>
39
40 #include <sys/types.h>
41 #include <sys/stat.h>
42 #include <sys/time.h>
43 #include <errno.h>
44
45 int arm7_9_debug_entry(target_t *target);
46 int arm7_9_enable_sw_bkpts(struct target_s *target);
47
48 /* command handler forward declarations */
49 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59
60 int arm7_9_reinit_embeddedice(target_t *target)
61 {
62 armv4_5_common_t *armv4_5 = target->arch_info;
63 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
64
65 breakpoint_t *breakpoint = target->breakpoints;
66
67 arm7_9->wp_available = 2;
68 arm7_9->wp0_used = 0;
69 arm7_9->wp1_used = 0;
70
71 /* mark all hardware breakpoints as unset */
72 while (breakpoint)
73 {
74 if (breakpoint->type == BKPT_HARD)
75 {
76 breakpoint->set = 0;
77 }
78 breakpoint = breakpoint->next;
79 }
80
81 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
82 {
83 arm7_9->sw_bkpts_enabled = 0;
84 arm7_9_enable_sw_bkpts(target);
85 }
86
87 arm7_9->reinit_embeddedice = 0;
88
89 return ERROR_OK;
90 }
91
92 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
93 {
94 target_t *target = priv;
95 armv4_5_common_t *armv4_5 = target->arch_info;
96 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
97
98 /* a test-logic reset occured
99 * the EmbeddedICE registers have been reset
100 * hardware breakpoints have been cleared
101 */
102 if (event == JTAG_TRST_ASSERTED)
103 {
104 arm7_9->reinit_embeddedice = 1;
105 }
106
107 return ERROR_OK;
108 }
109
110 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
111 {
112 armv4_5_common_t *armv4_5 = target->arch_info;
113 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
114
115 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
116 {
117 return -1;
118 }
119
120 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
121 {
122 return -1;
123 }
124
125 *armv4_5_p = armv4_5;
126 *arm7_9_p = arm7_9;
127
128 return ERROR_OK;
129 }
130
131 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
132 {
133 armv4_5_common_t *armv4_5 = target->arch_info;
134 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
135
136 if (target->state != TARGET_HALTED)
137 {
138 WARNING("target not halted");
139 return ERROR_TARGET_NOT_HALTED;
140 }
141
142 if (arm7_9->force_hw_bkpts)
143 breakpoint->type = BKPT_HARD;
144
145 if (breakpoint->set)
146 {
147 WARNING("breakpoint already set");
148 return ERROR_OK;
149 }
150
151 if (breakpoint->type == BKPT_HARD)
152 {
153 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
154 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
155 if (!arm7_9->wp0_used)
156 {
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
162
163 jtag_execute_queue();
164 arm7_9->wp0_used = 1;
165 breakpoint->set = 1;
166 }
167 else if (!arm7_9->wp1_used)
168 {
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
172 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
173 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
174
175 jtag_execute_queue();
176 arm7_9->wp1_used = 1;
177 breakpoint->set = 2;
178 }
179 else
180 {
181 ERROR("BUG: no hardware comparator available");
182 return ERROR_OK;
183 }
184 }
185 else if (breakpoint->type == BKPT_SOFT)
186 {
187 if (breakpoint->length == 4)
188 {
189 u32 verify = 0xffffffff;
190 /* keep the original instruction in target endianness */
191 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
192 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
193 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
194
195 target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
196 if (verify != arm7_9->arm_bkpt)
197 {
198 ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
199 return ERROR_OK;
200 }
201 }
202 else
203 {
204 u16 verify = 0xffff;
205 /* keep the original instruction in target endianness */
206 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
207 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
208 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
209
210 target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
211 if (verify != arm7_9->thumb_bkpt)
212 {
213 ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
214 return ERROR_OK;
215 }
216 }
217 breakpoint->set = 1;
218 }
219
220 return ERROR_OK;
221
222 }
223
224 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
225 {
226 armv4_5_common_t *armv4_5 = target->arch_info;
227 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
228
229 if (target->state != TARGET_HALTED)
230 {
231 WARNING("target not halted");
232 return ERROR_TARGET_NOT_HALTED;
233 }
234
235 if (!breakpoint->set)
236 {
237 WARNING("breakpoint not set");
238 return ERROR_OK;
239 }
240
241 if (breakpoint->type == BKPT_HARD)
242 {
243 if (breakpoint->set == 1)
244 {
245 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
246 jtag_execute_queue();
247 arm7_9->wp0_used = 0;
248 }
249 else if (breakpoint->set == 2)
250 {
251 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
252 jtag_execute_queue();
253 arm7_9->wp1_used = 0;
254 }
255 breakpoint->set = 0;
256 }
257 else
258 {
259 /* restore original instruction (kept in target endianness) */
260 if (breakpoint->length == 4)
261 {
262 u32 current_instr;
263 /* check that user program as not modified breakpoint instruction */
264 target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
265 if (current_instr==arm7_9->arm_bkpt)
266 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
267 }
268 else
269 {
270 u16 current_instr;
271 /* check that user program as not modified breakpoint instruction */
272 target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
273 if (current_instr==arm7_9->thumb_bkpt)
274 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
275 }
276 breakpoint->set = 0;
277 }
278
279 return ERROR_OK;
280 }
281
282 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
283 {
284 armv4_5_common_t *armv4_5 = target->arch_info;
285 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
286
287 if (target->state != TARGET_HALTED)
288 {
289 WARNING("target not halted");
290 return ERROR_TARGET_NOT_HALTED;
291 }
292
293 if (arm7_9->force_hw_bkpts)
294 {
295 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
296 breakpoint->type = BKPT_HARD;
297 }
298
299 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
300 {
301 INFO("sw breakpoint requested, but software breakpoints not enabled");
302 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
303 }
304
305 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
306 {
307 INFO("no watchpoint unit available for hardware breakpoint");
308 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
309 }
310
311 if ((breakpoint->length != 2) && (breakpoint->length != 4))
312 {
313 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
314 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
315 }
316
317 if (breakpoint->type == BKPT_HARD)
318 arm7_9->wp_available--;
319
320 return ERROR_OK;
321 }
322
323 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
324 {
325 armv4_5_common_t *armv4_5 = target->arch_info;
326 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
327
328 if (target->state != TARGET_HALTED)
329 {
330 WARNING("target not halted");
331 return ERROR_TARGET_NOT_HALTED;
332 }
333
334 if (breakpoint->set)
335 {
336 arm7_9_unset_breakpoint(target, breakpoint);
337 }
338
339 if (breakpoint->type == BKPT_HARD)
340 arm7_9->wp_available++;
341
342 return ERROR_OK;
343 }
344
345 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
346 {
347 armv4_5_common_t *armv4_5 = target->arch_info;
348 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
349 int rw_mask = 1;
350 u32 mask;
351
352 mask = watchpoint->length - 1;
353
354 if (target->state != TARGET_HALTED)
355 {
356 WARNING("target not halted");
357 return ERROR_TARGET_NOT_HALTED;
358 }
359
360 if (watchpoint->rw == WPT_ACCESS)
361 rw_mask = 0;
362 else
363 rw_mask = 1;
364
365 if (!arm7_9->wp0_used)
366 {
367 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
368 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
369 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
370 if( watchpoint->mask != 0xffffffffu )
371 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
372 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
373 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
374
375 jtag_execute_queue();
376 watchpoint->set = 1;
377 arm7_9->wp0_used = 2;
378 }
379 else if (!arm7_9->wp1_used)
380 {
381 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
382 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
383 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
384 if( watchpoint->mask != 0xffffffffu )
385 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
386 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
387 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
388
389 jtag_execute_queue();
390 watchpoint->set = 2;
391 arm7_9->wp1_used = 2;
392 }
393 else
394 {
395 ERROR("BUG: no hardware comparator available");
396 return ERROR_OK;
397 }
398
399 return ERROR_OK;
400 }
401
402 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
403 {
404 armv4_5_common_t *armv4_5 = target->arch_info;
405 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
406
407 if (target->state != TARGET_HALTED)
408 {
409 WARNING("target not halted");
410 return ERROR_TARGET_NOT_HALTED;
411 }
412
413 if (!watchpoint->set)
414 {
415 WARNING("breakpoint not set");
416 return ERROR_OK;
417 }
418
419 if (watchpoint->set == 1)
420 {
421 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
422 jtag_execute_queue();
423 arm7_9->wp0_used = 0;
424 }
425 else if (watchpoint->set == 2)
426 {
427 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
428 jtag_execute_queue();
429 arm7_9->wp1_used = 0;
430 }
431 watchpoint->set = 0;
432
433 return ERROR_OK;
434 }
435
436 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
437 {
438 armv4_5_common_t *armv4_5 = target->arch_info;
439 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
440
441 if (target->state != TARGET_HALTED)
442 {
443 WARNING("target not halted");
444 return ERROR_TARGET_NOT_HALTED;
445 }
446
447 if (arm7_9->wp_available < 1)
448 {
449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
450 }
451
452 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
453 {
454 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
455 }
456
457 arm7_9->wp_available--;
458
459 return ERROR_OK;
460 }
461
462 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
463 {
464 armv4_5_common_t *armv4_5 = target->arch_info;
465 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
466
467 if (target->state != TARGET_HALTED)
468 {
469 WARNING("target not halted");
470 return ERROR_TARGET_NOT_HALTED;
471 }
472
473 if (watchpoint->set)
474 {
475 arm7_9_unset_watchpoint(target, watchpoint);
476 }
477
478 arm7_9->wp_available++;
479
480 return ERROR_OK;
481 }
482
483 int arm7_9_enable_sw_bkpts(struct target_s *target)
484 {
485 armv4_5_common_t *armv4_5 = target->arch_info;
486 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
487 int retval;
488
489 if (arm7_9->sw_bkpts_enabled)
490 return ERROR_OK;
491
492 if (arm7_9->wp_available < 1)
493 {
494 WARNING("can't enable sw breakpoints with no watchpoint unit available");
495 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
496 }
497 arm7_9->wp_available--;
498
499 if (!arm7_9->wp0_used)
500 {
501 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
502 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
503 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
504 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
505 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
506 arm7_9->sw_bkpts_enabled = 1;
507 arm7_9->wp0_used = 3;
508 }
509 else if (!arm7_9->wp1_used)
510 {
511 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
512 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
513 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
514 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
515 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
516 arm7_9->sw_bkpts_enabled = 2;
517 arm7_9->wp1_used = 3;
518 }
519 else
520 {
521 ERROR("BUG: both watchpoints used, but wp_available >= 1");
522 exit(-1);
523 }
524
525 if ((retval = jtag_execute_queue()) != ERROR_OK)
526 {
527 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
528 exit(-1);
529 };
530
531 return ERROR_OK;
532 }
533
534 int arm7_9_disable_sw_bkpts(struct target_s *target)
535 {
536 armv4_5_common_t *armv4_5 = target->arch_info;
537 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
538
539 if (!arm7_9->sw_bkpts_enabled)
540 return ERROR_OK;
541
542 if (arm7_9->sw_bkpts_enabled == 1)
543 {
544 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
545 arm7_9->sw_bkpts_enabled = 0;
546 arm7_9->wp0_used = 0;
547 arm7_9->wp_available++;
548 }
549 else if (arm7_9->sw_bkpts_enabled == 2)
550 {
551 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
552 arm7_9->sw_bkpts_enabled = 0;
553 arm7_9->wp1_used = 0;
554 arm7_9->wp_available++;
555 }
556
557 return ERROR_OK;
558 }
559
560 int arm7_9_execute_sys_speed(struct target_s *target)
561 {
562 int timeout;
563 int retval;
564
565 armv4_5_common_t *armv4_5 = target->arch_info;
566 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
567 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
568 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
569
570 /* set RESTART instruction */
571 jtag_add_end_state(TAP_RTI);
572 arm_jtag_set_instr(jtag_info, 0x4, NULL);
573
574 for (timeout=0; timeout<50; timeout++)
575 {
576 /* read debug status register */
577 embeddedice_read_reg(dbg_stat);
578 if ((retval = jtag_execute_queue()) != ERROR_OK)
579 return retval;
580 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
581 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
582 break;
583 usleep(100000);
584 }
585 if (timeout == 50)
586 {
587 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
588 return ERROR_TARGET_TIMEOUT;
589 }
590
591 return ERROR_OK;
592 }
593
594 int arm7_9_execute_fast_sys_speed(struct target_s *target)
595 {
596 static int set=0;
597 static u8 check_value[4], check_mask[4];
598
599 armv4_5_common_t *armv4_5 = target->arch_info;
600 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
601 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
602 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
603
604 /* set RESTART instruction */
605 jtag_add_end_state(TAP_RTI);
606 arm_jtag_set_instr(jtag_info, 0x4, NULL);
607
608 if (!set)
609 {
610 /* check for DBGACK and SYSCOMP set (others don't care) */
611
612 /* NB! These are constants that must be available until after next jtag_execute() and
613 we evaluate the values upon first execution in lieu of setting up these constants
614 during early setup.
615 */
616 buf_set_u32(check_value, 0, 32, 0x9);
617 buf_set_u32(check_mask, 0, 32, 0x9);
618 set=1;
619 }
620
621 /* read debug status register */
622 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
623
624 return ERROR_OK;
625 }
626
627 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
628 {
629 armv4_5_common_t *armv4_5 = target->arch_info;
630 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
631 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
632 u32 *data;
633 int i;
634
635 data = malloc(size * (sizeof(u32)));
636
637 embeddedice_receive(jtag_info, data, size);
638
639 for (i = 0; i < size; i++)
640 {
641 h_u32_to_le(buffer + (i * 4), data[i]);
642 }
643
644 free(data);
645
646 return ERROR_OK;
647 }
648
649 int arm7_9_handle_target_request(void *priv)
650 {
651 target_t *target = priv;
652 armv4_5_common_t *armv4_5 = target->arch_info;
653 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
654 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
655 reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
656
657 if (!target->dbg_msg_enabled)
658 return ERROR_OK;
659
660 if (target->state == TARGET_RUNNING)
661 {
662 /* read DCC control register */
663 embeddedice_read_reg(dcc_control);
664 jtag_execute_queue();
665
666 /* check W bit */
667 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
668 {
669 u32 request;
670
671 embeddedice_receive(jtag_info, &request, 1);
672 target_request(target, request);
673 }
674 }
675
676 return ERROR_OK;
677 }
678
679 int arm7_9_poll(target_t *target)
680 {
681 int retval;
682 armv4_5_common_t *armv4_5 = target->arch_info;
683 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
684 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
685
686 if (arm7_9->reinit_embeddedice)
687 {
688 arm7_9_reinit_embeddedice(target);
689 }
690
691 /* read debug status register */
692 embeddedice_read_reg(dbg_stat);
693 if ((retval = jtag_execute_queue()) != ERROR_OK)
694 {
695 return retval;
696 }
697
698 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
699 {
700 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
701 if (target->state == TARGET_UNKNOWN)
702 {
703 target->state = TARGET_RUNNING;
704 WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
705 }
706 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
707 {
708 target->state = TARGET_HALTED;
709 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
710 return retval;
711
712 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
713 }
714 if (target->state == TARGET_DEBUG_RUNNING)
715 {
716 target->state = TARGET_HALTED;
717 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
718 return retval;
719
720 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
721 }
722 if (target->state != TARGET_HALTED)
723 {
724 WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
725 }
726 }
727 else
728 {
729 if (target->state != TARGET_DEBUG_RUNNING)
730 target->state = TARGET_RUNNING;
731 }
732
733 return ERROR_OK;
734 }
735
736 int arm7_9_assert_reset(target_t *target)
737 {
738 int retval;
739
740 DEBUG("target->state: %s", target_state_strings[target->state]);
741
742 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
743 {
744 /* if the target wasn't running, there might be working areas allocated */
745 target_free_all_working_areas(target);
746
747 /* assert SRST and TRST */
748 /* system would get ouf sync if we didn't reset test-logic, too */
749 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
750 {
751 if (retval == ERROR_JTAG_RESET_CANT_SRST)
752 {
753 return retval;
754 }
755 else
756 {
757 ERROR("unknown error");
758 exit(-1);
759 }
760 }
761 jtag_add_sleep(5000);
762 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
763 {
764 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
765 {
766 retval = jtag_add_reset(1, 1);
767 }
768 }
769 }
770 else
771 {
772 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
773 {
774 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
775 {
776 retval = jtag_add_reset(1, 1);
777 }
778
779 if (retval == ERROR_JTAG_RESET_CANT_SRST)
780 {
781 return retval;
782 }
783 else if (retval != ERROR_OK)
784 {
785 ERROR("unknown error");
786 exit(-1);
787 }
788 }
789 }
790
791 target->state = TARGET_RESET;
792 jtag_add_sleep(50000);
793
794 armv4_5_invalidate_core_regs(target);
795
796 return ERROR_OK;
797
798 }
799
800 int arm7_9_deassert_reset(target_t *target)
801 {
802 DEBUG("target->state: %s", target_state_strings[target->state]);
803
804 /* deassert reset lines */
805 jtag_add_reset(0, 0);
806
807 return ERROR_OK;
808 }
809
810 int arm7_9_clear_halt(target_t *target)
811 {
812 armv4_5_common_t *armv4_5 = target->arch_info;
813 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
814 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
815
816 /* we used DBGRQ only if we didn't come out of reset */
817 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
818 {
819 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
820 */
821 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
822 embeddedice_store_reg(dbg_ctrl);
823 }
824 else
825 {
826 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
827 {
828 /* if we came out of reset, and vector catch is supported, we used
829 * vector catch to enter debug state
830 * restore the register in that case
831 */
832 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
833 }
834 else
835 {
836 /* restore registers if watchpoint unit 0 was in use
837 */
838 if (arm7_9->wp0_used)
839 {
840 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
841 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
842 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
843 }
844 /* control value always has to be restored, as it was either disabled,
845 * or enabled with possibly different bits
846 */
847 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
848 }
849 }
850
851 return ERROR_OK;
852 }
853
854 int arm7_9_soft_reset_halt(struct target_s *target)
855 {
856 armv4_5_common_t *armv4_5 = target->arch_info;
857 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
858 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
859 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
860 int i;
861 int retval;
862
863 if ((retval=target->type->halt(target))!=ERROR_OK)
864 return retval;
865
866 for (i=0; i<10; i++)
867 {
868 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
869 break;
870 embeddedice_read_reg(dbg_stat);
871 if ((retval=jtag_execute_queue())!=ERROR_OK)
872 return retval;
873 /* do not eat all CPU, time out after 1 se*/
874 usleep(100*1000);
875
876 }
877 if (i==10)
878 {
879 ERROR("Failed to halt CPU after 1 sec");
880 return ERROR_TARGET_TIMEOUT;
881 }
882 target->state = TARGET_HALTED;
883
884 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
885 * ensure that DBGRQ is cleared
886 */
887 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
888 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
889 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
890 embeddedice_store_reg(dbg_ctrl);
891
892 arm7_9_clear_halt(target);
893
894 /* if the target is in Thumb state, change to ARM state */
895 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
896 {
897 u32 r0_thumb, pc_thumb;
898 DEBUG("target entered debug from Thumb state, changing to ARM");
899 /* Entered debug from Thumb mode */
900 armv4_5->core_state = ARMV4_5_STATE_THUMB;
901 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
902 }
903
904 /* all register content is now invalid */
905 armv4_5_invalidate_core_regs(target);
906
907 /* SVC, ARM state, IRQ and FIQ disabled */
908 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
909 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
910 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
911
912 /* start fetching from 0x0 */
913 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
914 armv4_5->core_cache->reg_list[15].dirty = 1;
915 armv4_5->core_cache->reg_list[15].valid = 1;
916
917 armv4_5->core_mode = ARMV4_5_MODE_SVC;
918 armv4_5->core_state = ARMV4_5_STATE_ARM;
919
920 /* reset registers */
921 for (i = 0; i <= 14; i++)
922 {
923 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
924 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
925 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
926 }
927
928 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
929
930 return ERROR_OK;
931 }
932
933 int arm7_9_prepare_reset_halt(target_t *target)
934 {
935 armv4_5_common_t *armv4_5 = target->arch_info;
936 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
937
938 /* poll the target, and resume if it was currently halted */
939 arm7_9_poll(target);
940 if (target->state == TARGET_HALTED)
941 {
942 arm7_9_resume(target, 1, 0x0, 0, 1);
943 }
944
945 if (arm7_9->has_vector_catch)
946 {
947 /* program vector catch register to catch reset vector */
948 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
949 }
950 else
951 {
952 /* program watchpoint unit to match on reset vector address */
953 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
954 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
955 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
956 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
957 }
958
959 return ERROR_OK;
960 }
961
962 int arm7_9_halt(target_t *target)
963 {
964 armv4_5_common_t *armv4_5 = target->arch_info;
965 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
966 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
967
968 DEBUG("target->state: %s", target_state_strings[target->state]);
969
970 if (target->state == TARGET_HALTED)
971 {
972 WARNING("target was already halted");
973 return ERROR_OK;
974 }
975
976 if (target->state == TARGET_UNKNOWN)
977 {
978 WARNING("target was in unknown state when halt was requested");
979 }
980
981 if (target->state == TARGET_RESET)
982 {
983 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
984 {
985 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
986 return ERROR_TARGET_FAILURE;
987 }
988 else
989 {
990 /* we came here in a reset_halt or reset_init sequence
991 * debug entry was already prepared in arm7_9_prepare_reset_halt()
992 */
993 target->debug_reason = DBG_REASON_DBGRQ;
994
995 return ERROR_OK;
996 }
997 }
998
999 if (arm7_9->use_dbgrq)
1000 {
1001 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1002 */
1003 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1004 embeddedice_store_reg(dbg_ctrl);
1005 }
1006 else
1007 {
1008 /* program watchpoint unit to match on any address
1009 */
1010 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1011 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1012 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1013 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
1014 }
1015
1016 target->debug_reason = DBG_REASON_DBGRQ;
1017
1018 return ERROR_OK;
1019 }
1020
1021 int arm7_9_debug_entry(target_t *target)
1022 {
1023 int i;
1024 u32 context[16];
1025 u32* context_p[16];
1026 u32 r0_thumb, pc_thumb;
1027 u32 cpsr;
1028 int retval;
1029 /* get pointers to arch-specific information */
1030 armv4_5_common_t *armv4_5 = target->arch_info;
1031 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1032 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1033 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1034
1035 #ifdef _DEBUG_ARM7_9_
1036 DEBUG("-");
1037 #endif
1038
1039 if (arm7_9->pre_debug_entry)
1040 arm7_9->pre_debug_entry(target);
1041
1042 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1043 * ensure that DBGRQ is cleared
1044 */
1045 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1046 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1047 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1048 embeddedice_store_reg(dbg_ctrl);
1049
1050 arm7_9_clear_halt(target);
1051
1052 if ((retval = jtag_execute_queue()) != ERROR_OK)
1053 {
1054 switch (retval)
1055 {
1056 case ERROR_JTAG_QUEUE_FAILED:
1057 ERROR("JTAG queue failed while writing EmbeddedICE control register");
1058 exit(-1);
1059 break;
1060 default:
1061 break;
1062 }
1063 }
1064
1065 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1066 return retval;
1067
1068
1069 if (target->state != TARGET_HALTED)
1070 {
1071 WARNING("target not halted");
1072 return ERROR_TARGET_NOT_HALTED;
1073 }
1074
1075 /* if the target is in Thumb state, change to ARM state */
1076 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1077 {
1078 DEBUG("target entered debug from Thumb state");
1079 /* Entered debug from Thumb mode */
1080 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1081 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1082 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
1083 }
1084 else
1085 {
1086 DEBUG("target entered debug from ARM state");
1087 /* Entered debug from ARM mode */
1088 armv4_5->core_state = ARMV4_5_STATE_ARM;
1089 }
1090
1091 for (i = 0; i < 16; i++)
1092 context_p[i] = &context[i];
1093 /* save core registers (r0 - r15 of current core mode) */
1094 arm7_9->read_core_regs(target, 0xffff, context_p);
1095
1096 arm7_9->read_xpsr(target, &cpsr, 0);
1097
1098 if ((retval = jtag_execute_queue()) != ERROR_OK)
1099 return retval;
1100
1101 /* if the core has been executing in Thumb state, set the T bit */
1102 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1103 cpsr |= 0x20;
1104
1105 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1106 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1107 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1108
1109 armv4_5->core_mode = cpsr & 0x1f;
1110
1111 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1112 {
1113 target->state = TARGET_UNKNOWN;
1114 ERROR("cpsr contains invalid mode value - communication failure");
1115 return ERROR_TARGET_FAILURE;
1116 }
1117
1118 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1119
1120 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1121 {
1122 DEBUG("thumb state, applying fixups");
1123 context[0] = r0_thumb;
1124 context[15] = pc_thumb;
1125 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1126 {
1127 /* adjust value stored by STM */
1128 context[15] -= 3 * 4;
1129 }
1130
1131 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1132 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1133 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1134 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1135 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1136 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1137 else if (target->debug_reason == DBG_REASON_DBGRQ)
1138 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1139 else
1140 {
1141 ERROR("unknown debug reason: %i", target->debug_reason);
1142 }
1143
1144
1145 for (i=0; i<=15; i++)
1146 {
1147 DEBUG("r%i: 0x%8.8x", i, context[i]);
1148 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1149 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1150 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1151 }
1152
1153 DEBUG("entered debug state at PC 0x%x", context[15]);
1154
1155 /* exceptions other than USR & SYS have a saved program status register */
1156 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1157 {
1158 u32 spsr;
1159 arm7_9->read_xpsr(target, &spsr, 1);
1160 jtag_execute_queue();
1161 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1162 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1163 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1164 }
1165
1166 /* r0 and r15 (pc) have to be restored later */
1167 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1168 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
1169
1170 if ((retval = jtag_execute_queue()) != ERROR_OK)
1171 return retval;
1172
1173 if (arm7_9->post_debug_entry)
1174 arm7_9->post_debug_entry(target);
1175
1176 return ERROR_OK;
1177 }
1178
1179 int arm7_9_full_context(target_t *target)
1180 {
1181 int i;
1182 int retval;
1183 armv4_5_common_t *armv4_5 = target->arch_info;
1184 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1185
1186 DEBUG("-");
1187
1188 if (target->state != TARGET_HALTED)
1189 {
1190 WARNING("target not halted");
1191 return ERROR_TARGET_NOT_HALTED;
1192 }
1193
1194 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1195 * SYS shares registers with User, so we don't touch SYS
1196 */
1197 for(i = 0; i < 6; i++)
1198 {
1199 u32 mask = 0;
1200 u32* reg_p[16];
1201 int j;
1202 int valid = 1;
1203
1204 /* check if there are invalid registers in the current mode
1205 */
1206 for (j = 0; j <= 16; j++)
1207 {
1208 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1209 valid = 0;
1210 }
1211
1212 if (!valid)
1213 {
1214 u32 tmp_cpsr;
1215
1216 /* change processor mode (and mask T bit) */
1217 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1218 tmp_cpsr |= armv4_5_number_to_mode(i);
1219 tmp_cpsr &= ~0x20;
1220 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1221
1222 for (j = 0; j < 15; j++)
1223 {
1224 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1225 {
1226 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1227 mask |= 1 << j;
1228 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1229 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1230 }
1231 }
1232
1233 /* if only the PSR is invalid, mask is all zeroes */
1234 if (mask)
1235 arm7_9->read_core_regs(target, mask, reg_p);
1236
1237 /* check if the PSR has to be read */
1238 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1239 {
1240 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1241 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1242 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1243 }
1244 }
1245 }
1246
1247 /* restore processor mode (mask T bit) */
1248 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1249
1250 if ((retval = jtag_execute_queue()) != ERROR_OK)
1251 {
1252 ERROR("JTAG failure");
1253 exit(-1);
1254 }
1255 return ERROR_OK;
1256 }
1257
1258 int arm7_9_restore_context(target_t *target)
1259 {
1260 armv4_5_common_t *armv4_5 = target->arch_info;
1261 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1262 reg_t *reg;
1263 armv4_5_core_reg_t *reg_arch_info;
1264 enum armv4_5_mode current_mode = armv4_5->core_mode;
1265 int i, j;
1266 int dirty;
1267 int mode_change;
1268
1269 DEBUG("-");
1270
1271 if (target->state != TARGET_HALTED)
1272 {
1273 WARNING("target not halted");
1274 return ERROR_TARGET_NOT_HALTED;
1275 }
1276
1277 if (arm7_9->pre_restore_context)
1278 arm7_9->pre_restore_context(target);
1279
1280 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1281 * SYS shares registers with User, so we don't touch SYS
1282 */
1283 for (i = 0; i < 6; i++)
1284 {
1285 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1286 dirty = 0;
1287 mode_change = 0;
1288 /* check if there are dirty registers in the current mode
1289 */
1290 for (j = 0; j <= 16; j++)
1291 {
1292 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1293 reg_arch_info = reg->arch_info;
1294 if (reg->dirty == 1)
1295 {
1296 if (reg->valid == 1)
1297 {
1298 dirty = 1;
1299 DEBUG("examining dirty reg: %s", reg->name);
1300 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1301 && (reg_arch_info->mode != current_mode)
1302 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1303 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1304 {
1305 mode_change = 1;
1306 DEBUG("require mode change");
1307 }
1308 }
1309 else
1310 {
1311 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1312 }
1313 }
1314 }
1315
1316 if (dirty)
1317 {
1318 u32 mask = 0x0;
1319 int num_regs = 0;
1320 u32 regs[16];
1321
1322 if (mode_change)
1323 {
1324 u32 tmp_cpsr;
1325
1326 /* change processor mode (mask T bit) */
1327 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1328 tmp_cpsr |= armv4_5_number_to_mode(i);
1329 tmp_cpsr &= ~0x20;
1330 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1331 current_mode = armv4_5_number_to_mode(i);
1332 }
1333
1334 for (j = 0; j <= 14; j++)
1335 {
1336 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1337 reg_arch_info = reg->arch_info;
1338
1339
1340 if (reg->dirty == 1)
1341 {
1342 regs[j] = buf_get_u32(reg->value, 0, 32);
1343 mask |= 1 << j;
1344 num_regs++;
1345 reg->dirty = 0;
1346 reg->valid = 1;
1347 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1348 }
1349 }
1350
1351 if (mask)
1352 {
1353 arm7_9->write_core_regs(target, mask, regs);
1354 }
1355
1356 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1357 reg_arch_info = reg->arch_info;
1358 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1359 {
1360 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1361 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1362 }
1363 }
1364 }
1365
1366 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1367 {
1368 /* restore processor mode (mask T bit) */
1369 u32 tmp_cpsr;
1370
1371 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1372 tmp_cpsr |= armv4_5_number_to_mode(i);
1373 tmp_cpsr &= ~0x20;
1374 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1375 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1376 }
1377 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1378 {
1379 /* CPSR has been changed, full restore necessary (mask T bit) */
1380 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1381 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1382 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1383 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1384 }
1385
1386 /* restore PC */
1387 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1388 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1389 armv4_5->core_cache->reg_list[15].dirty = 0;
1390
1391 if (arm7_9->post_restore_context)
1392 arm7_9->post_restore_context(target);
1393
1394 return ERROR_OK;
1395 }
1396
1397 int arm7_9_restart_core(struct target_s *target)
1398 {
1399 armv4_5_common_t *armv4_5 = target->arch_info;
1400 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1401 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1402
1403 /* set RESTART instruction */
1404 jtag_add_end_state(TAP_RTI);
1405 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1406
1407 jtag_add_runtest(1, TAP_RTI);
1408 if ((jtag_execute_queue()) != ERROR_OK)
1409 {
1410 exit(-1);
1411 }
1412
1413 return ERROR_OK;
1414 }
1415
1416 void arm7_9_enable_watchpoints(struct target_s *target)
1417 {
1418 watchpoint_t *watchpoint = target->watchpoints;
1419
1420 while (watchpoint)
1421 {
1422 if (watchpoint->set == 0)
1423 arm7_9_set_watchpoint(target, watchpoint);
1424 watchpoint = watchpoint->next;
1425 }
1426 }
1427
1428 void arm7_9_enable_breakpoints(struct target_s *target)
1429 {
1430 breakpoint_t *breakpoint = target->breakpoints;
1431
1432 /* set any pending breakpoints */
1433 while (breakpoint)
1434 {
1435 if (breakpoint->set == 0)
1436 arm7_9_set_breakpoint(target, breakpoint);
1437 breakpoint = breakpoint->next;
1438 }
1439 }
1440
1441 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1442 {
1443 breakpoint_t *breakpoint = target->breakpoints;
1444 watchpoint_t *watchpoint = target->watchpoints;
1445
1446 /* set any pending breakpoints */
1447 while (breakpoint)
1448 {
1449 if (breakpoint->set != 0)
1450 arm7_9_unset_breakpoint(target, breakpoint);
1451 breakpoint = breakpoint->next;
1452 }
1453
1454 while (watchpoint)
1455 {
1456 if (watchpoint->set != 0)
1457 arm7_9_unset_watchpoint(target, watchpoint);
1458 watchpoint = watchpoint->next;
1459 }
1460 }
1461
1462 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1463 {
1464 armv4_5_common_t *armv4_5 = target->arch_info;
1465 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1466 breakpoint_t *breakpoint = target->breakpoints;
1467 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1468 int err;
1469
1470 DEBUG("-");
1471
1472 if (target->state != TARGET_HALTED)
1473 {
1474 WARNING("target not halted");
1475 return ERROR_TARGET_NOT_HALTED;
1476 }
1477
1478 if (!debug_execution)
1479 {
1480 target_free_all_working_areas(target);
1481 }
1482
1483 /* current = 1: continue on current pc, otherwise continue at <address> */
1484 if (!current)
1485 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1486
1487 /* the front-end may request us not to handle breakpoints */
1488 if (handle_breakpoints)
1489 {
1490 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1491 {
1492 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1493 arm7_9_unset_breakpoint(target, breakpoint);
1494
1495 DEBUG("enable single-step");
1496 arm7_9->enable_single_step(target);
1497
1498 target->debug_reason = DBG_REASON_SINGLESTEP;
1499
1500 arm7_9_restore_context(target);
1501
1502 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1503 arm7_9->branch_resume(target);
1504 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1505 {
1506 arm7_9->branch_resume_thumb(target);
1507 }
1508 else
1509 {
1510 ERROR("unhandled core state");
1511 exit(-1);
1512 }
1513
1514 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1515 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1516 err = arm7_9_execute_sys_speed(target);
1517
1518 DEBUG("disable single-step");
1519 arm7_9->disable_single_step(target);
1520
1521 if (err != ERROR_OK)
1522 {
1523 arm7_9_set_breakpoint(target, breakpoint);
1524 target->state = TARGET_UNKNOWN;
1525 return err;
1526 }
1527
1528 arm7_9_debug_entry(target);
1529 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1530
1531 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1532 arm7_9_set_breakpoint(target, breakpoint);
1533 }
1534 }
1535
1536 /* enable any pending breakpoints and watchpoints */
1537 arm7_9_enable_breakpoints(target);
1538 arm7_9_enable_watchpoints(target);
1539
1540 arm7_9_restore_context(target);
1541
1542 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1543 {
1544 arm7_9->branch_resume(target);
1545 }
1546 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1547 {
1548 arm7_9->branch_resume_thumb(target);
1549 }
1550 else
1551 {
1552 ERROR("unhandled core state");
1553 exit(-1);
1554 }
1555
1556 /* deassert DBGACK and INTDIS */
1557 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1558 /* INTDIS only when we really resume, not during debug execution */
1559 if (!debug_execution)
1560 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1561 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1562
1563 arm7_9_restart_core(target);
1564
1565 target->debug_reason = DBG_REASON_NOTHALTED;
1566
1567 if (!debug_execution)
1568 {
1569 /* registers are now invalid */
1570 armv4_5_invalidate_core_regs(target);
1571 target->state = TARGET_RUNNING;
1572 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1573 }
1574 else
1575 {
1576 target->state = TARGET_DEBUG_RUNNING;
1577 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1578 }
1579
1580 DEBUG("target resumed");
1581
1582 return ERROR_OK;
1583 }
1584
1585 void arm7_9_enable_eice_step(target_t *target)
1586 {
1587 armv4_5_common_t *armv4_5 = target->arch_info;
1588 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1589
1590 /* setup an inverse breakpoint on the current PC
1591 * - comparator 1 matches the current address
1592 * - rangeout from comparator 1 is connected to comparator 0 rangein
1593 * - comparator 0 matches any address, as long as rangein is low */
1594 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1595 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1596 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1597 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1598 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1599 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1600 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1601 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1602 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1603 }
1604
1605 void arm7_9_disable_eice_step(target_t *target)
1606 {
1607 armv4_5_common_t *armv4_5 = target->arch_info;
1608 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1609
1610 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1611 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1612 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1613 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1614 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1615 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1616 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1617 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1618 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1619 }
1620
1621 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1622 {
1623 armv4_5_common_t *armv4_5 = target->arch_info;
1624 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1625 breakpoint_t *breakpoint = NULL;
1626 int err;
1627
1628 if (target->state != TARGET_HALTED)
1629 {
1630 WARNING("target not halted");
1631 return ERROR_TARGET_NOT_HALTED;
1632 }
1633
1634 /* current = 1: continue on current pc, otherwise continue at <address> */
1635 if (!current)
1636 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1637
1638 /* the front-end may request us not to handle breakpoints */
1639 if (handle_breakpoints)
1640 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1641 arm7_9_unset_breakpoint(target, breakpoint);
1642
1643 target->debug_reason = DBG_REASON_SINGLESTEP;
1644
1645 arm7_9_restore_context(target);
1646
1647 arm7_9->enable_single_step(target);
1648
1649 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1650 {
1651 arm7_9->branch_resume(target);
1652 }
1653 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1654 {
1655 arm7_9->branch_resume_thumb(target);
1656 }
1657 else
1658 {
1659 ERROR("unhandled core state");
1660 exit(-1);
1661 }
1662
1663 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1664
1665 err = arm7_9_execute_sys_speed(target);
1666 arm7_9->disable_single_step(target);
1667
1668 /* registers are now invalid */
1669 armv4_5_invalidate_core_regs(target);
1670
1671 if (err != ERROR_OK)
1672 {
1673 target->state = TARGET_UNKNOWN;
1674 } else {
1675 arm7_9_debug_entry(target);
1676 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1677 DEBUG("target stepped");
1678 }
1679
1680 if (breakpoint)
1681 arm7_9_set_breakpoint(target, breakpoint);
1682
1683 return err;
1684
1685 }
1686
1687 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1688 {
1689 u32* reg_p[16];
1690 u32 value;
1691 int retval;
1692 armv4_5_common_t *armv4_5 = target->arch_info;
1693 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1694 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1695
1696 if ((num < 0) || (num > 16))
1697 return ERROR_INVALID_ARGUMENTS;
1698
1699 if ((mode != ARMV4_5_MODE_ANY)
1700 && (mode != armv4_5->core_mode)
1701 && (reg_mode != ARMV4_5_MODE_ANY))
1702 {
1703 u32 tmp_cpsr;
1704
1705 /* change processor mode (mask T bit) */
1706 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1707 tmp_cpsr |= mode;
1708 tmp_cpsr &= ~0x20;
1709 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1710 }
1711
1712 if ((num >= 0) && (num <= 15))
1713 {
1714 /* read a normal core register */
1715 reg_p[num] = &value;
1716
1717 arm7_9->read_core_regs(target, 1 << num, reg_p);
1718 }
1719 else
1720 {
1721 /* read a program status register
1722 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1723 */
1724 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1725 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1726
1727 arm7_9->read_xpsr(target, &value, spsr);
1728 }
1729
1730 if ((retval = jtag_execute_queue()) != ERROR_OK)
1731 {
1732 ERROR("JTAG failure");
1733 exit(-1);
1734 }
1735
1736 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1737 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1738 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1739
1740 if ((mode != ARMV4_5_MODE_ANY)
1741 && (mode != armv4_5->core_mode)
1742 && (reg_mode != ARMV4_5_MODE_ANY)) {
1743 /* restore processor mode (mask T bit) */
1744 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1745 }
1746
1747 return ERROR_OK;
1748
1749 }
1750
1751 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1752 {
1753 u32 reg[16];
1754 armv4_5_common_t *armv4_5 = target->arch_info;
1755 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1756 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1757
1758 if ((num < 0) || (num > 16))
1759 return ERROR_INVALID_ARGUMENTS;
1760
1761 if ((mode != ARMV4_5_MODE_ANY)
1762 && (mode != armv4_5->core_mode)
1763 && (reg_mode != ARMV4_5_MODE_ANY)) {
1764 u32 tmp_cpsr;
1765
1766 /* change processor mode (mask T bit) */
1767 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1768 tmp_cpsr |= mode;
1769 tmp_cpsr &= ~0x20;
1770 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1771 }
1772
1773 if ((num >= 0) && (num <= 15))
1774 {
1775 /* write a normal core register */
1776 reg[num] = value;
1777
1778 arm7_9->write_core_regs(target, 1 << num, reg);
1779 }
1780 else
1781 {
1782 /* write a program status register
1783 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1784 */
1785 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1786 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1787
1788 /* if we're writing the CPSR, mask the T bit */
1789 if (!spsr)
1790 value &= ~0x20;
1791
1792 arm7_9->write_xpsr(target, value, spsr);
1793 }
1794
1795 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1796 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1797
1798 if ((mode != ARMV4_5_MODE_ANY)
1799 && (mode != armv4_5->core_mode)
1800 && (reg_mode != ARMV4_5_MODE_ANY)) {
1801 /* restore processor mode (mask T bit) */
1802 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1803 }
1804
1805 return jtag_execute_queue();
1806 }
1807
1808 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1809 {
1810 armv4_5_common_t *armv4_5 = target->arch_info;
1811 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1812
1813 u32 reg[16];
1814 int num_accesses = 0;
1815 int thisrun_accesses;
1816 int i;
1817 u32 cpsr;
1818 int retval;
1819 int last_reg = 0;
1820
1821 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1822
1823 if (target->state != TARGET_HALTED)
1824 {
1825 WARNING("target not halted");
1826 return ERROR_TARGET_NOT_HALTED;
1827 }
1828
1829 /* sanitize arguments */
1830 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1831 return ERROR_INVALID_ARGUMENTS;
1832
1833 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1834 return ERROR_TARGET_UNALIGNED_ACCESS;
1835
1836 /* load the base register with the address of the first word */
1837 reg[0] = address;
1838 arm7_9->write_core_regs(target, 0x1, reg);
1839
1840 switch (size)
1841 {
1842 case 4:
1843 while (num_accesses < count)
1844 {
1845 u32 reg_list;
1846 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1847 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1848
1849 if (last_reg <= thisrun_accesses)
1850 last_reg = thisrun_accesses;
1851
1852 arm7_9->load_word_regs(target, reg_list);
1853
1854 /* fast memory reads are only safe when the target is running
1855 * from a sufficiently high clock (32 kHz is usually too slow)
1856 */
1857 if (arm7_9->fast_memory_access)
1858 arm7_9_execute_fast_sys_speed(target);
1859 else
1860 arm7_9_execute_sys_speed(target);
1861
1862 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1863
1864 /* advance buffer, count number of accesses */
1865 buffer += thisrun_accesses * 4;
1866 num_accesses += thisrun_accesses;
1867 }
1868 break;
1869 case 2:
1870 while (num_accesses < count)
1871 {
1872 u32 reg_list;
1873 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1874 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1875
1876 for (i = 1; i <= thisrun_accesses; i++)
1877 {
1878 if (i > last_reg)
1879 last_reg = i;
1880 arm7_9->load_hword_reg(target, i);
1881 /* fast memory reads are only safe when the target is running
1882 * from a sufficiently high clock (32 kHz is usually too slow)
1883 */
1884 if (arm7_9->fast_memory_access)
1885 arm7_9_execute_fast_sys_speed(target);
1886 else
1887 arm7_9_execute_sys_speed(target);
1888 }
1889
1890 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1891
1892 /* advance buffer, count number of accesses */
1893 buffer += thisrun_accesses * 2;
1894 num_accesses += thisrun_accesses;
1895 }
1896 break;
1897 case 1:
1898 while (num_accesses < count)
1899 {
1900 u32 reg_list;
1901 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1902 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1903
1904 for (i = 1; i <= thisrun_accesses; i++)
1905 {
1906 if (i > last_reg)
1907 last_reg = i;
1908 arm7_9->load_byte_reg(target, i);
1909 /* fast memory reads are only safe when the target is running
1910 * from a sufficiently high clock (32 kHz is usually too slow)
1911 */
1912 if (arm7_9->fast_memory_access)
1913 arm7_9_execute_fast_sys_speed(target);
1914 else
1915 arm7_9_execute_sys_speed(target);
1916 }
1917
1918 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1919
1920 /* advance buffer, count number of accesses */
1921 buffer += thisrun_accesses * 1;
1922 num_accesses += thisrun_accesses;
1923 }
1924 break;
1925 default:
1926 ERROR("BUG: we shouldn't get here");
1927 exit(-1);
1928 break;
1929 }
1930
1931 for (i=0; i<=last_reg; i++)
1932 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
1933
1934 arm7_9->read_xpsr(target, &cpsr, 0);
1935 if ((retval = jtag_execute_queue()) != ERROR_OK)
1936 {
1937 ERROR("JTAG error while reading cpsr");
1938 return ERROR_TARGET_DATA_ABORT;
1939 }
1940
1941 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1942 {
1943 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1944
1945 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1946
1947 return ERROR_TARGET_DATA_ABORT;
1948 }
1949
1950 return ERROR_OK;
1951 }
1952
1953 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1954 {
1955 armv4_5_common_t *armv4_5 = target->arch_info;
1956 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1957 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1958
1959 u32 reg[16];
1960 int num_accesses = 0;
1961 int thisrun_accesses;
1962 int i;
1963 u32 cpsr;
1964 int retval;
1965 int last_reg = 0;
1966
1967 #ifdef _DEBUG_ARM7_9_
1968 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1969 #endif
1970
1971 if (target->state != TARGET_HALTED)
1972 {
1973 WARNING("target not halted");
1974 return ERROR_TARGET_NOT_HALTED;
1975 }
1976
1977 /* sanitize arguments */
1978 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1979 return ERROR_INVALID_ARGUMENTS;
1980
1981 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1982 return ERROR_TARGET_UNALIGNED_ACCESS;
1983
1984 /* load the base register with the address of the first word */
1985 reg[0] = address;
1986 arm7_9->write_core_regs(target, 0x1, reg);
1987
1988 /* Clear DBGACK, to make sure memory fetches work as expected */
1989 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1990 embeddedice_store_reg(dbg_ctrl);
1991
1992 switch (size)
1993 {
1994 case 4:
1995 while (num_accesses < count)
1996 {
1997 u32 reg_list;
1998 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1999 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2000
2001 for (i = 1; i <= thisrun_accesses; i++)
2002 {
2003 if (i > last_reg)
2004 last_reg = i;
2005 reg[i] = target_buffer_get_u32(target, buffer);
2006 buffer += 4;
2007 }
2008
2009 arm7_9->write_core_regs(target, reg_list, reg);
2010
2011 arm7_9->store_word_regs(target, reg_list);
2012
2013 /* fast memory writes are only safe when the target is running
2014 * from a sufficiently high clock (32 kHz is usually too slow)
2015 */
2016 if (arm7_9->fast_memory_access)
2017 arm7_9_execute_fast_sys_speed(target);
2018 else
2019 arm7_9_execute_sys_speed(target);
2020
2021 num_accesses += thisrun_accesses;
2022 }
2023 break;
2024 case 2:
2025 while (num_accesses < count)
2026 {
2027 u32 reg_list;
2028 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2029 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2030
2031 for (i = 1; i <= thisrun_accesses; i++)
2032 {
2033 if (i > last_reg)
2034 last_reg = i;
2035 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2036 buffer += 2;
2037 }
2038
2039 arm7_9->write_core_regs(target, reg_list, reg);
2040
2041 for (i = 1; i <= thisrun_accesses; i++)
2042 {
2043 arm7_9->store_hword_reg(target, i);
2044
2045 /* fast memory writes are only safe when the target is running
2046 * from a sufficiently high clock (32 kHz is usually too slow)
2047 */
2048 if (arm7_9->fast_memory_access)
2049 arm7_9_execute_fast_sys_speed(target);
2050 else
2051 arm7_9_execute_sys_speed(target);
2052 }
2053
2054 num_accesses += thisrun_accesses;
2055 }
2056 break;
2057 case 1:
2058 while (num_accesses < count)
2059 {
2060 u32 reg_list;
2061 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2062 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2063
2064 for (i = 1; i <= thisrun_accesses; i++)
2065 {
2066 if (i > last_reg)
2067 last_reg = i;
2068 reg[i] = *buffer++ & 0xff;
2069 }
2070
2071 arm7_9->write_core_regs(target, reg_list, reg);
2072
2073 for (i = 1; i <= thisrun_accesses; i++)
2074 {
2075 arm7_9->store_byte_reg(target, i);
2076 /* fast memory writes are only safe when the target is running
2077 * from a sufficiently high clock (32 kHz is usually too slow)
2078 */
2079 if (arm7_9->fast_memory_access)
2080 arm7_9_execute_fast_sys_speed(target);
2081 else
2082 arm7_9_execute_sys_speed(target);
2083 }
2084
2085 num_accesses += thisrun_accesses;
2086 }
2087 break;
2088 default:
2089 ERROR("BUG: we shouldn't get here");
2090 exit(-1);
2091 break;
2092 }
2093
2094 /* Re-Set DBGACK */
2095 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2096 embeddedice_store_reg(dbg_ctrl);
2097
2098 for (i=0; i<=last_reg; i++)
2099 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
2100
2101 arm7_9->read_xpsr(target, &cpsr, 0);
2102 if ((retval = jtag_execute_queue()) != ERROR_OK)
2103 {
2104 ERROR("JTAG error while reading cpsr");
2105 return ERROR_TARGET_DATA_ABORT;
2106 }
2107
2108 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2109 {
2110 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2111
2112 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2113
2114 return ERROR_TARGET_DATA_ABORT;
2115 }
2116
2117 return ERROR_OK;
2118 }
2119
2120 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2121 {
2122 armv4_5_common_t *armv4_5 = target->arch_info;
2123 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2124 enum armv4_5_state core_state = armv4_5->core_state;
2125 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2126 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2127 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2128 int i;
2129
2130 u32 dcc_code[] =
2131 {
2132 /* MRC TST BNE MRC STR B */
2133 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2134 };
2135
2136 if (!arm7_9->dcc_downloads)
2137 return target->type->write_memory(target, address, 4, count, buffer);
2138
2139 /* regrab previously allocated working_area, or allocate a new one */
2140 if (!arm7_9->dcc_working_area)
2141 {
2142 u8 dcc_code_buf[6 * 4];
2143
2144 /* make sure we have a working area */
2145 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2146 {
2147 INFO("no working area available, falling back to memory writes");
2148 return target->type->write_memory(target, address, 4, count, buffer);
2149 }
2150
2151 /* copy target instructions to target endianness */
2152 for (i = 0; i < 6; i++)
2153 {
2154 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2155 }
2156
2157 /* write DCC code to working area */
2158 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2159 }
2160
2161 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2162 armv4_5->core_cache->reg_list[0].valid = 1;
2163 armv4_5->core_cache->reg_list[0].dirty = 1;
2164 armv4_5->core_state = ARMV4_5_STATE_ARM;
2165
2166 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2167
2168 int little=target->endianness==TARGET_LITTLE_ENDIAN;
2169 if (count>2)
2170 {
2171 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2172 core function repeated.
2173 */
2174 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2175 buffer+=4;
2176
2177 embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2178 u8 reg_addr = ice_reg->addr & 0x1f;
2179 int chain_pos = ice_reg->jtag_info->chain_pos;
2180 /* we want the compiler to duplicate the code, which it does not
2181 * do automatically.
2182 */
2183 if (little)
2184 {
2185 for (i = 1; i < count - 1; i++)
2186 {
2187 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2188 buffer += 4;
2189 }
2190 } else
2191 {
2192 for (i = 1; i < count - 1; i++)
2193 {
2194 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
2195 buffer += 4;
2196 }
2197 }
2198 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2199 } else
2200 {
2201 for (i = 0; i < count; i++)
2202 {
2203 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2204 buffer += 4;
2205 }
2206 }
2207
2208 target->type->halt(target);
2209
2210 for (i=0; i<100; i++)
2211 {
2212 target->type->poll(target);
2213 if (target->state == TARGET_HALTED)
2214 break;
2215 usleep(1000); /* sleep 1ms */
2216 }
2217 if (i == 100)
2218 {
2219 ERROR("bulk write timed out, target not halted");
2220 return ERROR_TARGET_TIMEOUT;
2221 }
2222
2223 /* restore target state */
2224 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2225 armv4_5->core_cache->reg_list[0].valid = 1;
2226 armv4_5->core_cache->reg_list[0].dirty = 1;
2227 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2228 armv4_5->core_cache->reg_list[1].valid = 1;
2229 armv4_5->core_cache->reg_list[1].dirty = 1;
2230 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2231 armv4_5->core_cache->reg_list[15].valid = 1;
2232 armv4_5->core_cache->reg_list[15].dirty = 1;
2233 armv4_5->core_state = core_state;
2234
2235 return ERROR_OK;
2236 }
2237
2238 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
2239 {
2240 working_area_t *crc_algorithm;
2241 armv4_5_algorithm_t armv4_5_info;
2242 reg_param_t reg_params[2];
2243 int retval;
2244
2245 u32 arm7_9_crc_code[] = {
2246 0xE1A02000, /* mov r2, r0 */
2247 0xE3E00000, /* mov r0, #0xffffffff */
2248 0xE1A03001, /* mov r3, r1 */
2249 0xE3A04000, /* mov r4, #0 */
2250 0xEA00000B, /* b ncomp */
2251 /* nbyte: */
2252 0xE7D21004, /* ldrb r1, [r2, r4] */
2253 0xE59F7030, /* ldr r7, CRC32XOR */
2254 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2255 0xE3A05000, /* mov r5, #0 */
2256 /* loop: */
2257 0xE3500000, /* cmp r0, #0 */
2258 0xE1A06080, /* mov r6, r0, asl #1 */
2259 0xE2855001, /* add r5, r5, #1 */
2260 0xE1A00006, /* mov r0, r6 */
2261 0xB0260007, /* eorlt r0, r6, r7 */
2262 0xE3550008, /* cmp r5, #8 */
2263 0x1AFFFFF8, /* bne loop */
2264 0xE2844001, /* add r4, r4, #1 */
2265 /* ncomp: */
2266 0xE1540003, /* cmp r4, r3 */
2267 0x1AFFFFF1, /* bne nbyte */
2268 /* end: */
2269 0xEAFFFFFE, /* b end */
2270 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2271 };
2272
2273 int i;
2274
2275 if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
2276 {
2277 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2278 }
2279
2280 /* convert flash writing code into a buffer in target endianness */
2281 for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++)
2282 target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]);
2283
2284 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2285 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2286 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2287
2288 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2289 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2290
2291 buf_set_u32(reg_params[0].value, 0, 32, address);
2292 buf_set_u32(reg_params[1].value, 0, 32, count);
2293
2294 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
2295 crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
2296 {
2297 ERROR("error executing arm7_9 crc algorithm");
2298 destroy_reg_param(&reg_params[0]);
2299 destroy_reg_param(&reg_params[1]);
2300 target_free_working_area(target, crc_algorithm);
2301 return retval;
2302 }
2303
2304 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2305
2306 destroy_reg_param(&reg_params[0]);
2307 destroy_reg_param(&reg_params[1]);
2308
2309 target_free_working_area(target, crc_algorithm);
2310
2311 return ERROR_OK;
2312 }
2313
2314 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2315 {
2316 command_t *arm7_9_cmd;
2317
2318 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2319
2320 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2321 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2322
2323 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2324
2325 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2326 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2327 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2328 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2329 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2330 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2331 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2332 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2333 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2334 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2335
2336 armv4_5_register_commands(cmd_ctx);
2337
2338 etm_register_commands(cmd_ctx);
2339
2340 return ERROR_OK;
2341 }
2342
2343 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2344 {
2345 u32 value;
2346 int spsr;
2347 int retval;
2348 target_t *target = get_current_target(cmd_ctx);
2349 armv4_5_common_t *armv4_5;
2350 arm7_9_common_t *arm7_9;
2351
2352 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2353 {
2354 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2355 return ERROR_OK;
2356 }
2357
2358 if (target->state != TARGET_HALTED)
2359 {
2360 command_print(cmd_ctx, "can't write registers while running");
2361 return ERROR_OK;
2362 }
2363
2364 if (argc < 2)
2365 {
2366 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2367 return ERROR_OK;
2368 }
2369
2370 value = strtoul(args[0], NULL, 0);
2371 spsr = strtol(args[1], NULL, 0);
2372
2373 /* if we're writing the CPSR, mask the T bit */
2374 if (!spsr)
2375 value &= ~0x20;
2376
2377 arm7_9->write_xpsr(target, value, spsr);
2378 if ((retval = jtag_execute_queue()) != ERROR_OK)
2379 {
2380 ERROR("JTAG error while writing to xpsr");
2381 return retval;
2382 }
2383
2384 return ERROR_OK;
2385 }
2386
2387 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2388 {
2389 u32 value;
2390 int rotate;
2391 int spsr;
2392 int retval;
2393 target_t *target = get_current_target(cmd_ctx);
2394 armv4_5_common_t *armv4_5;
2395 arm7_9_common_t *arm7_9;
2396
2397 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2398 {
2399 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2400 return ERROR_OK;
2401 }
2402
2403 if (target->state != TARGET_HALTED)
2404 {
2405 command_print(cmd_ctx, "can't write registers while running");
2406 return ERROR_OK;
2407 }
2408
2409 if (argc < 3)
2410 {
2411 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2412 return ERROR_OK;
2413 }
2414
2415 value = strtoul(args[0], NULL, 0);
2416 rotate = strtol(args[1], NULL, 0);
2417 spsr = strtol(args[2], NULL, 0);
2418
2419 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2420 if ((retval = jtag_execute_queue()) != ERROR_OK)
2421 {
2422 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2423 return retval;
2424 }
2425
2426 return ERROR_OK;
2427 }
2428
2429 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2430 {
2431 u32 value;
2432 u32 mode;
2433 int num;
2434 target_t *target = get_current_target(cmd_ctx);
2435 armv4_5_common_t *armv4_5;
2436 arm7_9_common_t *arm7_9;
2437
2438 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2439 {
2440 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2441 return ERROR_OK;
2442 }
2443
2444 if (target->state != TARGET_HALTED)
2445 {
2446 command_print(cmd_ctx, "can't write registers while running");
2447 return ERROR_OK;
2448 }
2449
2450 if (argc < 3)
2451 {
2452 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2453 return ERROR_OK;
2454 }
2455
2456 num = strtol(args[0], NULL, 0);
2457 mode = strtoul(args[1], NULL, 0);
2458 value = strtoul(args[2], NULL, 0);
2459
2460 arm7_9_write_core_reg(target, num, mode, value);
2461
2462 return ERROR_OK;
2463 }
2464
2465 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2466 {
2467 target_t *target = get_current_target(cmd_ctx);
2468 armv4_5_common_t *armv4_5;
2469 arm7_9_common_t *arm7_9;
2470
2471 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2472 {
2473 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2474 return ERROR_OK;
2475 }
2476
2477 if (argc == 0)
2478 {
2479 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2480 return ERROR_OK;
2481 }
2482
2483 if (strcmp("enable", args[0]) == 0)
2484 {
2485 if (arm7_9->sw_bkpts_use_wp)
2486 {
2487 arm7_9_enable_sw_bkpts(target);
2488 }
2489 else
2490 {
2491 arm7_9->sw_bkpts_enabled = 1;
2492 }
2493 }
2494 else if (strcmp("disable", args[0]) == 0)
2495 {
2496 if (arm7_9->sw_bkpts_use_wp)
2497 {
2498 arm7_9_disable_sw_bkpts(target);
2499 }
2500 else
2501 {
2502 arm7_9->sw_bkpts_enabled = 0;
2503 }
2504 }
2505 else
2506 {
2507 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2508 }
2509
2510 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2511
2512 return ERROR_OK;
2513 }
2514
2515 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2516 {
2517 target_t *target = get_current_target(cmd_ctx);
2518 armv4_5_common_t *armv4_5;
2519 arm7_9_common_t *arm7_9;
2520
2521 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2522 {
2523 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2524 return ERROR_OK;
2525 }
2526
2527 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2528 {
2529 arm7_9->force_hw_bkpts = 1;
2530 if (arm7_9->sw_bkpts_use_wp)
2531 {
2532 arm7_9_disable_sw_bkpts(target);
2533 }
2534 }
2535 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2536 {
2537 arm7_9->force_hw_bkpts = 0;
2538 }
2539 else
2540 {
2541 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2542 }
2543
2544 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2545
2546 return ERROR_OK;
2547 }
2548
2549 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2550 {
2551 target_t *target = get_current_target(cmd_ctx);
2552 armv4_5_common_t *armv4_5;
2553 arm7_9_common_t *arm7_9;
2554
2555 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2556 {
2557 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2558 return ERROR_OK;
2559 }
2560
2561 if (argc > 0)
2562 {
2563 if (strcmp("enable", args[0]) == 0)
2564 {
2565 arm7_9->use_dbgrq = 1;
2566 }
2567 else if (strcmp("disable", args[0]) == 0)
2568 {
2569 arm7_9->use_dbgrq = 0;
2570 }
2571 else
2572 {
2573 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2574 }
2575 }
2576
2577 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2578
2579 return ERROR_OK;
2580 }
2581
2582 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2583 {
2584 target_t *target = get_current_target(cmd_ctx);
2585 armv4_5_common_t *armv4_5;
2586 arm7_9_common_t *arm7_9;
2587
2588 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2589 {
2590 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2591 return ERROR_OK;
2592 }
2593
2594 if (argc > 0)
2595 {
2596 if (strcmp("enable", args[0]) == 0)
2597 {
2598 arm7_9->fast_memory_access = 1;
2599 }
2600 else if (strcmp("disable", args[0]) == 0)
2601 {
2602 arm7_9->fast_memory_access = 0;
2603 }
2604 else
2605 {
2606 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2607 }
2608 }
2609
2610 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2611
2612 return ERROR_OK;
2613 }
2614
2615 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2616 {
2617 target_t *target = get_current_target(cmd_ctx);
2618 armv4_5_common_t *armv4_5;
2619 arm7_9_common_t *arm7_9;
2620
2621 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2622 {
2623 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2624 return ERROR_OK;
2625 }
2626
2627 if (argc > 0)
2628 {
2629 if (strcmp("enable", args[0]) == 0)
2630 {
2631 arm7_9->dcc_downloads = 1;
2632 }
2633 else if (strcmp("disable", args[0]) == 0)
2634 {
2635 arm7_9->dcc_downloads = 0;
2636 }
2637 else
2638 {
2639 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2640 }
2641 }
2642
2643 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2644
2645 return ERROR_OK;
2646 }
2647
2648 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2649 {
2650 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2651
2652 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2653
2654 arm_jtag_setup_connection(&arm7_9->jtag_info);
2655 arm7_9->wp_available = 2;
2656 arm7_9->wp0_used = 0;
2657 arm7_9->wp1_used = 0;
2658 arm7_9->force_hw_bkpts = 0;
2659 arm7_9->use_dbgrq = 0;
2660
2661 arm7_9->etm_ctx = NULL;
2662 arm7_9->has_single_step = 0;
2663 arm7_9->has_monitor_mode = 0;
2664 arm7_9->has_vector_catch = 0;
2665
2666 arm7_9->reinit_embeddedice = 0;
2667
2668 arm7_9->debug_entry_from_reset = 0;
2669
2670 arm7_9->dcc_working_area = NULL;
2671
2672 arm7_9->fast_memory_access = 0;
2673 arm7_9->dcc_downloads = 0;
2674
2675 jtag_register_event_callback(arm7_9_jtag_callback, target);
2676
2677 armv4_5->arch_info = arm7_9;
2678 armv4_5->read_core_reg = arm7_9_read_core_reg;
2679 armv4_5->write_core_reg = arm7_9_write_core_reg;
2680 armv4_5->full_context = arm7_9_full_context;
2681
2682 armv4_5_init_arch_info(target, armv4_5);
2683
2684 target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
2685
2686 return ERROR_OK;
2687 }
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