arm7_9_common: use register_commands()
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 √ėyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2008 by Hongtao Zheng *
12 * hontor@126.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29 #ifdef HAVE_CONFIG_H
30 #include "config.h"
31 #endif
32
33 #include "breakpoints.h"
34 #include "embeddedice.h"
35 #include "target_request.h"
36 #include "etm.h"
37 #include "time_support.h"
38 #include "arm_simulator.h"
39 #include "algorithm.h"
40 #include "register.h"
41
42
43 /**
44 * @file
45 * Hold common code supporting the ARM7 and ARM9 core generations.
46 *
47 * While the ARM core implementations evolved substantially during these
48 * two generations, they look quite similar from the JTAG perspective.
49 * Both have similar debug facilities, based on the same two scan chains
50 * providing access to the core and to an EmbeddedICE module. Both can
51 * support similar ETM and ETB modules, for tracing. And both expose
52 * what could be viewed as "ARM Classic", with multiple processor modes,
53 * shadowed registers, and support for the Thumb instruction set.
54 *
55 * Processor differences include things like presence or absence of MMU
56 * and cache, pipeline sizes, use of a modified Harvard Architecure
57 * (with separate instruction and data busses from the CPU), support
58 * for cpu clock gating during idle, and more.
59 */
60
61 static int arm7_9_debug_entry(struct target *target);
62
63 /**
64 * Clear watchpoints for an ARM7/9 target.
65 *
66 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
67 * @return JTAG error status after executing queue
68 */
69 static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
70 {
71 LOG_DEBUG("-");
72 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
73 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
74 arm7_9->sw_breakpoint_count = 0;
75 arm7_9->sw_breakpoints_added = 0;
76 arm7_9->wp0_used = 0;
77 arm7_9->wp1_used = arm7_9->wp1_used_default;
78 arm7_9->wp_available = arm7_9->wp_available_max;
79
80 return jtag_execute_queue();
81 }
82
83 /**
84 * Assign a watchpoint to one of the two available hardware comparators in an
85 * ARM7 or ARM9 target.
86 *
87 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
88 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
89 */
90 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
91 {
92 if (!arm7_9->wp0_used)
93 {
94 arm7_9->wp0_used = 1;
95 breakpoint->set = 1;
96 arm7_9->wp_available--;
97 }
98 else if (!arm7_9->wp1_used)
99 {
100 arm7_9->wp1_used = 1;
101 breakpoint->set = 2;
102 arm7_9->wp_available--;
103 }
104 else
105 {
106 LOG_ERROR("BUG: no hardware comparator available");
107 }
108 LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
109 breakpoint->unique_id,
110 breakpoint->address,
111 breakpoint->set );
112 }
113
114 /**
115 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
116 *
117 * @param arm7_9 Pointer to common struct for ARM7/9 targets
118 * @return Error codes if there is a problem finding a watchpoint or the result
119 * of executing the JTAG queue
120 */
121 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
122 {
123 if (arm7_9->sw_breakpoints_added)
124 {
125 return ERROR_OK;
126 }
127 if (arm7_9->wp_available < 1)
128 {
129 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
130 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
131 }
132 arm7_9->wp_available--;
133
134 /* pick a breakpoint unit */
135 if (!arm7_9->wp0_used)
136 {
137 arm7_9->sw_breakpoints_added = 1;
138 arm7_9->wp0_used = 3;
139 } else if (!arm7_9->wp1_used)
140 {
141 arm7_9->sw_breakpoints_added = 2;
142 arm7_9->wp1_used = 3;
143 }
144 else
145 {
146 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
147 return ERROR_FAIL;
148 }
149
150 if (arm7_9->sw_breakpoints_added == 1)
151 {
152 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
153 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
154 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
155 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
157 }
158 else if (arm7_9->sw_breakpoints_added == 2)
159 {
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
162 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
163 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
164 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
165 }
166 else
167 {
168 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
169 return ERROR_FAIL;
170 }
171 LOG_DEBUG("SW BP using hw wp: %d",
172 arm7_9->sw_breakpoints_added );
173
174 return jtag_execute_queue();
175 }
176
177 /**
178 * Setup the common pieces for an ARM7/9 target after reset or on startup.
179 *
180 * @param target Pointer to an ARM7/9 target to setup
181 * @return Result of clearing the watchpoints on the target
182 */
183 int arm7_9_setup(struct target *target)
184 {
185 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
186
187 return arm7_9_clear_watchpoints(arm7_9);
188 }
189
190 /**
191 * Set either a hardware or software breakpoint on an ARM7/9 target. The
192 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
193 * might have erased the values in Embedded ICE.
194 *
195 * @param target Pointer to the target device to set the breakpoints on
196 * @param breakpoint Pointer to the breakpoint to be set
197 * @return For hardware breakpoints, this is the result of executing the JTAG
198 * queue. For software breakpoints, this will be the status of the
199 * required memory reads and writes
200 */
201 int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
202 {
203 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
204 int retval = ERROR_OK;
205
206 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
207 breakpoint->unique_id,
208 breakpoint->address,
209 breakpoint->type);
210
211 if (target->state != TARGET_HALTED)
212 {
213 LOG_WARNING("target not halted");
214 return ERROR_TARGET_NOT_HALTED;
215 }
216
217 if (breakpoint->type == BKPT_HARD)
218 {
219 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
220 uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
221
222 /* reassign a hw breakpoint */
223 if (breakpoint->set == 0)
224 {
225 arm7_9_assign_wp(arm7_9, breakpoint);
226 }
227
228 if (breakpoint->set == 1)
229 {
230 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
231 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
232 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
233 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
234 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
235 }
236 else if (breakpoint->set == 2)
237 {
238 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
239 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
240 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
241 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
242 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
243 }
244 else
245 {
246 LOG_ERROR("BUG: no hardware comparator available");
247 return ERROR_OK;
248 }
249
250 retval = jtag_execute_queue();
251 }
252 else if (breakpoint->type == BKPT_SOFT)
253 {
254 /* did we already set this breakpoint? */
255 if (breakpoint->set)
256 return ERROR_OK;
257
258 if (breakpoint->length == 4)
259 {
260 uint32_t verify = 0xffffffff;
261 /* keep the original instruction in target endianness */
262 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
263 {
264 return retval;
265 }
266 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
267 if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
268 {
269 return retval;
270 }
271
272 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
273 {
274 return retval;
275 }
276 if (verify != arm7_9->arm_bkpt)
277 {
278 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
279 return ERROR_OK;
280 }
281 }
282 else
283 {
284 uint16_t verify = 0xffff;
285 /* keep the original instruction in target endianness */
286 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
287 {
288 return retval;
289 }
290 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
291 if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
292 {
293 return retval;
294 }
295
296 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
297 {
298 return retval;
299 }
300 if (verify != arm7_9->thumb_bkpt)
301 {
302 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
303 return ERROR_OK;
304 }
305 }
306
307 if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
308 return retval;
309
310 arm7_9->sw_breakpoint_count++;
311
312 breakpoint->set = 1;
313 }
314
315 return retval;
316 }
317
318 /**
319 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
320 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
321 * will be updated. Otherwise, the software breakpoint will be restored to its
322 * original instruction if it hasn't already been modified.
323 *
324 * @param target Pointer to ARM7/9 target to unset the breakpoint from
325 * @param breakpoint Pointer to breakpoint to be unset
326 * @return For hardware breakpoints, this is the result of executing the JTAG
327 * queue. For software breakpoints, this will be the status of the
328 * required memory reads and writes
329 */
330 int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
331 {
332 int retval = ERROR_OK;
333 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
334
335 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
336 breakpoint->unique_id,
337 breakpoint->address );
338
339 if (!breakpoint->set)
340 {
341 LOG_WARNING("breakpoint not set");
342 return ERROR_OK;
343 }
344
345 if (breakpoint->type == BKPT_HARD)
346 {
347 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
348 breakpoint->unique_id,
349 breakpoint->set );
350 if (breakpoint->set == 1)
351 {
352 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
353 arm7_9->wp0_used = 0;
354 arm7_9->wp_available++;
355 }
356 else if (breakpoint->set == 2)
357 {
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
359 arm7_9->wp1_used = 0;
360 arm7_9->wp_available++;
361 }
362 retval = jtag_execute_queue();
363 breakpoint->set = 0;
364 }
365 else
366 {
367 /* restore original instruction (kept in target endianness) */
368 if (breakpoint->length == 4)
369 {
370 uint32_t current_instr;
371 /* check that user program as not modified breakpoint instruction */
372 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
373 {
374 return retval;
375 }
376 if (current_instr == arm7_9->arm_bkpt)
377 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
378 {
379 return retval;
380 }
381 }
382 else
383 {
384 uint16_t current_instr;
385 /* check that user program as not modified breakpoint instruction */
386 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
387 {
388 return retval;
389 }
390 if (current_instr == arm7_9->thumb_bkpt)
391 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
392 {
393 return retval;
394 }
395 }
396
397 if (--arm7_9->sw_breakpoint_count==0)
398 {
399 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
400 if (arm7_9->sw_breakpoints_added == 1)
401 {
402 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
403 }
404 else if (arm7_9->sw_breakpoints_added == 2)
405 {
406 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
407 }
408 }
409
410 breakpoint->set = 0;
411 }
412
413 return retval;
414 }
415
416 /**
417 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
418 * dangling breakpoints and that the desired breakpoint can be added.
419 *
420 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
421 * @param breakpoint Pointer to the breakpoint to be added
422 * @return An error status if there is a problem adding the breakpoint or the
423 * result of setting the breakpoint
424 */
425 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
426 {
427 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
428
429 if (target->state != TARGET_HALTED)
430 {
431 LOG_WARNING("target not halted");
432 return ERROR_TARGET_NOT_HALTED;
433 }
434
435 if (arm7_9->breakpoint_count == 0)
436 {
437 /* make sure we don't have any dangling breakpoints. This is vital upon
438 * GDB connect/disconnect
439 */
440 arm7_9_clear_watchpoints(arm7_9);
441 }
442
443 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
444 {
445 LOG_INFO("no watchpoint unit available for hardware breakpoint");
446 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
447 }
448
449 if ((breakpoint->length != 2) && (breakpoint->length != 4))
450 {
451 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
452 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
453 }
454
455 if (breakpoint->type == BKPT_HARD)
456 {
457 arm7_9_assign_wp(arm7_9, breakpoint);
458 }
459
460 arm7_9->breakpoint_count++;
461
462 return arm7_9_set_breakpoint(target, breakpoint);
463 }
464
465 /**
466 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
467 * dangling breakpoints and updates available watchpoints if it is a hardware
468 * breakpoint.
469 *
470 * @param target Pointer to the target to have a breakpoint removed
471 * @param breakpoint Pointer to the breakpoint to be removed
472 * @return Error status if there was a problem unsetting the breakpoint or the
473 * watchpoints could not be cleared
474 */
475 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
476 {
477 int retval = ERROR_OK;
478 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
479
480 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
481 {
482 return retval;
483 }
484
485 if (breakpoint->type == BKPT_HARD)
486 arm7_9->wp_available++;
487
488 arm7_9->breakpoint_count--;
489 if (arm7_9->breakpoint_count == 0)
490 {
491 /* make sure we don't have any dangling breakpoints */
492 if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
493 {
494 return retval;
495 }
496 }
497
498 return ERROR_OK;
499 }
500
501 /**
502 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
503 * considered a bug to call this function when there are no available watchpoint
504 * units.
505 *
506 * @param target Pointer to an ARM7/9 target to set a watchpoint on
507 * @param watchpoint Pointer to the watchpoint to be set
508 * @return Error status if watchpoint set fails or the result of executing the
509 * JTAG queue
510 */
511 int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
512 {
513 int retval = ERROR_OK;
514 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
515 int rw_mask = 1;
516 uint32_t mask;
517
518 mask = watchpoint->length - 1;
519
520 if (target->state != TARGET_HALTED)
521 {
522 LOG_WARNING("target not halted");
523 return ERROR_TARGET_NOT_HALTED;
524 }
525
526 if (watchpoint->rw == WPT_ACCESS)
527 rw_mask = 0;
528 else
529 rw_mask = 1;
530
531 if (!arm7_9->wp0_used)
532 {
533 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
534 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
535 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
536 if (watchpoint->mask != 0xffffffffu)
537 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
538 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
539 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
540
541 if ((retval = jtag_execute_queue()) != ERROR_OK)
542 {
543 return retval;
544 }
545 watchpoint->set = 1;
546 arm7_9->wp0_used = 2;
547 }
548 else if (!arm7_9->wp1_used)
549 {
550 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
551 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
552 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
553 if (watchpoint->mask != 0xffffffffu)
554 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
555 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
556 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
557
558 if ((retval = jtag_execute_queue()) != ERROR_OK)
559 {
560 return retval;
561 }
562 watchpoint->set = 2;
563 arm7_9->wp1_used = 2;
564 }
565 else
566 {
567 LOG_ERROR("BUG: no hardware comparator available");
568 return ERROR_OK;
569 }
570
571 return ERROR_OK;
572 }
573
574 /**
575 * Unset an existing watchpoint and clear the used watchpoint unit.
576 *
577 * @param target Pointer to the target to have the watchpoint removed
578 * @param watchpoint Pointer to the watchpoint to be removed
579 * @return Error status while trying to unset the watchpoint or the result of
580 * executing the JTAG queue
581 */
582 int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
583 {
584 int retval = ERROR_OK;
585 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
586
587 if (target->state != TARGET_HALTED)
588 {
589 LOG_WARNING("target not halted");
590 return ERROR_TARGET_NOT_HALTED;
591 }
592
593 if (!watchpoint->set)
594 {
595 LOG_WARNING("breakpoint not set");
596 return ERROR_OK;
597 }
598
599 if (watchpoint->set == 1)
600 {
601 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
602 if ((retval = jtag_execute_queue()) != ERROR_OK)
603 {
604 return retval;
605 }
606 arm7_9->wp0_used = 0;
607 }
608 else if (watchpoint->set == 2)
609 {
610 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
611 if ((retval = jtag_execute_queue()) != ERROR_OK)
612 {
613 return retval;
614 }
615 arm7_9->wp1_used = 0;
616 }
617 watchpoint->set = 0;
618
619 return ERROR_OK;
620 }
621
622 /**
623 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
624 * available, an error response is returned.
625 *
626 * @param target Pointer to the ARM7/9 target to add a watchpoint to
627 * @param watchpoint Pointer to the watchpoint to be added
628 * @return Error status while trying to add the watchpoint
629 */
630 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
631 {
632 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
633
634 if (target->state != TARGET_HALTED)
635 {
636 LOG_WARNING("target not halted");
637 return ERROR_TARGET_NOT_HALTED;
638 }
639
640 if (arm7_9->wp_available < 1)
641 {
642 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
643 }
644
645 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
646 {
647 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
648 }
649
650 arm7_9->wp_available--;
651
652 return ERROR_OK;
653 }
654
655 /**
656 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
657 * the used watchpoint unit will be reopened.
658 *
659 * @param target Pointer to the target to remove a watchpoint from
660 * @param watchpoint Pointer to the watchpoint to be removed
661 * @return Result of trying to unset the watchpoint
662 */
663 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
664 {
665 int retval = ERROR_OK;
666 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
667
668 if (watchpoint->set)
669 {
670 if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
671 {
672 return retval;
673 }
674 }
675
676 arm7_9->wp_available++;
677
678 return ERROR_OK;
679 }
680
681 /**
682 * Restarts the target by sending a RESTART instruction and moving the JTAG
683 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
684 * asserted by the processor.
685 *
686 * @param target Pointer to target to issue commands to
687 * @return Error status if there is a timeout or a problem while executing the
688 * JTAG queue
689 */
690 int arm7_9_execute_sys_speed(struct target *target)
691 {
692 int retval;
693 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
694 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
695 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
696
697 /* set RESTART instruction */
698 jtag_set_end_state(TAP_IDLE);
699 if (arm7_9->need_bypass_before_restart) {
700 arm7_9->need_bypass_before_restart = 0;
701 arm_jtag_set_instr(jtag_info, 0xf, NULL);
702 }
703 arm_jtag_set_instr(jtag_info, 0x4, NULL);
704
705 long long then = timeval_ms();
706 int timeout;
707 while (!(timeout = ((timeval_ms()-then) > 1000)))
708 {
709 /* read debug status register */
710 embeddedice_read_reg(dbg_stat);
711 if ((retval = jtag_execute_queue()) != ERROR_OK)
712 return retval;
713 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
714 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
715 break;
716 if (debug_level >= 3)
717 {
718 alive_sleep(100);
719 } else
720 {
721 keep_alive();
722 }
723 }
724 if (timeout)
725 {
726 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
727 return ERROR_TARGET_TIMEOUT;
728 }
729
730 return ERROR_OK;
731 }
732
733 /**
734 * Restarts the target by sending a RESTART instruction and moving the JTAG
735 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
736 * waiting until they are.
737 *
738 * @param target Pointer to the target to issue commands to
739 * @return Always ERROR_OK
740 */
741 int arm7_9_execute_fast_sys_speed(struct target *target)
742 {
743 static int set = 0;
744 static uint8_t check_value[4], check_mask[4];
745
746 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
747 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
748 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
749
750 /* set RESTART instruction */
751 jtag_set_end_state(TAP_IDLE);
752 if (arm7_9->need_bypass_before_restart) {
753 arm7_9->need_bypass_before_restart = 0;
754 arm_jtag_set_instr(jtag_info, 0xf, NULL);
755 }
756 arm_jtag_set_instr(jtag_info, 0x4, NULL);
757
758 if (!set)
759 {
760 /* check for DBGACK and SYSCOMP set (others don't care) */
761
762 /* NB! These are constants that must be available until after next jtag_execute() and
763 * we evaluate the values upon first execution in lieu of setting up these constants
764 * during early setup.
765 * */
766 buf_set_u32(check_value, 0, 32, 0x9);
767 buf_set_u32(check_mask, 0, 32, 0x9);
768 set = 1;
769 }
770
771 /* read debug status register */
772 embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
773
774 return ERROR_OK;
775 }
776
777 /**
778 * Get some data from the ARM7/9 target.
779 *
780 * @param target Pointer to the ARM7/9 target to read data from
781 * @param size The number of 32bit words to be read
782 * @param buffer Pointer to the buffer that will hold the data
783 * @return The result of receiving data from the Embedded ICE unit
784 */
785 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
786 {
787 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
788 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
789 uint32_t *data;
790 int retval = ERROR_OK;
791 uint32_t i;
792
793 data = malloc(size * (sizeof(uint32_t)));
794
795 retval = embeddedice_receive(jtag_info, data, size);
796
797 /* return the 32-bit ints in the 8-bit array */
798 for (i = 0; i < size; i++)
799 {
800 h_u32_to_le(buffer + (i * 4), data[i]);
801 }
802
803 free(data);
804
805 return retval;
806 }
807
808 /**
809 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
810 * target is running and the DCC control register has the W bit high, this will
811 * execute the request on the target.
812 *
813 * @param priv Void pointer expected to be a struct target pointer
814 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
815 * from the Embedded ICE unit
816 */
817 int arm7_9_handle_target_request(void *priv)
818 {
819 int retval = ERROR_OK;
820 struct target *target = priv;
821 if (!target_was_examined(target))
822 return ERROR_OK;
823 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
824 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
825 struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
826
827 if (!target->dbg_msg_enabled)
828 return ERROR_OK;
829
830 if (target->state == TARGET_RUNNING)
831 {
832 /* read DCC control register */
833 embeddedice_read_reg(dcc_control);
834 if ((retval = jtag_execute_queue()) != ERROR_OK)
835 {
836 return retval;
837 }
838
839 /* check W bit */
840 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
841 {
842 uint32_t request;
843
844 if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
845 {
846 return retval;
847 }
848 if ((retval = target_request(target, request)) != ERROR_OK)
849 {
850 return retval;
851 }
852 }
853 }
854
855 return ERROR_OK;
856 }
857
858 /**
859 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
860 * is manipulated to the right halted state based on its current state. This is
861 * what happens:
862 *
863 * <table>
864 * <tr><th > State</th><th > Action</th></tr>
865 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
866 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
867 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
868 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
869 * </table>
870 *
871 * If the target does not end up in the halted state, a warning is produced. If
872 * DBGACK is cleared, then the target is expected to either be running or
873 * running in debug.
874 *
875 * @param target Pointer to the ARM7/9 target to poll
876 * @return ERROR_OK or an error status if a command fails
877 */
878 int arm7_9_poll(struct target *target)
879 {
880 int retval;
881 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
882 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
883
884 /* read debug status register */
885 embeddedice_read_reg(dbg_stat);
886 if ((retval = jtag_execute_queue()) != ERROR_OK)
887 {
888 return retval;
889 }
890
891 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
892 {
893 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
894 if (target->state == TARGET_UNKNOWN)
895 {
896 /* Starting OpenOCD with target in debug-halt */
897 target->state = TARGET_RUNNING;
898 LOG_DEBUG("DBGACK already set during server startup.");
899 }
900 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
901 {
902 int check_pc = 0;
903 if (target->state == TARGET_RESET)
904 {
905 if (target->reset_halt)
906 {
907 enum reset_types jtag_reset_config = jtag_get_reset_config();
908 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
909 {
910 check_pc = 1;
911 }
912 }
913 }
914
915 target->state = TARGET_HALTED;
916
917 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
918 return retval;
919
920 if (check_pc)
921 {
922 struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
923 uint32_t t=*((uint32_t *)reg->value);
924 if (t != 0)
925 {
926 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
927 }
928 }
929
930 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
931 {
932 return retval;
933 }
934 }
935 if (target->state == TARGET_DEBUG_RUNNING)
936 {
937 target->state = TARGET_HALTED;
938 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
939 return retval;
940
941 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
942 {
943 return retval;
944 }
945 }
946 if (target->state != TARGET_HALTED)
947 {
948 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
949 }
950 }
951 else
952 {
953 if (target->state != TARGET_DEBUG_RUNNING)
954 target->state = TARGET_RUNNING;
955 }
956
957 return ERROR_OK;
958 }
959
960 /**
961 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
962 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
963 * affected) completely stop the JTAG clock while the core is held in reset
964 * (SRST). It isn't possible to program the halt condition once reset is
965 * asserted, hence a hook that allows the target to set up its reset-halt
966 * condition is setup prior to asserting reset.
967 *
968 * @param target Pointer to an ARM7/9 target to assert reset on
969 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
970 */
971 int arm7_9_assert_reset(struct target *target)
972 {
973 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
974
975 LOG_DEBUG("target->state: %s",
976 target_state_name(target));
977
978 enum reset_types jtag_reset_config = jtag_get_reset_config();
979 if (!(jtag_reset_config & RESET_HAS_SRST))
980 {
981 LOG_ERROR("Can't assert SRST");
982 return ERROR_FAIL;
983 }
984
985 /* At this point trst has been asserted/deasserted once. We would
986 * like to program EmbeddedICE while SRST is asserted, instead of
987 * depending on SRST to leave that module alone. However, many CPUs
988 * gate the JTAG clock while SRST is asserted; or JTAG may need
989 * clock stability guarantees (adaptive clocking might help).
990 *
991 * So we assume JTAG access during SRST is off the menu unless it's
992 * been specifically enabled.
993 */
994 bool srst_asserted = false;
995
996 if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
997 && (jtag_reset_config & RESET_SRST_NO_GATING))
998 {
999 jtag_add_reset(0, 1);
1000 srst_asserted = true;
1001 }
1002
1003 if (target->reset_halt)
1004 {
1005 /*
1006 * Some targets do not support communication while SRST is asserted. We need to
1007 * set up the reset vector catch here.
1008 *
1009 * If TRST is asserted, then these settings will be reset anyway, so setting them
1010 * here is harmless.
1011 */
1012 if (arm7_9->has_vector_catch)
1013 {
1014 /* program vector catch register to catch reset vector */
1015 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
1016
1017 /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
1018 jtag_add_runtest(1, jtag_get_end_state());
1019 }
1020 else
1021 {
1022 /* program watchpoint unit to match on reset vector address */
1023 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
1024 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
1025 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1026 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1027 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1028 }
1029 }
1030
1031 /* here we should issue an SRST only, but we may have to assert TRST as well */
1032 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1033 {
1034 jtag_add_reset(1, 1);
1035 } else if (!srst_asserted)
1036 {
1037 jtag_add_reset(0, 1);
1038 }
1039
1040 target->state = TARGET_RESET;
1041 jtag_add_sleep(50000);
1042
1043 register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
1044
1045 if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
1046 {
1047 /* debug entry was already prepared in arm7_9_assert_reset() */
1048 target->debug_reason = DBG_REASON_DBGRQ;
1049 }
1050
1051 return ERROR_OK;
1052 }
1053
1054 /**
1055 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1056 * and the target is being reset into a halt, a warning will be triggered
1057 * because it is not possible to reset into a halted mode in this case. The
1058 * target is halted using the target's functions.
1059 *
1060 * @param target Pointer to the target to have the reset deasserted
1061 * @return ERROR_OK or an error from polling or halting the target
1062 */
1063 int arm7_9_deassert_reset(struct target *target)
1064 {
1065 int retval = ERROR_OK;
1066 LOG_DEBUG("target->state: %s",
1067 target_state_name(target));
1068
1069 /* deassert reset lines */
1070 jtag_add_reset(0, 0);
1071
1072 enum reset_types jtag_reset_config = jtag_get_reset_config();
1073 if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
1074 {
1075 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1076 /* set up embedded ice registers again */
1077 if ((retval = target_examine_one(target)) != ERROR_OK)
1078 return retval;
1079
1080 if ((retval = target_poll(target)) != ERROR_OK)
1081 {
1082 return retval;
1083 }
1084
1085 if ((retval = target_halt(target)) != ERROR_OK)
1086 {
1087 return retval;
1088 }
1089
1090 }
1091 return retval;
1092 }
1093
1094 /**
1095 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1096 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1097 * vector catch was used, it is restored. Otherwise, the control value is
1098 * restored and the watchpoint unit is restored if it was in use.
1099 *
1100 * @param target Pointer to the ARM7/9 target to have halt cleared
1101 * @return Always ERROR_OK
1102 */
1103 int arm7_9_clear_halt(struct target *target)
1104 {
1105 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1106 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1107
1108 /* we used DBGRQ only if we didn't come out of reset */
1109 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
1110 {
1111 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1112 */
1113 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1114 embeddedice_store_reg(dbg_ctrl);
1115 }
1116 else
1117 {
1118 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
1119 {
1120 /* if we came out of reset, and vector catch is supported, we used
1121 * vector catch to enter debug state
1122 * restore the register in that case
1123 */
1124 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
1125 }
1126 else
1127 {
1128 /* restore registers if watchpoint unit 0 was in use
1129 */
1130 if (arm7_9->wp0_used)
1131 {
1132 if (arm7_9->debug_entry_from_reset)
1133 {
1134 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
1135 }
1136 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1137 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1138 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1139 }
1140 /* control value always has to be restored, as it was either disabled,
1141 * or enabled with possibly different bits
1142 */
1143 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1144 }
1145 }
1146
1147 return ERROR_OK;
1148 }
1149
1150 /**
1151 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1152 * and then there is a wait until the processor shows the halt. This wait can
1153 * timeout and results in an error being returned. The software reset involves
1154 * clearing the halt, updating the debug control register, changing to ARM mode,
1155 * reset of the program counter, and reset of all of the registers.
1156 *
1157 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1158 * @return Error status if any of the commands fail, otherwise ERROR_OK
1159 */
1160 int arm7_9_soft_reset_halt(struct target *target)
1161 {
1162 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1163 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1164 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1165 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1166 int i;
1167 int retval;
1168
1169 /* FIX!!! replace some of this code with tcl commands
1170 *
1171 * halt # the halt command is synchronous
1172 * armv4_5 core_state arm
1173 *
1174 */
1175
1176 if ((retval = target_halt(target)) != ERROR_OK)
1177 return retval;
1178
1179 long long then = timeval_ms();
1180 int timeout;
1181 while (!(timeout = ((timeval_ms()-then) > 1000)))
1182 {
1183 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
1184 break;
1185 embeddedice_read_reg(dbg_stat);
1186 if ((retval = jtag_execute_queue()) != ERROR_OK)
1187 return retval;
1188 if (debug_level >= 3)
1189 {
1190 alive_sleep(100);
1191 } else
1192 {
1193 keep_alive();
1194 }
1195 }
1196 if (timeout)
1197 {
1198 LOG_ERROR("Failed to halt CPU after 1 sec");
1199 return ERROR_TARGET_TIMEOUT;
1200 }
1201 target->state = TARGET_HALTED;
1202
1203 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1204 * ensure that DBGRQ is cleared
1205 */
1206 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1207 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1208 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1209 embeddedice_store_reg(dbg_ctrl);
1210
1211 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1212 {
1213 return retval;
1214 }
1215
1216 /* if the target is in Thumb state, change to ARM state */
1217 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1218 {
1219 uint32_t r0_thumb, pc_thumb;
1220 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1221 /* Entered debug from Thumb mode */
1222 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1223 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1224 }
1225
1226 /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */
1227
1228 /* all register content is now invalid */
1229 register_cache_invalidate(armv4_5->core_cache);
1230
1231 /* SVC, ARM state, IRQ and FIQ disabled */
1232 uint32_t cpsr;
1233
1234 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
1235 cpsr &= ~0xff;
1236 cpsr |= 0xd3;
1237 arm_set_cpsr(armv4_5, cpsr);
1238 armv4_5->cpsr->dirty = 1;
1239
1240 /* start fetching from 0x0 */
1241 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
1242 armv4_5->core_cache->reg_list[15].dirty = 1;
1243 armv4_5->core_cache->reg_list[15].valid = 1;
1244
1245 /* reset registers */
1246 for (i = 0; i <= 14; i++)
1247 {
1248 struct reg *r = arm_reg_current(armv4_5, i);
1249
1250 buf_set_u32(r->value, 0, 32, 0xffffffff);
1251 r->dirty = 1;
1252 r->valid = 1;
1253 }
1254
1255 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1256 {
1257 return retval;
1258 }
1259
1260 return ERROR_OK;
1261 }
1262
1263 /**
1264 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1265 * line or by programming a watchpoint to trigger on any address. It is
1266 * considered a bug to call this function while the target is in the
1267 * TARGET_RESET state.
1268 *
1269 * @param target Pointer to the ARM7/9 target to be halted
1270 * @return Always ERROR_OK
1271 */
1272 int arm7_9_halt(struct target *target)
1273 {
1274 if (target->state == TARGET_RESET)
1275 {
1276 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1277 return ERROR_OK;
1278 }
1279
1280 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1281 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1282
1283 LOG_DEBUG("target->state: %s",
1284 target_state_name(target));
1285
1286 if (target->state == TARGET_HALTED)
1287 {
1288 LOG_DEBUG("target was already halted");
1289 return ERROR_OK;
1290 }
1291
1292 if (target->state == TARGET_UNKNOWN)
1293 {
1294 LOG_WARNING("target was in unknown state when halt was requested");
1295 }
1296
1297 if (arm7_9->use_dbgrq)
1298 {
1299 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1300 */
1301 if (arm7_9->set_special_dbgrq) {
1302 arm7_9->set_special_dbgrq(target);
1303 } else {
1304 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1305 embeddedice_store_reg(dbg_ctrl);
1306 }
1307 }
1308 else
1309 {
1310 /* program watchpoint unit to match on any address
1311 */
1312 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1313 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1314 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1315 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1316 }
1317
1318 target->debug_reason = DBG_REASON_DBGRQ;
1319
1320 return ERROR_OK;
1321 }
1322
1323 /**
1324 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1325 * ARM. The JTAG queue is then executed and the reason for debug entry is
1326 * examined. Once done, the target is verified to be halted and the processor
1327 * is forced into ARM mode. The core registers are saved for the current core
1328 * mode and the program counter (register 15) is updated as needed. The core
1329 * registers and CPSR and SPSR are saved for restoration later.
1330 *
1331 * @param target Pointer to target that is entering debug mode
1332 * @return Error code if anything fails, otherwise ERROR_OK
1333 */
1334 static int arm7_9_debug_entry(struct target *target)
1335 {
1336 int i;
1337 uint32_t context[16];
1338 uint32_t* context_p[16];
1339 uint32_t r0_thumb, pc_thumb;
1340 uint32_t cpsr, cpsr_mask = 0;
1341 int retval;
1342 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1343 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1344 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1345 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1346
1347 #ifdef _DEBUG_ARM7_9_
1348 LOG_DEBUG("-");
1349 #endif
1350
1351 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1352 * ensure that DBGRQ is cleared
1353 */
1354 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1355 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1356 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1357 embeddedice_store_reg(dbg_ctrl);
1358
1359 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1360 {
1361 return retval;
1362 }
1363
1364 if ((retval = jtag_execute_queue()) != ERROR_OK)
1365 {
1366 return retval;
1367 }
1368
1369 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1370 return retval;
1371
1372
1373 if (target->state != TARGET_HALTED)
1374 {
1375 LOG_WARNING("target not halted");
1376 return ERROR_TARGET_NOT_HALTED;
1377 }
1378
1379 /* if the target is in Thumb state, change to ARM state */
1380 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1381 {
1382 LOG_DEBUG("target entered debug from Thumb state");
1383 /* Entered debug from Thumb mode */
1384 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1385 cpsr_mask = 1 << 5;
1386 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1387 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
1388 ", pc_thumb: 0x%8.8" PRIx32, r0_thumb, pc_thumb);
1389 } else if (buf_get_u32(dbg_stat->value, 5, 1)) {
1390 /* \todo Get some vaguely correct handling of Jazelle, if
1391 * anyone ever uses it and full info becomes available.
1392 * See ARM9EJS TRM B.7.1 for how to switch J->ARM; and
1393 * B.7.3 for the reverse. That'd be the bare minimum...
1394 */
1395 LOG_DEBUG("target entered debug from Jazelle state");
1396 armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
1397 cpsr_mask = 1 << 24;
1398 LOG_ERROR("Jazelle debug entry -- BROKEN!");
1399 } else {
1400 LOG_DEBUG("target entered debug from ARM state");
1401 /* Entered debug from ARM mode */
1402 armv4_5->core_state = ARMV4_5_STATE_ARM;
1403 }
1404
1405 for (i = 0; i < 16; i++)
1406 context_p[i] = &context[i];
1407 /* save core registers (r0 - r15 of current core mode) */
1408 arm7_9->read_core_regs(target, 0xffff, context_p);
1409
1410 arm7_9->read_xpsr(target, &cpsr, 0);
1411
1412 if ((retval = jtag_execute_queue()) != ERROR_OK)
1413 return retval;
1414
1415 /* Sync our CPSR copy with J or T bits EICE reported, but
1416 * which we then erased by putting the core into ARM mode.
1417 */
1418 arm_set_cpsr(armv4_5, cpsr | cpsr_mask);
1419
1420 if (!is_arm_mode(armv4_5->core_mode))
1421 {
1422 target->state = TARGET_UNKNOWN;
1423 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1424 return ERROR_TARGET_FAILURE;
1425 }
1426
1427 LOG_DEBUG("target entered debug state in %s mode",
1428 arm_mode_name(armv4_5->core_mode));
1429
1430 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1431 {
1432 LOG_DEBUG("thumb state, applying fixups");
1433 context[0] = r0_thumb;
1434 context[15] = pc_thumb;
1435 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1436 {
1437 /* adjust value stored by STM */
1438 context[15] -= 3 * 4;
1439 }
1440
1441 if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
1442 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1443 else
1444 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1445
1446 for (i = 0; i <= 15; i++)
1447 {
1448 struct reg *r = arm_reg_current(armv4_5, i);
1449
1450 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
1451
1452 buf_set_u32(r->value, 0, 32, context[i]);
1453 /* r0 and r15 (pc) have to be restored later */
1454 r->dirty = (i == 0) || (i == 15);
1455 r->valid = 1;
1456 }
1457
1458 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
1459
1460 /* exceptions other than USR & SYS have a saved program status register */
1461 if (armv4_5->spsr) {
1462 uint32_t spsr;
1463 arm7_9->read_xpsr(target, &spsr, 1);
1464 if ((retval = jtag_execute_queue()) != ERROR_OK)
1465 {
1466 return retval;
1467 }
1468 buf_set_u32(armv4_5->spsr->value, 0, 32, spsr);
1469 armv4_5->spsr->dirty = 0;
1470 armv4_5->spsr->valid = 1;
1471 }
1472
1473 if ((retval = jtag_execute_queue()) != ERROR_OK)
1474 return retval;
1475
1476 if (arm7_9->post_debug_entry)
1477 arm7_9->post_debug_entry(target);
1478
1479 return ERROR_OK;
1480 }
1481
1482 /**
1483 * Validate the full context for an ARM7/9 target in all processor modes. If
1484 * there are any invalid registers for the target, they will all be read. This
1485 * includes the PSR.
1486 *
1487 * @param target Pointer to the ARM7/9 target to capture the full context from
1488 * @return Error if the target is not halted, has an invalid core mode, or if
1489 * the JTAG queue fails to execute
1490 */
1491 int arm7_9_full_context(struct target *target)
1492 {
1493 int i;
1494 int retval;
1495 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1496 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1497
1498 LOG_DEBUG("-");
1499
1500 if (target->state != TARGET_HALTED)
1501 {
1502 LOG_WARNING("target not halted");
1503 return ERROR_TARGET_NOT_HALTED;
1504 }
1505
1506 if (!is_arm_mode(armv4_5->core_mode))
1507 return ERROR_FAIL;
1508
1509 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1510 * SYS shares registers with User, so we don't touch SYS
1511 */
1512 for (i = 0; i < 6; i++)
1513 {
1514 uint32_t mask = 0;
1515 uint32_t* reg_p[16];
1516 int j;
1517 int valid = 1;
1518
1519 /* check if there are invalid registers in the current mode
1520 */
1521 for (j = 0; j <= 16; j++)
1522 {
1523 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1524 valid = 0;
1525 }
1526
1527 if (!valid)
1528 {
1529 uint32_t tmp_cpsr;
1530
1531 /* change processor mode (and mask T bit) */
1532 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
1533 & 0xe0;
1534 tmp_cpsr |= armv4_5_number_to_mode(i);
1535 tmp_cpsr &= ~0x20;
1536 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1537
1538 for (j = 0; j < 15; j++)
1539 {
1540 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1541 {
1542 reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1543 mask |= 1 << j;
1544 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1545 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1546 }
1547 }
1548
1549 /* if only the PSR is invalid, mask is all zeroes */
1550 if (mask)
1551 arm7_9->read_core_regs(target, mask, reg_p);
1552
1553 /* check if the PSR has to be read */
1554 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1555 {
1556 arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1557 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1558 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1559 }
1560 }
1561 }
1562
1563 /* restore processor mode (mask T bit) */
1564 arm7_9->write_xpsr_im8(target,
1565 buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
1566 0, 0);
1567
1568 if ((retval = jtag_execute_queue()) != ERROR_OK)
1569 {
1570 return retval;
1571 }
1572 return ERROR_OK;
1573 }
1574
1575 /**
1576 * Restore the processor context on an ARM7/9 target. The full processor
1577 * context is analyzed to see if any of the registers are dirty on this end, but
1578 * have a valid new value. If this is the case, the processor is changed to the
1579 * appropriate mode and the new register values are written out to the
1580 * processor. If there happens to be a dirty register with an invalid value, an
1581 * error will be logged.
1582 *
1583 * @param target Pointer to the ARM7/9 target to have its context restored
1584 * @return Error status if the target is not halted or the core mode in the
1585 * armv4_5 struct is invalid.
1586 */
1587 int arm7_9_restore_context(struct target *target)
1588 {
1589 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1590 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1591 struct reg *reg;
1592 struct arm_reg *reg_arch_info;
1593 enum armv4_5_mode current_mode = armv4_5->core_mode;
1594 int i, j;
1595 int dirty;
1596 int mode_change;
1597
1598 LOG_DEBUG("-");
1599
1600 if (target->state != TARGET_HALTED)
1601 {
1602 LOG_WARNING("target not halted");
1603 return ERROR_TARGET_NOT_HALTED;
1604 }
1605
1606 if (arm7_9->pre_restore_context)
1607 arm7_9->pre_restore_context(target);
1608
1609 if (!is_arm_mode(armv4_5->core_mode))
1610 return ERROR_FAIL;
1611
1612 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1613 * SYS shares registers with User, so we don't touch SYS
1614 */
1615 for (i = 0; i < 6; i++)
1616 {
1617 LOG_DEBUG("examining %s mode",
1618 arm_mode_name(armv4_5->core_mode));
1619 dirty = 0;
1620 mode_change = 0;
1621 /* check if there are dirty registers in the current mode
1622 */
1623 for (j = 0; j <= 16; j++)
1624 {
1625 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1626 reg_arch_info = reg->arch_info;
1627 if (reg->dirty == 1)
1628 {
1629 if (reg->valid == 1)
1630 {
1631 dirty = 1;
1632 LOG_DEBUG("examining dirty reg: %s", reg->name);
1633 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1634 && (reg_arch_info->mode != current_mode)
1635 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1636 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1637 {
1638 mode_change = 1;
1639 LOG_DEBUG("require mode change");
1640 }
1641 }
1642 else
1643 {
1644 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1645 }
1646 }
1647 }
1648
1649 if (dirty)
1650 {
1651 uint32_t mask = 0x0;
1652 int num_regs = 0;
1653 uint32_t regs[16];
1654
1655 if (mode_change)
1656 {
1657 uint32_t tmp_cpsr;
1658
1659 /* change processor mode (mask T bit) */
1660 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
1661 0, 8) & 0xe0;
1662 tmp_cpsr |= armv4_5_number_to_mode(i);
1663 tmp_cpsr &= ~0x20;
1664 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1665 current_mode = armv4_5_number_to_mode(i);
1666 }
1667
1668 for (j = 0; j <= 14; j++)
1669 {
1670 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1671 reg_arch_info = reg->arch_info;
1672
1673
1674 if (reg->dirty == 1)
1675 {
1676 regs[j] = buf_get_u32(reg->value, 0, 32);
1677 mask |= 1 << j;
1678 num_regs++;
1679 reg->dirty = 0;
1680 reg->valid = 1;
1681 LOG_DEBUG("writing register %i mode %s "
1682 "with value 0x%8.8" PRIx32, j,
1683 arm_mode_name(armv4_5->core_mode),
1684 regs[j]);
1685 }
1686 }
1687
1688 if (mask)
1689 {
1690 arm7_9->write_core_regs(target, mask, regs);
1691 }
1692
1693 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1694 reg_arch_info = reg->arch_info;
1695 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1696 {
1697 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
1698 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1699 }
1700 }
1701 }
1702
1703 if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
1704 {
1705 /* restore processor mode (mask T bit) */
1706 uint32_t tmp_cpsr;
1707
1708 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
1709 tmp_cpsr |= armv4_5_number_to_mode(i);
1710 tmp_cpsr &= ~0x20;
1711 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
1712 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1713 }
1714 else if (armv4_5->cpsr->dirty)
1715 {
1716 /* CPSR has been changed, full restore necessary (mask T bit) */
1717 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1718 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1719 arm7_9->write_xpsr(target,
1720 buf_get_u32(armv4_5->cpsr->value, 0, 32)
1721 & ~0x20, 0);
1722 armv4_5->cpsr->dirty = 0;
1723 armv4_5->cpsr->valid = 1;
1724 }
1725
1726 /* restore PC */
1727 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1728 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1729 armv4_5->core_cache->reg_list[15].dirty = 0;
1730
1731 if (arm7_9->post_restore_context)
1732 arm7_9->post_restore_context(target);
1733
1734 return ERROR_OK;
1735 }
1736
1737 /**
1738 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1739 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1740 * restart.
1741 *
1742 * @param target Pointer to the ARM7/9 target to be restarted
1743 * @return Result of executing the JTAG queue
1744 */
1745 int arm7_9_restart_core(struct target *target)
1746 {
1747 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1748 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
1749
1750 /* set RESTART instruction */
1751 jtag_set_end_state(TAP_IDLE);
1752 if (arm7_9->need_bypass_before_restart) {
1753 arm7_9->need_bypass_before_restart = 0;
1754 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1755 }
1756 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1757
1758 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
1759 return jtag_execute_queue();
1760 }
1761
1762 /**
1763 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1764 * iterated through and are set on the target if they aren't already set.
1765 *
1766 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1767 */
1768 void arm7_9_enable_watchpoints(struct target *target)
1769 {
1770 struct watchpoint *watchpoint = target->watchpoints;
1771
1772 while (watchpoint)
1773 {
1774 if (watchpoint->set == 0)
1775 arm7_9_set_watchpoint(target, watchpoint);
1776 watchpoint = watchpoint->next;
1777 }
1778 }
1779
1780 /**
1781 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1782 * iterated through and are set on the target.
1783 *
1784 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1785 */
1786 void arm7_9_enable_breakpoints(struct target *target)
1787 {
1788 struct breakpoint *breakpoint = target->breakpoints;
1789
1790 /* set any pending breakpoints */
1791 while (breakpoint)
1792 {
1793 arm7_9_set_breakpoint(target, breakpoint);
1794 breakpoint = breakpoint->next;
1795 }
1796 }
1797
1798 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
1799 {
1800 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1801 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1802 struct breakpoint *breakpoint = target->breakpoints;
1803 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1804 int err, retval = ERROR_OK;
1805
1806 LOG_DEBUG("-");
1807
1808 if (target->state != TARGET_HALTED)
1809 {
1810 LOG_WARNING("target not halted");
1811 return ERROR_TARGET_NOT_HALTED;
1812 }
1813
1814 if (!debug_execution)
1815 {
1816 target_free_all_working_areas(target);
1817 }
1818
1819 /* current = 1: continue on current pc, otherwise continue at <address> */
1820 if (!current)
1821 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1822
1823 uint32_t current_pc;
1824 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1825
1826 /* the front-end may request us not to handle breakpoints */
1827 if (handle_breakpoints)
1828 {
1829 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1830 {
1831 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
1832 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1833 {
1834 return retval;
1835 }
1836
1837 /* calculate PC of next instruction */
1838 uint32_t next_pc;
1839 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1840 {
1841 uint32_t current_opcode;
1842 target_read_u32(target, current_pc, &current_opcode);
1843 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1844 return retval;
1845 }
1846
1847 LOG_DEBUG("enable single-step");
1848 arm7_9->enable_single_step(target, next_pc);
1849
1850 target->debug_reason = DBG_REASON_SINGLESTEP;
1851
1852 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1853 {
1854 return retval;
1855 }
1856
1857 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1858 arm7_9->branch_resume(target);
1859 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1860 {
1861 arm7_9->branch_resume_thumb(target);
1862 }
1863 else
1864 {
1865 LOG_ERROR("unhandled core state");
1866 return ERROR_FAIL;
1867 }
1868
1869 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1870 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1871 err = arm7_9_execute_sys_speed(target);
1872
1873 LOG_DEBUG("disable single-step");
1874 arm7_9->disable_single_step(target);
1875
1876 if (err != ERROR_OK)
1877 {
1878 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1879 {
1880 return retval;
1881 }
1882 target->state = TARGET_UNKNOWN;
1883 return err;
1884 }
1885
1886 arm7_9_debug_entry(target);
1887 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1888
1889 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1890 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1891 {
1892 return retval;
1893 }
1894 }
1895 }
1896
1897 /* enable any pending breakpoints and watchpoints */
1898 arm7_9_enable_breakpoints(target);
1899 arm7_9_enable_watchpoints(target);
1900
1901 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1902 {
1903 return retval;
1904 }
1905
1906 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1907 {
1908 arm7_9->branch_resume(target);
1909 }
1910 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1911 {
1912 arm7_9->branch_resume_thumb(target);
1913 }
1914 else
1915 {
1916 LOG_ERROR("unhandled core state");
1917 return ERROR_FAIL;
1918 }
1919
1920 /* deassert DBGACK and INTDIS */
1921 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1922 /* INTDIS only when we really resume, not during debug execution */
1923 if (!debug_execution)
1924 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1925 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1926
1927 if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1928 {
1929 return retval;
1930 }
1931
1932 target->debug_reason = DBG_REASON_NOTHALTED;
1933
1934 if (!debug_execution)
1935 {
1936 /* registers are now invalid */
1937 register_cache_invalidate(armv4_5->core_cache);
1938 target->state = TARGET_RUNNING;
1939 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1940 {
1941 return retval;
1942 }
1943 }
1944 else
1945 {
1946 target->state = TARGET_DEBUG_RUNNING;
1947 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1948 {
1949 return retval;
1950 }
1951 }
1952
1953 LOG_DEBUG("target resumed");
1954
1955 return ERROR_OK;
1956 }
1957
1958 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
1959 {
1960 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1961 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1962 uint32_t current_pc;
1963 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1964
1965 if (next_pc != current_pc)
1966 {
1967 /* setup an inverse breakpoint on the current PC
1968 * - comparator 1 matches the current address
1969 * - rangeout from comparator 1 is connected to comparator 0 rangein
1970 * - comparator 0 matches any address, as long as rangein is low */
1971 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1972 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1973 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1974 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
1975 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1976 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1977 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1978 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1979 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1980 }
1981 else
1982 {
1983 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1984 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1985 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
1986 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
1987 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
1988 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1989 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1990 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1991 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1992 }
1993 }
1994
1995 void arm7_9_disable_eice_step(struct target *target)
1996 {
1997 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1998
1999 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
2000 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
2001 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
2002 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
2003 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
2004 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
2005 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
2006 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
2007 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
2008 }
2009
2010 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
2011 {
2012 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2013 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2014 struct breakpoint *breakpoint = NULL;
2015 int err, retval;
2016
2017 if (target->state != TARGET_HALTED)
2018 {
2019 LOG_WARNING("target not halted");
2020 return ERROR_TARGET_NOT_HALTED;
2021 }
2022
2023 /* current = 1: continue on current pc, otherwise continue at <address> */
2024 if (!current)
2025 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
2026
2027 uint32_t current_pc;
2028 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2029
2030 /* the front-end may request us not to handle breakpoints */
2031 if (handle_breakpoints)
2032 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
2033 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
2034 {
2035 return retval;
2036 }
2037
2038 target->debug_reason = DBG_REASON_SINGLESTEP;
2039
2040 /* calculate PC of next instruction */
2041 uint32_t next_pc;
2042 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
2043 {
2044 uint32_t current_opcode;
2045 target_read_u32(target, current_pc, &current_opcode);
2046 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
2047 return retval;
2048 }
2049
2050 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
2051 {
2052 return retval;
2053 }
2054
2055 arm7_9->enable_single_step(target, next_pc);
2056
2057 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
2058 {
2059 arm7_9->branch_resume(target);
2060 }
2061 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
2062 {
2063 arm7_9->branch_resume_thumb(target);
2064 }
2065 else
2066 {
2067 LOG_ERROR("unhandled core state");
2068 return ERROR_FAIL;
2069 }
2070
2071 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
2072 {
2073 return retval;
2074 }
2075
2076 err = arm7_9_execute_sys_speed(target);
2077 arm7_9->disable_single_step(target);
2078
2079 /* registers are now invalid */
2080 register_cache_invalidate(armv4_5->core_cache);
2081
2082 if (err != ERROR_OK)
2083 {
2084 target->state = TARGET_UNKNOWN;
2085 } else {
2086 arm7_9_debug_entry(target);
2087 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
2088 {
2089 return retval;
2090 }
2091 LOG_DEBUG("target stepped");
2092 }
2093
2094 if (breakpoint)
2095 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
2096 {
2097 return retval;
2098 }
2099
2100 return err;
2101 }
2102
2103 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
2104 int num, enum armv4_5_mode mode)
2105 {
2106 uint32_t* reg_p[16];
2107 uint32_t value;
2108 int retval;
2109 struct arm_reg *areg = r->arch_info;
2110 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2111 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2112
2113 if (!is_arm_mode(armv4_5->core_mode))
2114 return ERROR_FAIL;
2115 if ((num < 0) || (num > 16))
2116 return ERROR_INVALID_ARGUMENTS;
2117
2118 if ((mode != ARMV4_5_MODE_ANY)
2119 && (mode != armv4_5->core_mode)
2120 && (areg->mode != ARMV4_5_MODE_ANY))
2121 {
2122 uint32_t tmp_cpsr;
2123
2124 /* change processor mode (mask T bit) */
2125 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2126 tmp_cpsr |= mode;
2127 tmp_cpsr &= ~0x20;
2128 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2129 }
2130
2131 if ((num >= 0) && (num <= 15))
2132 {
2133 /* read a normal core register */
2134 reg_p[num] = &value;
2135
2136 arm7_9->read_core_regs(target, 1 << num, reg_p);
2137 }
2138 else
2139 {
2140 /* read a program status register
2141 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2142 */
2143 arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
2144 }
2145
2146 if ((retval = jtag_execute_queue()) != ERROR_OK)
2147 {
2148 return retval;
2149 }
2150
2151 r->valid = 1;
2152 r->dirty = 0;
2153 buf_set_u32(r->value, 0, 32, value);
2154
2155 if ((mode != ARMV4_5_MODE_ANY)
2156 && (mode != armv4_5->core_mode)
2157 && (areg->mode != ARMV4_5_MODE_ANY)) {
2158 /* restore processor mode (mask T bit) */
2159 arm7_9->write_xpsr_im8(target,
2160 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2161 & ~0x20, 0, 0);
2162 }
2163
2164 return ERROR_OK;
2165 }
2166
2167 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
2168 int num, enum armv4_5_mode mode, uint32_t value)
2169 {
2170 uint32_t reg[16];
2171 struct arm_reg *areg = r->arch_info;
2172 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2173 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2174
2175 if (!is_arm_mode(armv4_5->core_mode))
2176 return ERROR_FAIL;
2177 if ((num < 0) || (num > 16))
2178 return ERROR_INVALID_ARGUMENTS;
2179
2180 if ((mode != ARMV4_5_MODE_ANY)
2181 && (mode != armv4_5->core_mode)
2182 && (areg->mode != ARMV4_5_MODE_ANY)) {
2183 uint32_t tmp_cpsr;
2184
2185 /* change processor mode (mask T bit) */
2186 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2187 tmp_cpsr |= mode;
2188 tmp_cpsr &= ~0x20;
2189 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2190 }
2191
2192 if ((num >= 0) && (num <= 15))
2193 {
2194 /* write a normal core register */
2195 reg[num] = value;
2196
2197 arm7_9->write_core_regs(target, 1 << num, reg);
2198 }
2199 else
2200 {
2201 /* write a program status register
2202 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2203 */
2204 int spsr = (areg->mode != ARMV4_5_MODE_ANY);
2205
2206 /* if we're writing the CPSR, mask the T bit */
2207 if (!spsr)
2208 value &= ~0x20;
2209
2210 arm7_9->write_xpsr(target, value, spsr);
2211 }
2212
2213 r->valid = 1;
2214 r->dirty = 0;
2215
2216 if ((mode != ARMV4_5_MODE_ANY)
2217 && (mode != armv4_5->core_mode)
2218 && (areg->mode != ARMV4_5_MODE_ANY)) {
2219 /* restore processor mode (mask T bit) */
2220 arm7_9->write_xpsr_im8(target,
2221 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2222 & ~0x20, 0, 0);
2223 }
2224
2225 return jtag_execute_queue();
2226 }
2227
2228 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2229 {
2230 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2231 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2232 uint32_t reg[16];
2233 uint32_t num_accesses = 0;
2234 int thisrun_accesses;
2235 int i;
2236 uint32_t cpsr;
2237 int retval;
2238 int last_reg = 0;
2239
2240 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
2241
2242 if (target->state != TARGET_HALTED)
2243 {
2244 LOG_WARNING("target not halted");
2245 return ERROR_TARGET_NOT_HALTED;
2246 }
2247
2248 /* sanitize arguments */
2249 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2250 return ERROR_INVALID_ARGUMENTS;
2251
2252 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2253 return ERROR_TARGET_UNALIGNED_ACCESS;
2254
2255 /* load the base register with the address of the first word */
2256 reg[0] = address;
2257 arm7_9->write_core_regs(target, 0x1, reg);
2258
2259 int j = 0;
2260
2261 switch (size)
2262 {
2263 case 4:
2264 while (num_accesses < count)
2265 {
2266 uint32_t reg_list;
2267 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2268 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2269
2270 if (last_reg <= thisrun_accesses)
2271 last_reg = thisrun_accesses;
2272
2273 arm7_9->load_word_regs(target, reg_list);
2274
2275 /* fast memory reads are only safe when the target is running
2276 * from a sufficiently high clock (32 kHz is usually too slow)
2277 */
2278 if (arm7_9->fast_memory_access)
2279 retval = arm7_9_execute_fast_sys_speed(target);
2280 else
2281 retval = arm7_9_execute_sys_speed(target);
2282 if (retval != ERROR_OK)
2283 return retval;
2284
2285 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2286
2287 /* advance buffer, count number of accesses */
2288 buffer += thisrun_accesses * 4;
2289 num_accesses += thisrun_accesses;
2290
2291 if ((j++%1024) == 0)
2292 {
2293 keep_alive();
2294 }
2295 }
2296 break;
2297 case 2:
2298 while (num_accesses < count)
2299 {
2300 uint32_t reg_list;
2301 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2302 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2303
2304 for (i = 1; i <= thisrun_accesses; i++)
2305 {
2306 if (i > last_reg)
2307 last_reg = i;
2308 arm7_9->load_hword_reg(target, i);
2309 /* fast memory reads are only safe when the target is running
2310 * from a sufficiently high clock (32 kHz is usually too slow)
2311 */
2312 if (arm7_9->fast_memory_access)
2313 retval = arm7_9_execute_fast_sys_speed(target);
2314 else
2315 retval = arm7_9_execute_sys_speed(target);
2316 if (retval != ERROR_OK)
2317 {
2318 return retval;
2319 }
2320
2321 }
2322
2323 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2324
2325 /* advance buffer, count number of accesses */
2326 buffer += thisrun_accesses * 2;
2327 num_accesses += thisrun_accesses;
2328
2329 if ((j++%1024) == 0)
2330 {
2331 keep_alive();
2332 }
2333 }
2334 break;
2335 case 1:
2336 while (num_accesses < count)
2337 {
2338 uint32_t reg_list;
2339 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2340 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2341
2342 for (i = 1; i <= thisrun_accesses; i++)
2343 {
2344 if (i > last_reg)
2345 last_reg = i;
2346 arm7_9->load_byte_reg(target, i);
2347 /* fast memory reads are only safe when the target is running
2348 * from a sufficiently high clock (32 kHz is usually too slow)
2349 */
2350 if (arm7_9->fast_memory_access)
2351 retval = arm7_9_execute_fast_sys_speed(target);
2352 else
2353 retval = arm7_9_execute_sys_speed(target);
2354 if (retval != ERROR_OK)
2355 {
2356 return retval;
2357 }
2358 }
2359
2360 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2361
2362 /* advance buffer, count number of accesses */
2363 buffer += thisrun_accesses * 1;
2364 num_accesses += thisrun_accesses;
2365
2366 if ((j++%1024) == 0)
2367 {
2368 keep_alive();
2369 }
2370 }
2371 break;
2372 default:
2373 LOG_ERROR("BUG: we shouldn't get here");
2374 exit(-1);
2375 break;
2376 }
2377
2378 if (!is_arm_mode(armv4_5->core_mode))
2379 return ERROR_FAIL;
2380
2381 for (i = 0; i <= last_reg; i++) {
2382 struct reg *r = arm_reg_current(armv4_5, i);
2383
2384 r->dirty = r->valid;
2385 }
2386
2387 arm7_9->read_xpsr(target, &cpsr, 0);
2388 if ((retval = jtag_execute_queue()) != ERROR_OK)
2389 {
2390 LOG_ERROR("JTAG error while reading cpsr");
2391 return ERROR_TARGET_DATA_ABORT;
2392 }
2393
2394 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2395 {
2396 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2397
2398 arm7_9->write_xpsr_im8(target,
2399 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2400 & ~0x20, 0, 0);
2401
2402 return ERROR_TARGET_DATA_ABORT;
2403 }
2404
2405 return ERROR_OK;
2406 }
2407
2408 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2409 {
2410 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2411 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2412 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2413
2414 uint32_t reg[16];
2415 uint32_t num_accesses = 0;
2416 int thisrun_accesses;
2417 int i;
2418 uint32_t cpsr;
2419 int retval;
2420 int last_reg = 0;
2421
2422 #ifdef _DEBUG_ARM7_9_
2423 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2424 #endif
2425
2426 if (target->state != TARGET_HALTED)
2427 {
2428 LOG_WARNING("target not halted");
2429 return ERROR_TARGET_NOT_HALTED;
2430 }
2431
2432 /* sanitize arguments */
2433 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2434 return ERROR_INVALID_ARGUMENTS;
2435
2436 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2437 return ERROR_TARGET_UNALIGNED_ACCESS;
2438
2439 /* load the base register with the address of the first word */
2440 reg[0] = address;
2441 arm7_9->write_core_regs(target, 0x1, reg);
2442
2443 /* Clear DBGACK, to make sure memory fetches work as expected */
2444 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2445 embeddedice_store_reg(dbg_ctrl);
2446
2447 switch (size)
2448 {
2449 case 4:
2450 while (num_accesses < count)
2451 {
2452 uint32_t reg_list;
2453 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2454 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2455
2456 for (i = 1; i <= thisrun_accesses; i++)
2457 {
2458 if (i > last_reg)
2459 last_reg = i;
2460 reg[i] = target_buffer_get_u32(target, buffer);
2461 buffer += 4;
2462 }
2463
2464 arm7_9->write_core_regs(target, reg_list, reg);
2465
2466 arm7_9->store_word_regs(target, reg_list);
2467
2468 /* fast memory writes are only safe when the target is running
2469 * from a sufficiently high clock (32 kHz is usually too slow)
2470 */
2471 if (arm7_9->fast_memory_access)
2472 retval = arm7_9_execute_fast_sys_speed(target);
2473 else
2474 retval = arm7_9_execute_sys_speed(target);
2475 if (retval != ERROR_OK)
2476 {
2477 return retval;
2478 }
2479
2480 num_accesses += thisrun_accesses;
2481 }
2482 break;
2483 case 2:
2484 while (num_accesses < count)
2485 {
2486 uint32_t reg_list;
2487 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2488 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2489
2490 for (i = 1; i <= thisrun_accesses; i++)
2491 {
2492 if (i > last_reg)
2493 last_reg = i;
2494 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2495 buffer += 2;
2496 }
2497
2498 arm7_9->write_core_regs(target, reg_list, reg);
2499
2500 for (i = 1; i <= thisrun_accesses; i++)
2501 {
2502 arm7_9->store_hword_reg(target, i);
2503
2504 /* fast memory writes are only safe when the target is running
2505 * from a sufficiently high clock (32 kHz is usually too slow)
2506 */
2507 if (arm7_9->fast_memory_access)
2508 retval = arm7_9_execute_fast_sys_speed(target);
2509 else
2510 retval = arm7_9_execute_sys_speed(target);
2511 if (retval != ERROR_OK)
2512 {
2513 return retval;
2514 }
2515 }
2516
2517 num_accesses += thisrun_accesses;
2518 }
2519 break;
2520 case 1:
2521 while (num_accesses < count)
2522 {
2523 uint32_t reg_list;
2524 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2525 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2526
2527 for (i = 1; i <= thisrun_accesses; i++)
2528 {
2529 if (i > last_reg)
2530 last_reg = i;
2531 reg[i] = *buffer++ & 0xff;
2532 }
2533
2534 arm7_9->write_core_regs(target, reg_list, reg);
2535
2536 for (i = 1; i <= thisrun_accesses; i++)
2537 {
2538 arm7_9->store_byte_reg(target, i);
2539 /* fast memory writes are only safe when the target is running
2540 * from a sufficiently high clock (32 kHz is usually too slow)
2541 */
2542 if (arm7_9->fast_memory_access)
2543 retval = arm7_9_execute_fast_sys_speed(target);
2544 else
2545 retval = arm7_9_execute_sys_speed(target);
2546 if (retval != ERROR_OK)
2547 {
2548 return retval;
2549 }
2550
2551 }
2552
2553 num_accesses += thisrun_accesses;
2554 }
2555 break;
2556 default:
2557 LOG_ERROR("BUG: we shouldn't get here");
2558 exit(-1);
2559 break;
2560 }
2561
2562 /* Re-Set DBGACK */
2563 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2564 embeddedice_store_reg(dbg_ctrl);
2565
2566 if (!is_arm_mode(armv4_5->core_mode))
2567 return ERROR_FAIL;
2568
2569 for (i = 0; i <= last_reg; i++) {
2570 struct reg *r = arm_reg_current(armv4_5, i);
2571
2572 r->dirty = r->valid;
2573 }
2574
2575 arm7_9->read_xpsr(target, &cpsr, 0);
2576 if ((retval = jtag_execute_queue()) != ERROR_OK)
2577 {
2578 LOG_ERROR("JTAG error while reading cpsr");
2579 return ERROR_TARGET_DATA_ABORT;
2580 }
2581
2582 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2583 {
2584 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2585
2586 arm7_9->write_xpsr_im8(target,
2587 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2588 & ~0x20, 0, 0);
2589
2590 return ERROR_TARGET_DATA_ABORT;
2591 }
2592
2593 return ERROR_OK;
2594 }
2595
2596 static int dcc_count;
2597 static uint8_t *dcc_buffer;
2598
2599 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
2600 {
2601 int retval = ERROR_OK;
2602 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2603
2604 if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
2605 return retval;
2606
2607 int little = target->endianness == TARGET_LITTLE_ENDIAN;
2608 int count = dcc_count;
2609 uint8_t *buffer = dcc_buffer;
2610 if (count > 2)
2611 {
2612 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2613 * core function repeated. */
2614 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2615 buffer += 4;
2616
2617 struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2618 uint8_t reg_addr = ice_reg->addr & 0x1f;
2619 struct jtag_tap *tap;
2620 tap = ice_reg->jtag_info->tap;
2621
2622 embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
2623 buffer += (count-2)*4;
2624
2625 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2626 } else
2627 {
2628 int i;
2629 for (i = 0; i < count; i++)
2630 {
2631 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2632 buffer += 4;
2633 }
2634 }
2635
2636 if ((retval = target_halt(target))!= ERROR_OK)
2637 {
2638 return retval;
2639 }
2640 return target_wait_state(target, TARGET_HALTED, 500);
2641 }
2642
2643 static const uint32_t dcc_code[] =
2644 {
2645 /* r0 == input, points to memory buffer
2646 * r1 == scratch
2647 */
2648
2649 /* spin until DCC control (c0) reports data arrived */
2650 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2651 0xe3110001, /* tst r1, #1 */
2652 0x0afffffc, /* bne w */
2653
2654 /* read word from DCC (c1), write to memory */
2655 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2656 0xe4801004, /* str r1, [r0], #4 */
2657
2658 /* repeat */
2659 0xeafffff9 /* b w */
2660 };
2661
2662 int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info));
2663
2664 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
2665 {
2666 int retval;
2667 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2668 int i;
2669
2670 if (!arm7_9->dcc_downloads)
2671 return target_write_memory(target, address, 4, count, buffer);
2672
2673 /* regrab previously allocated working_area, or allocate a new one */
2674 if (!arm7_9->dcc_working_area)
2675 {
2676 uint8_t dcc_code_buf[6 * 4];
2677
2678 /* make sure we have a working area */
2679 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2680 {
2681 LOG_INFO("no working area available, falling back to memory writes");
2682 return target_write_memory(target, address, 4, count, buffer);
2683 }
2684
2685 /* copy target instructions to target endianness */
2686 for (i = 0; i < 6; i++)
2687 {
2688 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2689 }
2690
2691 /* write DCC code to working area */
2692 if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2693 {
2694 return retval;
2695 }
2696 }
2697
2698 struct armv4_5_algorithm armv4_5_info;
2699 struct reg_param reg_params[1];
2700
2701 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2702 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2703 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2704
2705 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
2706
2707 buf_set_u32(reg_params[0].value, 0, 32, address);
2708
2709 dcc_count = count;
2710 dcc_buffer = buffer;
2711 retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2712 arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2713
2714 if (retval == ERROR_OK)
2715 {
2716 uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
2717 if (endaddress != (address + count*4))
2718 {
2719 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
2720 retval = ERROR_FAIL;
2721 }
2722 }
2723
2724 destroy_reg_param(&reg_params[0]);
2725
2726 return retval;
2727 }
2728
2729 /**
2730 * Perform per-target setup that requires JTAG access.
2731 */
2732 int arm7_9_examine(struct target *target)
2733 {
2734 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2735 int retval;
2736
2737 if (!target_was_examined(target)) {
2738 struct reg_cache *t, **cache_p;
2739
2740 t = embeddedice_build_reg_cache(target, arm7_9);
2741 if (t == NULL)
2742 return ERROR_FAIL;
2743
2744 cache_p = register_get_last_cache_p(&target->reg_cache);
2745 (*cache_p) = t;
2746 arm7_9->eice_cache = (*cache_p);
2747
2748 if (arm7_9->armv4_5_common.etm)
2749 (*cache_p)->next = etm_build_reg_cache(target,
2750 &arm7_9->jtag_info,
2751 arm7_9->armv4_5_common.etm);
2752
2753 target_set_examined(target);
2754 }
2755
2756 retval = embeddedice_setup(target);
2757 if (retval == ERROR_OK)
2758 retval = arm7_9_setup(target);
2759 if (retval == ERROR_OK && arm7_9->armv4_5_common.etm)
2760 retval = etm_setup(target);
2761 return retval;
2762 }
2763
2764 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
2765 {
2766 struct target *target = get_current_target(CMD_CTX);
2767 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2768
2769 if (!is_arm7_9(arm7_9))
2770 {
2771 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2772 return ERROR_TARGET_INVALID;
2773 }
2774
2775 if (CMD_ARGC > 0)
2776 COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
2777
2778 command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2779
2780 return ERROR_OK;
2781 }
2782
2783 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
2784 {
2785 struct target *target = get_current_target(CMD_CTX);
2786 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2787
2788 if (!is_arm7_9(arm7_9))
2789 {
2790 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2791 return ERROR_TARGET_INVALID;
2792 }
2793
2794 if (CMD_ARGC > 0)
2795 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
2796
2797 command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2798
2799 return ERROR_OK;
2800 }
2801
2802 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
2803 {
2804 struct target *target = get_current_target(CMD_CTX);
2805 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2806
2807 if (!is_arm7_9(arm7_9))
2808 {
2809 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2810 return ERROR_TARGET_INVALID;
2811 }
2812
2813 if (CMD_ARGC > 0)
2814 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
2815
2816 command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2817
2818 return ERROR_OK;
2819 }
2820
2821 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
2822 {
2823 int retval = ERROR_OK;
2824 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2825
2826 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2827
2828 if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2829 return retval;
2830
2831 /* caller must have allocated via calloc(), so everything's zeroed */
2832
2833 arm7_9->wp_available_max = 2;
2834
2835 arm7_9->fast_memory_access = false;
2836 arm7_9->dcc_downloads = false;
2837
2838 armv4_5->arch_info = arm7_9;
2839 armv4_5->read_core_reg = arm7_9_read_core_reg;
2840 armv4_5->write_core_reg = arm7_9_write_core_reg;
2841 armv4_5->full_context = arm7_9_full_context;
2842
2843 if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
2844 return retval;
2845
2846 return target_register_timer_callback(arm7_9_handle_target_request,
2847 1, 1, target);
2848 }
2849
2850 static const struct command_registration arm7_9_any_command_handlers[] = {
2851 {
2852 "dbgrq",
2853 .handler = &handle_arm7_9_dbgrq_command,
2854 .mode = COMMAND_ANY,
2855 .usage = "<enable|disable>",
2856 .help = "use EmbeddedICE dbgrq instead of breakpoint "
2857 "for target halt requests",
2858 },
2859 {
2860 "fast_memory_access",
2861 .handler = &handle_arm7_9_fast_memory_access_command,
2862 .mode = COMMAND_ANY,
2863 .usage = "<enable|disable>",
2864 .help = "use fast memory accesses instead of slower "
2865 "but potentially safer accesses",
2866 },
2867 {
2868 "dcc_downloads",
2869 .handler = &handle_arm7_9_dcc_downloads_command,
2870 .mode = COMMAND_ANY,
2871 .usage = "<enable | disable>",
2872 .help = "use DCC downloads for larger memory writes",
2873 },
2874 COMMAND_REGISTRATION_DONE
2875 };
2876 static const struct command_registration arm7_9_command_handlers[] = {
2877 {
2878 .name = "arm7_9",
2879 .mode = COMMAND_ANY,
2880 .help = "arm7/9 specific commands",
2881 .chain = arm7_9_any_command_handlers,
2882 },
2883 COMMAND_REGISTRATION_DONE
2884 };
2885
2886 int arm7_9_register_commands(struct command_context *cmd_ctx)
2887 {
2888 armv4_5_register_commands(cmd_ctx);
2889 etm_register_commands(cmd_ctx);
2890 return register_commands(cmd_ctx, NULL, arm7_9_command_handlers);
2891 }