1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2008 by Hongtao Zheng *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
33 #include "embeddedice.h"
34 #include "target_request.h"
35 #include "arm7_9_common.h"
36 #include "time_support.h"
37 #include "arm_simulator.h"
40 int arm7_9_debug_entry(target_t
*target
);
41 int arm7_9_enable_sw_bkpts(struct target_s
*target
);
43 /* command handler forward declarations */
44 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int handle_arm7_9_read_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
47 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
49 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
50 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
51 int handle_arm7_9_etm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
54 * Clear watchpoints for an ARM7/9 target.
56 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
57 * @return JTAG error status after executing queue
59 static int arm7_9_clear_watchpoints(arm7_9_common_t
*arm7_9
)
62 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
63 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
64 arm7_9
->sw_breakpoint_count
= 0;
65 arm7_9
->sw_breakpoints_added
= 0;
67 arm7_9
->wp1_used
= arm7_9
->wp1_used_default
;
68 arm7_9
->wp_available
= arm7_9
->wp_available_max
;
70 return jtag_execute_queue();
74 * Assign a watchpoint to one of the two available hardware comparators in an
75 * ARM7 or ARM9 target.
77 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
78 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
80 static void arm7_9_assign_wp(arm7_9_common_t
*arm7_9
, breakpoint_t
*breakpoint
)
82 if (!arm7_9
->wp0_used
)
86 arm7_9
->wp_available
--;
88 else if (!arm7_9
->wp1_used
)
92 arm7_9
->wp_available
--;
96 LOG_ERROR("BUG: no hardware comparator available");
98 LOG_DEBUG("BPID: %d (0x%08" PRIx32
") using hw wp: %d",
99 breakpoint
->unique_id
,
105 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
107 * @param arm7_9 Pointer to common struct for ARM7/9 targets
108 * @return Error codes if there is a problem finding a watchpoint or the result
109 * of executing the JTAG queue
111 static int arm7_9_set_software_breakpoints(arm7_9_common_t
*arm7_9
)
113 if (arm7_9
->sw_breakpoints_added
)
117 if (arm7_9
->wp_available
< 1)
119 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
120 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
122 arm7_9
->wp_available
--;
124 /* pick a breakpoint unit */
125 if (!arm7_9
->wp0_used
)
127 arm7_9
->sw_breakpoints_added
= 1;
128 arm7_9
->wp0_used
= 3;
129 } else if (!arm7_9
->wp1_used
)
131 arm7_9
->sw_breakpoints_added
= 2;
132 arm7_9
->wp1_used
= 3;
136 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
140 if (arm7_9
->sw_breakpoints_added
== 1)
142 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], arm7_9
->arm_bkpt
);
143 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0x0);
144 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffffu
);
145 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
146 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
148 else if (arm7_9
->sw_breakpoints_added
== 2)
150 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], arm7_9
->arm_bkpt
);
151 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0x0);
152 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0xffffffffu
);
153 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
154 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
158 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
161 LOG_DEBUG("SW BP using hw wp: %d",
162 arm7_9
->sw_breakpoints_added
);
164 return jtag_execute_queue();
168 * Setup the common pieces for an ARM7/9 target after reset or on startup.
170 * @param target Pointer to an ARM7/9 target to setup
171 * @return Result of clearing the watchpoints on the target
173 int arm7_9_setup(target_t
*target
)
175 armv4_5_common_t
*armv4_5
= target
->arch_info
;
176 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
178 return arm7_9_clear_watchpoints(arm7_9
);
182 * Retrieves the architecture information pointers for ARMv4/5 and ARM7/9
183 * targets. A return of ERROR_OK signifies that the target is a valid target
184 * and that the pointers have been set properly.
186 * @param target Pointer to the target device to get the pointers from
187 * @param armv4_5_p Pointer to be filled in with the common struct for ARMV4/5
189 * @param arm7_9_p Pointer to be filled in with the common struct for ARM7/9
191 * @return ERROR_OK if successful
193 int arm7_9_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
)
195 armv4_5_common_t
*armv4_5
= target
->arch_info
;
196 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
198 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
203 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
208 *armv4_5_p
= armv4_5
;
215 * Set either a hardware or software breakpoint on an ARM7/9 target. The
216 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
217 * might have erased the values in Embedded ICE.
219 * @param target Pointer to the target device to set the breakpoints on
220 * @param breakpoint Pointer to the breakpoint to be set
221 * @return For hardware breakpoints, this is the result of executing the JTAG
222 * queue. For software breakpoints, this will be the status of the
223 * required memory reads and writes
225 int arm7_9_set_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
227 armv4_5_common_t
*armv4_5
= target
->arch_info
;
228 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
229 int retval
= ERROR_OK
;
231 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32
", Type: %d" ,
232 breakpoint
->unique_id
,
236 if (target
->state
!= TARGET_HALTED
)
238 LOG_WARNING("target not halted");
239 return ERROR_TARGET_NOT_HALTED
;
242 if (breakpoint
->type
== BKPT_HARD
)
244 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
245 uint32_t mask
= (breakpoint
->length
== 4) ? 0x3u
: 0x1u
;
247 /* reassign a hw breakpoint */
248 if (breakpoint
->set
== 0)
250 arm7_9_assign_wp(arm7_9
, breakpoint
);
253 if (breakpoint
->set
== 1)
255 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], breakpoint
->address
);
256 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
257 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffffu
);
258 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
259 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
261 else if (breakpoint
->set
== 2)
263 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], breakpoint
->address
);
264 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
265 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffffu
);
266 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
267 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
271 LOG_ERROR("BUG: no hardware comparator available");
275 retval
= jtag_execute_queue();
277 else if (breakpoint
->type
== BKPT_SOFT
)
279 /* did we already set this breakpoint? */
283 if (breakpoint
->length
== 4)
285 uint32_t verify
= 0xffffffff;
286 /* keep the original instruction in target endianness */
287 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
291 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
292 if ((retval
= target_write_u32(target
, breakpoint
->address
, arm7_9
->arm_bkpt
)) != ERROR_OK
)
297 if ((retval
= target_read_u32(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
301 if (verify
!= arm7_9
->arm_bkpt
)
303 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
309 uint16_t verify
= 0xffff;
310 /* keep the original instruction in target endianness */
311 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
315 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
316 if ((retval
= target_write_u16(target
, breakpoint
->address
, arm7_9
->thumb_bkpt
)) != ERROR_OK
)
321 if ((retval
= target_read_u16(target
, breakpoint
->address
, &verify
)) != ERROR_OK
)
325 if (verify
!= arm7_9
->thumb_bkpt
)
327 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32
" - check that memory is read/writable", breakpoint
->address
);
332 if ((retval
= arm7_9_set_software_breakpoints(arm7_9
)) != ERROR_OK
)
335 arm7_9
->sw_breakpoint_count
++;
344 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
345 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
346 * will be updated. Otherwise, the software breakpoint will be restored to its
347 * original instruction if it hasn't already been modified.
349 * @param target Pointer to ARM7/9 target to unset the breakpoint from
350 * @param breakpoint Pointer to breakpoint to be unset
351 * @return For hardware breakpoints, this is the result of executing the JTAG
352 * queue. For software breakpoints, this will be the status of the
353 * required memory reads and writes
355 int arm7_9_unset_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
357 int retval
= ERROR_OK
;
359 armv4_5_common_t
*armv4_5
= target
->arch_info
;
360 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
362 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32
,
363 breakpoint
->unique_id
,
364 breakpoint
->address
);
366 if (!breakpoint
->set
)
368 LOG_WARNING("breakpoint not set");
372 if (breakpoint
->type
== BKPT_HARD
)
374 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
375 breakpoint
->unique_id
,
377 if (breakpoint
->set
== 1)
379 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
380 arm7_9
->wp0_used
= 0;
381 arm7_9
->wp_available
++;
383 else if (breakpoint
->set
== 2)
385 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
386 arm7_9
->wp1_used
= 0;
387 arm7_9
->wp_available
++;
389 retval
= jtag_execute_queue();
394 /* restore original instruction (kept in target endianness) */
395 if (breakpoint
->length
== 4)
397 uint32_t current_instr
;
398 /* check that user program as not modified breakpoint instruction */
399 if ((retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
403 if (current_instr
== arm7_9
->arm_bkpt
)
404 if ((retval
= target_write_memory(target
, breakpoint
->address
, 4, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
411 uint16_t current_instr
;
412 /* check that user program as not modified breakpoint instruction */
413 if ((retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, (uint8_t*)¤t_instr
)) != ERROR_OK
)
417 if (current_instr
== arm7_9
->thumb_bkpt
)
418 if ((retval
= target_write_memory(target
, breakpoint
->address
, 2, 1, breakpoint
->orig_instr
)) != ERROR_OK
)
424 if (--arm7_9
->sw_breakpoint_count
==0)
426 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
427 if (arm7_9
->sw_breakpoints_added
== 1)
429 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0);
431 else if (arm7_9
->sw_breakpoints_added
== 2)
433 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0);
444 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
445 * dangling breakpoints and that the desired breakpoint can be added.
447 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
448 * @param breakpoint Pointer to the breakpoint to be added
449 * @return An error status if there is a problem adding the breakpoint or the
450 * result of setting the breakpoint
452 int arm7_9_add_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
454 armv4_5_common_t
*armv4_5
= target
->arch_info
;
455 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
457 if (target
->state
!= TARGET_HALTED
)
459 LOG_WARNING("target not halted");
460 return ERROR_TARGET_NOT_HALTED
;
463 if (arm7_9
->breakpoint_count
== 0)
465 /* make sure we don't have any dangling breakpoints. This is vital upon
466 * GDB connect/disconnect
468 arm7_9_clear_watchpoints(arm7_9
);
471 if ((breakpoint
->type
== BKPT_HARD
) && (arm7_9
->wp_available
< 1))
473 LOG_INFO("no watchpoint unit available for hardware breakpoint");
474 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
477 if ((breakpoint
->length
!= 2) && (breakpoint
->length
!= 4))
479 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
480 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
483 if (breakpoint
->type
== BKPT_HARD
)
485 arm7_9_assign_wp(arm7_9
, breakpoint
);
488 arm7_9
->breakpoint_count
++;
490 return arm7_9_set_breakpoint(target
, breakpoint
);
494 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
495 * dangling breakpoints and updates available watchpoints if it is a hardware
498 * @param target Pointer to the target to have a breakpoint removed
499 * @param breakpoint Pointer to the breakpoint to be removed
500 * @return Error status if there was a problem unsetting the breakpoint or the
501 * watchpoints could not be cleared
503 int arm7_9_remove_breakpoint(struct target_s
*target
, breakpoint_t
*breakpoint
)
505 int retval
= ERROR_OK
;
506 armv4_5_common_t
*armv4_5
= target
->arch_info
;
507 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
509 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
514 if (breakpoint
->type
== BKPT_HARD
)
515 arm7_9
->wp_available
++;
517 arm7_9
->breakpoint_count
--;
518 if (arm7_9
->breakpoint_count
== 0)
520 /* make sure we don't have any dangling breakpoints */
521 if ((retval
= arm7_9_clear_watchpoints(arm7_9
)) != ERROR_OK
)
531 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
532 * considered a bug to call this function when there are no available watchpoint
535 * @param target Pointer to an ARM7/9 target to set a watchpoint on
536 * @param watchpoint Pointer to the watchpoint to be set
537 * @return Error status if watchpoint set fails or the result of executing the
540 int arm7_9_set_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
542 int retval
= ERROR_OK
;
543 armv4_5_common_t
*armv4_5
= target
->arch_info
;
544 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
548 mask
= watchpoint
->length
- 1;
550 if (target
->state
!= TARGET_HALTED
)
552 LOG_WARNING("target not halted");
553 return ERROR_TARGET_NOT_HALTED
;
556 if (watchpoint
->rw
== WPT_ACCESS
)
561 if (!arm7_9
->wp0_used
)
563 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], watchpoint
->address
);
564 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], mask
);
565 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], watchpoint
->mask
);
566 if (watchpoint
->mask
!= 0xffffffffu
)
567 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_VALUE
], watchpoint
->value
);
568 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
569 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
571 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
576 arm7_9
->wp0_used
= 2;
578 else if (!arm7_9
->wp1_used
)
580 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], watchpoint
->address
);
581 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], mask
);
582 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], watchpoint
->mask
);
583 if (watchpoint
->mask
!= 0xffffffffu
)
584 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_VALUE
], watchpoint
->value
);
585 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], 0xff & ~EICE_W_CTRL_nOPC
& ~rw_mask
);
586 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
| EICE_W_CTRL_nOPC
| (watchpoint
->rw
& 1));
588 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
593 arm7_9
->wp1_used
= 2;
597 LOG_ERROR("BUG: no hardware comparator available");
605 * Unset an existing watchpoint and clear the used watchpoint unit.
607 * @param target Pointer to the target to have the watchpoint removed
608 * @param watchpoint Pointer to the watchpoint to be removed
609 * @return Error status while trying to unset the watchpoint or the result of
610 * executing the JTAG queue
612 int arm7_9_unset_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
614 int retval
= ERROR_OK
;
615 armv4_5_common_t
*armv4_5
= target
->arch_info
;
616 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
618 if (target
->state
!= TARGET_HALTED
)
620 LOG_WARNING("target not halted");
621 return ERROR_TARGET_NOT_HALTED
;
624 if (!watchpoint
->set
)
626 LOG_WARNING("breakpoint not set");
630 if (watchpoint
->set
== 1)
632 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
633 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
637 arm7_9
->wp0_used
= 0;
639 else if (watchpoint
->set
== 2)
641 embeddedice_set_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
642 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
646 arm7_9
->wp1_used
= 0;
654 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
655 * available, an error response is returned.
657 * @param target Pointer to the ARM7/9 target to add a watchpoint to
658 * @param watchpoint Pointer to the watchpoint to be added
659 * @return Error status while trying to add the watchpoint
661 int arm7_9_add_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
663 armv4_5_common_t
*armv4_5
= target
->arch_info
;
664 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
666 if (target
->state
!= TARGET_HALTED
)
668 LOG_WARNING("target not halted");
669 return ERROR_TARGET_NOT_HALTED
;
672 if (arm7_9
->wp_available
< 1)
674 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
677 if ((watchpoint
->length
!= 1) && (watchpoint
->length
!= 2) && (watchpoint
->length
!= 4))
679 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
682 arm7_9
->wp_available
--;
688 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
689 * the used watchpoint unit will be reopened.
691 * @param target Pointer to the target to remove a watchpoint from
692 * @param watchpoint Pointer to the watchpoint to be removed
693 * @return Result of trying to unset the watchpoint
695 int arm7_9_remove_watchpoint(struct target_s
*target
, watchpoint_t
*watchpoint
)
697 int retval
= ERROR_OK
;
698 armv4_5_common_t
*armv4_5
= target
->arch_info
;
699 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
703 if ((retval
= arm7_9_unset_watchpoint(target
, watchpoint
)) != ERROR_OK
)
709 arm7_9
->wp_available
++;
715 * Restarts the target by sending a RESTART instruction and moving the JTAG
716 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
717 * asserted by the processor.
719 * @param target Pointer to target to issue commands to
720 * @return Error status if there is a timeout or a problem while executing the
723 int arm7_9_execute_sys_speed(struct target_s
*target
)
727 armv4_5_common_t
*armv4_5
= target
->arch_info
;
728 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
729 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
730 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
732 /* set RESTART instruction */
733 jtag_set_end_state(TAP_IDLE
);
734 if (arm7_9
->need_bypass_before_restart
) {
735 arm7_9
->need_bypass_before_restart
= 0;
736 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
738 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
740 long long then
= timeval_ms();
742 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
744 /* read debug status register */
745 embeddedice_read_reg(dbg_stat
);
746 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
748 if ((buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
749 && (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_SYSCOMP
, 1)))
751 if (debug_level
>= 3)
761 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32
"", buf_get_u32(dbg_stat
->value
, 0, dbg_stat
->size
));
762 return ERROR_TARGET_TIMEOUT
;
769 * Restarts the target by sending a RESTART instruction and moving the JTAG
770 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
771 * waiting until they are.
773 * @param target Pointer to the target to issue commands to
774 * @return Always ERROR_OK
776 int arm7_9_execute_fast_sys_speed(struct target_s
*target
)
779 static uint8_t check_value
[4], check_mask
[4];
781 armv4_5_common_t
*armv4_5
= target
->arch_info
;
782 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
783 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
784 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
786 /* set RESTART instruction */
787 jtag_set_end_state(TAP_IDLE
);
788 if (arm7_9
->need_bypass_before_restart
) {
789 arm7_9
->need_bypass_before_restart
= 0;
790 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
792 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
796 /* check for DBGACK and SYSCOMP set (others don't care) */
798 /* NB! These are constants that must be available until after next jtag_execute() and
799 * we evaluate the values upon first execution in lieu of setting up these constants
800 * during early setup.
802 buf_set_u32(check_value
, 0, 32, 0x9);
803 buf_set_u32(check_mask
, 0, 32, 0x9);
807 /* read debug status register */
808 embeddedice_read_reg_w_check(dbg_stat
, check_value
, check_mask
);
814 * Get some data from the ARM7/9 target.
816 * @param target Pointer to the ARM7/9 target to read data from
817 * @param size The number of 32bit words to be read
818 * @param buffer Pointer to the buffer that will hold the data
819 * @return The result of receiving data from the Embedded ICE unit
821 int arm7_9_target_request_data(target_t
*target
, uint32_t size
, uint8_t *buffer
)
823 armv4_5_common_t
*armv4_5
= target
->arch_info
;
824 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
825 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
827 int retval
= ERROR_OK
;
830 data
= malloc(size
* (sizeof(uint32_t)));
832 retval
= embeddedice_receive(jtag_info
, data
, size
);
834 /* return the 32-bit ints in the 8-bit array */
835 for (i
= 0; i
< size
; i
++)
837 h_u32_to_le(buffer
+ (i
* 4), data
[i
]);
846 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
847 * target is running and the DCC control register has the W bit high, this will
848 * execute the request on the target.
850 * @param priv Void pointer expected to be a target_t pointer
851 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
852 * from the Embedded ICE unit
854 int arm7_9_handle_target_request(void *priv
)
856 int retval
= ERROR_OK
;
857 target_t
*target
= priv
;
858 if (!target_was_examined(target
))
860 armv4_5_common_t
*armv4_5
= target
->arch_info
;
861 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
862 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
863 reg_t
*dcc_control
= &arm7_9
->eice_cache
->reg_list
[EICE_COMMS_CTRL
];
865 if (!target
->dbg_msg_enabled
)
868 if (target
->state
== TARGET_RUNNING
)
870 /* read DCC control register */
871 embeddedice_read_reg(dcc_control
);
872 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
878 if (buf_get_u32(dcc_control
->value
, 1, 1) == 1)
882 if ((retval
= embeddedice_receive(jtag_info
, &request
, 1)) != ERROR_OK
)
886 if ((retval
= target_request(target
, request
)) != ERROR_OK
)
897 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
898 * is manipulated to the right halted state based on its current state. This is
902 * <tr><th > State</th><th > Action</th></tr>
903 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
904 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
905 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
906 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
909 * If the target does not end up in the halted state, a warning is produced. If
910 * DBGACK is cleared, then the target is expected to either be running or
913 * @param target Pointer to the ARM7/9 target to poll
914 * @return ERROR_OK or an error status if a command fails
916 int arm7_9_poll(target_t
*target
)
919 armv4_5_common_t
*armv4_5
= target
->arch_info
;
920 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
921 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
923 /* read debug status register */
924 embeddedice_read_reg(dbg_stat
);
925 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
930 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1))
932 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
933 if (target
->state
== TARGET_UNKNOWN
)
935 /* Starting OpenOCD with target in debug-halt */
936 target
->state
= TARGET_RUNNING
;
937 LOG_DEBUG("DBGACK already set during server startup.");
939 if ((target
->state
== TARGET_RUNNING
) || (target
->state
== TARGET_RESET
))
942 if (target
->state
== TARGET_RESET
)
944 if (target
->reset_halt
)
946 enum reset_types jtag_reset_config
= jtag_get_reset_config();
947 if ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) == 0)
954 target
->state
= TARGET_HALTED
;
956 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
961 reg_t
*reg
= register_get_by_name(target
->reg_cache
, "pc", 1);
962 uint32_t t
=*((uint32_t *)reg
->value
);
965 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
969 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
974 if (target
->state
== TARGET_DEBUG_RUNNING
)
976 target
->state
= TARGET_HALTED
;
977 if ((retval
= arm7_9_debug_entry(target
)) != ERROR_OK
)
980 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
)) != ERROR_OK
)
985 if (target
->state
!= TARGET_HALTED
)
987 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target
->state
);
992 if (target
->state
!= TARGET_DEBUG_RUNNING
)
993 target
->state
= TARGET_RUNNING
;
1000 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
1001 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
1002 * affected) completely stop the JTAG clock while the core is held in reset
1003 * (SRST). It isn't possible to program the halt condition once reset is
1004 * asserted, hence a hook that allows the target to set up its reset-halt
1005 * condition is setup prior to asserting reset.
1007 * @param target Pointer to an ARM7/9 target to assert reset on
1008 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
1010 int arm7_9_assert_reset(target_t
*target
)
1012 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1013 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1014 LOG_DEBUG("target->state: %s",
1015 target_state_name(target
));
1017 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1018 if (!(jtag_reset_config
& RESET_HAS_SRST
))
1020 LOG_ERROR("Can't assert SRST");
1024 /* at this point trst has been asserted/deasserted once. We want to
1025 * program embedded ice while SRST is asserted, but some CPUs gate
1026 * the JTAG clock while SRST is asserted
1028 bool srst_asserted
= false;
1029 if (((jtag_reset_config
& RESET_SRST_PULLS_TRST
) == 0) && ((jtag_reset_config
& RESET_SRST_GATES_JTAG
) == 0))
1031 jtag_add_reset(0, 1);
1032 srst_asserted
= true;
1035 if (target
->reset_halt
)
1038 * Some targets do not support communication while SRST is asserted. We need to
1039 * set up the reset vector catch here.
1041 * If TRST is asserted, then these settings will be reset anyway, so setting them
1044 if (arm7_9
->has_vector_catch
)
1046 /* program vector catch register to catch reset vector */
1047 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
], 0x1);
1049 /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
1050 jtag_add_runtest(1, jtag_get_end_state());
1054 /* program watchpoint unit to match on reset vector address */
1055 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
], 0x0);
1056 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0x3);
1057 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1058 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1059 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1063 /* here we should issue an SRST only, but we may have to assert TRST as well */
1064 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
1066 jtag_add_reset(1, 1);
1067 } else if (!srst_asserted
)
1069 jtag_add_reset(0, 1);
1072 target
->state
= TARGET_RESET
;
1073 jtag_add_sleep(50000);
1075 armv4_5_invalidate_core_regs(target
);
1077 if ((target
->reset_halt
) && ((jtag_reset_config
& RESET_SRST_PULLS_TRST
) == 0))
1079 /* debug entry was already prepared in arm7_9_assert_reset() */
1080 target
->debug_reason
= DBG_REASON_DBGRQ
;
1087 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1088 * and the target is being reset into a halt, a warning will be triggered
1089 * because it is not possible to reset into a halted mode in this case. The
1090 * target is halted using the target's functions.
1092 * @param target Pointer to the target to have the reset deasserted
1093 * @return ERROR_OK or an error from polling or halting the target
1095 int arm7_9_deassert_reset(target_t
*target
)
1097 int retval
= ERROR_OK
;
1098 LOG_DEBUG("target->state: %s",
1099 target_state_name(target
));
1101 /* deassert reset lines */
1102 jtag_add_reset(0, 0);
1104 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1105 if (target
->reset_halt
&& (jtag_reset_config
& RESET_SRST_PULLS_TRST
) != 0)
1107 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1108 /* set up embedded ice registers again */
1109 if ((retval
= target_examine_one(target
)) != ERROR_OK
)
1112 if ((retval
= target_poll(target
)) != ERROR_OK
)
1117 if ((retval
= target_halt(target
)) != ERROR_OK
)
1127 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1128 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1129 * vector catch was used, it is restored. Otherwise, the control value is
1130 * restored and the watchpoint unit is restored if it was in use.
1132 * @param target Pointer to the ARM7/9 target to have halt cleared
1133 * @return Always ERROR_OK
1135 int arm7_9_clear_halt(target_t
*target
)
1137 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1138 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1139 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1141 /* we used DBGRQ only if we didn't come out of reset */
1142 if (!arm7_9
->debug_entry_from_reset
&& arm7_9
->use_dbgrq
)
1144 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1146 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1147 embeddedice_store_reg(dbg_ctrl
);
1151 if (arm7_9
->debug_entry_from_reset
&& arm7_9
->has_vector_catch
)
1153 /* if we came out of reset, and vector catch is supported, we used
1154 * vector catch to enter debug state
1155 * restore the register in that case
1157 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
]);
1161 /* restore registers if watchpoint unit 0 was in use
1163 if (arm7_9
->wp0_used
)
1165 if (arm7_9
->debug_entry_from_reset
)
1167 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_VALUE
]);
1169 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
1170 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
1171 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
1173 /* control value always has to be restored, as it was either disabled,
1174 * or enabled with possibly different bits
1176 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
1184 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1185 * and then there is a wait until the processor shows the halt. This wait can
1186 * timeout and results in an error being returned. The software reset involves
1187 * clearing the halt, updating the debug control register, changing to ARM mode,
1188 * reset of the program counter, and reset of all of the registers.
1190 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1191 * @return Error status if any of the commands fail, otherwise ERROR_OK
1193 int arm7_9_soft_reset_halt(struct target_s
*target
)
1195 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1196 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1197 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1198 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1202 /* FIX!!! replace some of this code with tcl commands
1204 * halt # the halt command is synchronous
1205 * armv4_5 core_state arm
1209 if ((retval
= target_halt(target
)) != ERROR_OK
)
1212 long long then
= timeval_ms();
1214 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
1216 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) != 0)
1218 embeddedice_read_reg(dbg_stat
);
1219 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1221 if (debug_level
>= 3)
1231 LOG_ERROR("Failed to halt CPU after 1 sec");
1232 return ERROR_TARGET_TIMEOUT
;
1234 target
->state
= TARGET_HALTED
;
1236 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1237 * ensure that DBGRQ is cleared
1239 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1240 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1241 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1242 embeddedice_store_reg(dbg_ctrl
);
1244 if ((retval
= arm7_9_clear_halt(target
)) != ERROR_OK
)
1249 /* if the target is in Thumb state, change to ARM state */
1250 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1252 uint32_t r0_thumb
, pc_thumb
;
1253 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1254 /* Entered debug from Thumb mode */
1255 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1256 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1259 /* all register content is now invalid */
1260 if ((retval
= armv4_5_invalidate_core_regs(target
)) != ERROR_OK
)
1265 /* SVC, ARM state, IRQ and FIQ disabled */
1266 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
1267 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
1268 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1270 /* start fetching from 0x0 */
1271 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
1272 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
1273 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
1275 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
1276 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1278 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1281 /* reset registers */
1282 for (i
= 0; i
<= 14; i
++)
1284 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, 0xffffffff);
1285 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 1;
1286 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1289 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
1298 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1299 * line or by programming a watchpoint to trigger on any address. It is
1300 * considered a bug to call this function while the target is in the
1301 * TARGET_RESET state.
1303 * @param target Pointer to the ARM7/9 target to be halted
1304 * @return Always ERROR_OK
1306 int arm7_9_halt(target_t
*target
)
1308 if (target
->state
== TARGET_RESET
)
1310 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1314 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1315 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1316 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1318 LOG_DEBUG("target->state: %s",
1319 target_state_name(target
));
1321 if (target
->state
== TARGET_HALTED
)
1323 LOG_DEBUG("target was already halted");
1327 if (target
->state
== TARGET_UNKNOWN
)
1329 LOG_WARNING("target was in unknown state when halt was requested");
1332 if (arm7_9
->use_dbgrq
)
1334 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1336 if (arm7_9
->set_special_dbgrq
) {
1337 arm7_9
->set_special_dbgrq(target
);
1339 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 1);
1340 embeddedice_store_reg(dbg_ctrl
);
1345 /* program watchpoint unit to match on any address
1347 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
1348 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
1349 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
1350 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
1353 target
->debug_reason
= DBG_REASON_DBGRQ
;
1359 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1360 * ARM. The JTAG queue is then executed and the reason for debug entry is
1361 * examined. Once done, the target is verified to be halted and the processor
1362 * is forced into ARM mode. The core registers are saved for the current core
1363 * mode and the program counter (register 15) is updated as needed. The core
1364 * registers and CPSR and SPSR are saved for restoration later.
1366 * @param target Pointer to target that is entering debug mode
1367 * @return Error code if anything fails, otherwise ERROR_OK
1369 int arm7_9_debug_entry(target_t
*target
)
1372 uint32_t context
[16];
1373 uint32_t* context_p
[16];
1374 uint32_t r0_thumb
, pc_thumb
;
1377 /* get pointers to arch-specific information */
1378 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1379 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1380 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
1381 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1383 #ifdef _DEBUG_ARM7_9_
1387 if (arm7_9
->pre_debug_entry
)
1388 arm7_9
->pre_debug_entry(target
);
1390 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1391 * ensure that DBGRQ is cleared
1393 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
1394 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGRQ
, 1, 0);
1395 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 1);
1396 embeddedice_store_reg(dbg_ctrl
);
1398 if ((retval
= arm7_9_clear_halt(target
)) != ERROR_OK
)
1403 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1408 if ((retval
= arm7_9
->examine_debug_reason(target
)) != ERROR_OK
)
1412 if (target
->state
!= TARGET_HALTED
)
1414 LOG_WARNING("target not halted");
1415 return ERROR_TARGET_NOT_HALTED
;
1418 /* if the target is in Thumb state, change to ARM state */
1419 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_ITBIT
, 1))
1421 LOG_DEBUG("target entered debug from Thumb state");
1422 /* Entered debug from Thumb mode */
1423 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
1424 arm7_9
->change_to_arm(target
, &r0_thumb
, &pc_thumb
);
1425 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
", pc_thumb: 0x%8.8" PRIx32
"", r0_thumb
, pc_thumb
);
1429 LOG_DEBUG("target entered debug from ARM state");
1430 /* Entered debug from ARM mode */
1431 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
1434 for (i
= 0; i
< 16; i
++)
1435 context_p
[i
] = &context
[i
];
1436 /* save core registers (r0 - r15 of current core mode) */
1437 arm7_9
->read_core_regs(target
, 0xffff, context_p
);
1439 arm7_9
->read_xpsr(target
, &cpsr
, 0);
1441 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1444 /* if the core has been executing in Thumb state, set the T bit */
1445 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1448 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, cpsr
);
1449 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1450 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1452 armv4_5
->core_mode
= cpsr
& 0x1f;
1454 if (armv4_5_mode_to_number(armv4_5
->core_mode
) == -1)
1456 target
->state
= TARGET_UNKNOWN
;
1457 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1458 return ERROR_TARGET_FAILURE
;
1461 LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)]);
1463 if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1465 LOG_DEBUG("thumb state, applying fixups");
1466 context
[0] = r0_thumb
;
1467 context
[15] = pc_thumb
;
1468 } else if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1470 /* adjust value stored by STM */
1471 context
[15] -= 3 * 4;
1474 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
) || (!arm7_9
->use_dbgrq
))
1475 context
[15] -= 3 * ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1477 context
[15] -= arm7_9
->dbgreq_adjust_pc
* ((armv4_5
->core_state
== ARMV4_5_STATE_ARM
) ? 4 : 2);
1479 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1482 for (i
= 0; i
<= 15; i
++)
1484 LOG_DEBUG("r%i: 0x%8.8" PRIx32
"", i
, context
[i
]);
1485 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).value
, 0, 32, context
[i
]);
1486 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= 0;
1487 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
= 1;
1490 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
"", context
[15]);
1492 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1495 /* exceptions other than USR & SYS have a saved program status register */
1496 if ((armv4_5
->core_mode
!= ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_SYS
))
1499 arm7_9
->read_xpsr(target
, &spsr
, 1);
1500 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1504 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).value
, 0, 32, spsr
);
1505 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).dirty
= 0;
1506 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 16).valid
= 1;
1509 /* r0 and r15 (pc) have to be restored later */
1510 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1511 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 15).valid
;
1513 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1516 if (arm7_9
->post_debug_entry
)
1517 arm7_9
->post_debug_entry(target
);
1523 * Validate the full context for an ARM7/9 target in all processor modes. If
1524 * there are any invalid registers for the target, they will all be read. This
1527 * @param target Pointer to the ARM7/9 target to capture the full context from
1528 * @return Error if the target is not halted, has an invalid core mode, or if
1529 * the JTAG queue fails to execute
1531 int arm7_9_full_context(target_t
*target
)
1535 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1536 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1540 if (target
->state
!= TARGET_HALTED
)
1542 LOG_WARNING("target not halted");
1543 return ERROR_TARGET_NOT_HALTED
;
1546 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1549 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1550 * SYS shares registers with User, so we don't touch SYS
1552 for (i
= 0; i
< 6; i
++)
1555 uint32_t* reg_p
[16];
1559 /* check if there are invalid registers in the current mode
1561 for (j
= 0; j
<= 16; j
++)
1563 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1571 /* change processor mode (and mask T bit) */
1572 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1573 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1575 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1577 for (j
= 0; j
< 15; j
++)
1579 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
== 0)
1581 reg_p
[j
] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).value
;
1583 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).valid
= 1;
1584 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
).dirty
= 0;
1588 /* if only the PSR is invalid, mask is all zeroes */
1590 arm7_9
->read_core_regs(target
, mask
, reg_p
);
1592 /* check if the PSR has to be read */
1593 if (ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
== 0)
1595 arm7_9
->read_xpsr(target
, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).value
, 1);
1596 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).valid
= 1;
1597 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16).dirty
= 0;
1602 /* restore processor mode (mask T bit) */
1603 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
1605 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1613 * Restore the processor context on an ARM7/9 target. The full processor
1614 * context is analyzed to see if any of the registers are dirty on this end, but
1615 * have a valid new value. If this is the case, the processor is changed to the
1616 * appropriate mode and the new register values are written out to the
1617 * processor. If there happens to be a dirty register with an invalid value, an
1618 * error will be logged.
1620 * @param target Pointer to the ARM7/9 target to have its context restored
1621 * @return Error status if the target is not halted or the core mode in the
1622 * armv4_5 struct is invalid.
1624 int arm7_9_restore_context(target_t
*target
)
1626 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1627 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1629 armv4_5_core_reg_t
*reg_arch_info
;
1630 enum armv4_5_mode current_mode
= armv4_5
->core_mode
;
1637 if (target
->state
!= TARGET_HALTED
)
1639 LOG_WARNING("target not halted");
1640 return ERROR_TARGET_NOT_HALTED
;
1643 if (arm7_9
->pre_restore_context
)
1644 arm7_9
->pre_restore_context(target
);
1646 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1649 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1650 * SYS shares registers with User, so we don't touch SYS
1652 for (i
= 0; i
< 6; i
++)
1654 LOG_DEBUG("examining %s mode", armv4_5_mode_strings
[i
]);
1657 /* check if there are dirty registers in the current mode
1659 for (j
= 0; j
<= 16; j
++)
1661 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1662 reg_arch_info
= reg
->arch_info
;
1663 if (reg
->dirty
== 1)
1665 if (reg
->valid
== 1)
1668 LOG_DEBUG("examining dirty reg: %s", reg
->name
);
1669 if ((reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
)
1670 && (reg_arch_info
->mode
!= current_mode
)
1671 && !((reg_arch_info
->mode
== ARMV4_5_MODE_USR
) && (armv4_5
->core_mode
== ARMV4_5_MODE_SYS
))
1672 && !((reg_arch_info
->mode
== ARMV4_5_MODE_SYS
) && (armv4_5
->core_mode
== ARMV4_5_MODE_USR
)))
1675 LOG_DEBUG("require mode change");
1680 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg
->name
);
1687 uint32_t mask
= 0x0;
1695 /* change processor mode (mask T bit) */
1696 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1697 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1699 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1700 current_mode
= armv4_5_number_to_mode(i
);
1703 for (j
= 0; j
<= 14; j
++)
1705 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), j
);
1706 reg_arch_info
= reg
->arch_info
;
1709 if (reg
->dirty
== 1)
1711 regs
[j
] = buf_get_u32(reg
->value
, 0, 32);
1716 LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32
"", j
, armv4_5_mode_strings
[i
], regs
[j
]);
1722 arm7_9
->write_core_regs(target
, mask
, regs
);
1725 reg
= &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_number_to_mode(i
), 16);
1726 reg_arch_info
= reg
->arch_info
;
1727 if ((reg
->dirty
) && (reg_arch_info
->mode
!= ARMV4_5_MODE_ANY
))
1729 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32
"", i
, buf_get_u32(reg
->value
, 0, 32));
1730 arm7_9
->write_xpsr(target
, buf_get_u32(reg
->value
, 0, 32), 1);
1735 if ((armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 0) && (armv4_5
->core_mode
!= current_mode
))
1737 /* restore processor mode (mask T bit) */
1740 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
1741 tmp_cpsr
|= armv4_5_number_to_mode(i
);
1743 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr
));
1744 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
1746 else if (armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
== 1)
1748 /* CPSR has been changed, full restore necessary (mask T bit) */
1749 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32));
1750 arm7_9
->write_xpsr(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32) & ~0x20, 0);
1751 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 0;
1752 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
1756 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1757 arm7_9
->write_pc(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1758 armv4_5
->core_cache
->reg_list
[15].dirty
= 0;
1760 if (arm7_9
->post_restore_context
)
1761 arm7_9
->post_restore_context(target
);
1767 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1768 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1771 * @param target Pointer to the ARM7/9 target to be restarted
1772 * @return Result of executing the JTAG queue
1774 int arm7_9_restart_core(struct target_s
*target
)
1776 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1777 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1778 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
1780 /* set RESTART instruction */
1781 jtag_set_end_state(TAP_IDLE
);
1782 if (arm7_9
->need_bypass_before_restart
) {
1783 arm7_9
->need_bypass_before_restart
= 0;
1784 arm_jtag_set_instr(jtag_info
, 0xf, NULL
);
1786 arm_jtag_set_instr(jtag_info
, 0x4, NULL
);
1788 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE
));
1789 return jtag_execute_queue();
1793 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1794 * iterated through and are set on the target if they aren't already set.
1796 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1798 void arm7_9_enable_watchpoints(struct target_s
*target
)
1800 watchpoint_t
*watchpoint
= target
->watchpoints
;
1804 if (watchpoint
->set
== 0)
1805 arm7_9_set_watchpoint(target
, watchpoint
);
1806 watchpoint
= watchpoint
->next
;
1811 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1812 * iterated through and are set on the target.
1814 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1816 void arm7_9_enable_breakpoints(struct target_s
*target
)
1818 breakpoint_t
*breakpoint
= target
->breakpoints
;
1820 /* set any pending breakpoints */
1823 arm7_9_set_breakpoint(target
, breakpoint
);
1824 breakpoint
= breakpoint
->next
;
1828 int arm7_9_resume(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
, int debug_execution
)
1830 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1831 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1832 breakpoint_t
*breakpoint
= target
->breakpoints
;
1833 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
1834 int err
, retval
= ERROR_OK
;
1838 if (target
->state
!= TARGET_HALTED
)
1840 LOG_WARNING("target not halted");
1841 return ERROR_TARGET_NOT_HALTED
;
1844 if (!debug_execution
)
1846 target_free_all_working_areas(target
);
1849 /* current = 1: continue on current pc, otherwise continue at <address> */
1851 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
1853 uint32_t current_pc
;
1854 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1856 /* the front-end may request us not to handle breakpoints */
1857 if (handle_breakpoints
)
1859 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
1861 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (id: %d)", breakpoint
->address
, breakpoint
->unique_id
);
1862 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1867 /* calculate PC of next instruction */
1869 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
1871 uint32_t current_opcode
;
1872 target_read_u32(target
, current_pc
, ¤t_opcode
);
1873 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
1877 LOG_DEBUG("enable single-step");
1878 arm7_9
->enable_single_step(target
, next_pc
);
1880 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1882 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
1887 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1888 arm7_9
->branch_resume(target
);
1889 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1891 arm7_9
->branch_resume_thumb(target
);
1895 LOG_ERROR("unhandled core state");
1899 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1900 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1901 err
= arm7_9_execute_sys_speed(target
);
1903 LOG_DEBUG("disable single-step");
1904 arm7_9
->disable_single_step(target
);
1906 if (err
!= ERROR_OK
)
1908 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1912 target
->state
= TARGET_UNKNOWN
;
1916 arm7_9_debug_entry(target
);
1917 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32
"", buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
1919 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32
"", breakpoint
->address
);
1920 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
1927 /* enable any pending breakpoints and watchpoints */
1928 arm7_9_enable_breakpoints(target
);
1929 arm7_9_enable_watchpoints(target
);
1931 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
1936 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
1938 arm7_9
->branch_resume(target
);
1940 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
1942 arm7_9
->branch_resume_thumb(target
);
1946 LOG_ERROR("unhandled core state");
1950 /* deassert DBGACK and INTDIS */
1951 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
1952 /* INTDIS only when we really resume, not during debug execution */
1953 if (!debug_execution
)
1954 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_INTDIS
, 1, 0);
1955 embeddedice_write_reg(dbg_ctrl
, buf_get_u32(dbg_ctrl
->value
, 0, dbg_ctrl
->size
));
1957 if ((retval
= arm7_9_restart_core(target
)) != ERROR_OK
)
1962 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1964 if (!debug_execution
)
1966 /* registers are now invalid */
1967 armv4_5_invalidate_core_regs(target
);
1968 target
->state
= TARGET_RUNNING
;
1969 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
1976 target
->state
= TARGET_DEBUG_RUNNING
;
1977 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
)) != ERROR_OK
)
1983 LOG_DEBUG("target resumed");
1988 void arm7_9_enable_eice_step(target_t
*target
, uint32_t next_pc
)
1990 armv4_5_common_t
*armv4_5
= target
->arch_info
;
1991 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
1993 uint32_t current_pc
;
1994 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
1996 if (next_pc
!= current_pc
)
1998 /* setup an inverse breakpoint on the current PC
1999 * - comparator 1 matches the current address
2000 * - rangeout from comparator 1 is connected to comparator 0 rangein
2001 * - comparator 0 matches any address, as long as rangein is low */
2002 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
2003 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
2004 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
2005 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], ~(EICE_W_CTRL_RANGE
| EICE_W_CTRL_nOPC
) & 0xff);
2006 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], current_pc
);
2007 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
2008 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
2009 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], 0x0);
2010 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
2014 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
], 0xffffffff);
2015 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
], 0xffffffff);
2016 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
], 0x0);
2017 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
], 0xff);
2018 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
], next_pc
);
2019 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
], 0);
2020 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
], 0xffffffff);
2021 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
], EICE_W_CTRL_ENABLE
);
2022 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
], ~EICE_W_CTRL_nOPC
& 0xff);
2026 void arm7_9_disable_eice_step(target_t
*target
)
2028 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2029 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2031 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_ADDR_MASK
]);
2032 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_DATA_MASK
]);
2033 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_VALUE
]);
2034 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W0_CONTROL_MASK
]);
2035 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_VALUE
]);
2036 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_ADDR_MASK
]);
2037 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_DATA_MASK
]);
2038 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_MASK
]);
2039 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_W1_CONTROL_VALUE
]);
2042 int arm7_9_step(struct target_s
*target
, int current
, uint32_t address
, int handle_breakpoints
)
2044 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2045 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2046 breakpoint_t
*breakpoint
= NULL
;
2049 if (target
->state
!= TARGET_HALTED
)
2051 LOG_WARNING("target not halted");
2052 return ERROR_TARGET_NOT_HALTED
;
2055 /* current = 1: continue on current pc, otherwise continue at <address> */
2057 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, address
);
2059 uint32_t current_pc
;
2060 current_pc
= buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32);
2062 /* the front-end may request us not to handle breakpoints */
2063 if (handle_breakpoints
)
2064 if ((breakpoint
= breakpoint_find(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32))))
2065 if ((retval
= arm7_9_unset_breakpoint(target
, breakpoint
)) != ERROR_OK
)
2070 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
2072 /* calculate PC of next instruction */
2074 if ((retval
= arm_simulate_step(target
, &next_pc
)) != ERROR_OK
)
2076 uint32_t current_opcode
;
2077 target_read_u32(target
, current_pc
, ¤t_opcode
);
2078 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32
"", current_opcode
);
2082 if ((retval
= arm7_9_restore_context(target
)) != ERROR_OK
)
2087 arm7_9
->enable_single_step(target
, next_pc
);
2089 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
2091 arm7_9
->branch_resume(target
);
2093 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
2095 arm7_9
->branch_resume_thumb(target
);
2099 LOG_ERROR("unhandled core state");
2103 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
)) != ERROR_OK
)
2108 err
= arm7_9_execute_sys_speed(target
);
2109 arm7_9
->disable_single_step(target
);
2111 /* registers are now invalid */
2112 armv4_5_invalidate_core_regs(target
);
2114 if (err
!= ERROR_OK
)
2116 target
->state
= TARGET_UNKNOWN
;
2118 arm7_9_debug_entry(target
);
2119 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
2123 LOG_DEBUG("target stepped");
2127 if ((retval
= arm7_9_set_breakpoint(target
, breakpoint
)) != ERROR_OK
)
2135 int arm7_9_read_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
)
2137 uint32_t* reg_p
[16];
2140 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2141 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2143 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2146 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
2148 if ((num
< 0) || (num
> 16))
2149 return ERROR_INVALID_ARGUMENTS
;
2151 if ((mode
!= ARMV4_5_MODE_ANY
)
2152 && (mode
!= armv4_5
->core_mode
)
2153 && (reg_mode
!= ARMV4_5_MODE_ANY
))
2157 /* change processor mode (mask T bit) */
2158 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
2161 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
2164 if ((num
>= 0) && (num
<= 15))
2166 /* read a normal core register */
2167 reg_p
[num
] = &value
;
2169 arm7_9
->read_core_regs(target
, 1 << num
, reg_p
);
2173 /* read a program status register
2174 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2176 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
2177 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
2179 arm7_9
->read_xpsr(target
, &value
, spsr
);
2182 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2187 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
2188 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
2189 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).value
, 0, 32, value
);
2191 if ((mode
!= ARMV4_5_MODE_ANY
)
2192 && (mode
!= armv4_5
->core_mode
)
2193 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
2194 /* restore processor mode (mask T bit) */
2195 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2201 int arm7_9_write_core_reg(struct target_s
*target
, int num
, enum armv4_5_mode mode
, uint32_t value
)
2204 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2205 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2207 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2210 enum armv4_5_mode reg_mode
= ((armv4_5_core_reg_t
*)ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
)->mode
;
2212 if ((num
< 0) || (num
> 16))
2213 return ERROR_INVALID_ARGUMENTS
;
2215 if ((mode
!= ARMV4_5_MODE_ANY
)
2216 && (mode
!= armv4_5
->core_mode
)
2217 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
2220 /* change processor mode (mask T bit) */
2221 tmp_cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & 0xE0;
2224 arm7_9
->write_xpsr_im8(target
, tmp_cpsr
& 0xff, 0, 0);
2227 if ((num
>= 0) && (num
<= 15))
2229 /* write a normal core register */
2232 arm7_9
->write_core_regs(target
, 1 << num
, reg
);
2236 /* write a program status register
2237 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2239 armv4_5_core_reg_t
*arch_info
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).arch_info
;
2240 int spsr
= (arch_info
->mode
== ARMV4_5_MODE_ANY
) ? 0 : 1;
2242 /* if we're writing the CPSR, mask the T bit */
2246 arm7_9
->write_xpsr(target
, value
, spsr
);
2249 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).valid
= 1;
2250 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, mode
, num
).dirty
= 0;
2252 if ((mode
!= ARMV4_5_MODE_ANY
)
2253 && (mode
!= armv4_5
->core_mode
)
2254 && (reg_mode
!= ARMV4_5_MODE_ANY
)) {
2255 /* restore processor mode (mask T bit) */
2256 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2259 return jtag_execute_queue();
2262 int arm7_9_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
2264 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2265 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2268 uint32_t num_accesses
= 0;
2269 int thisrun_accesses
;
2275 LOG_DEBUG("address: 0x%8.8" PRIx32
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"", address
, size
, count
);
2277 if (target
->state
!= TARGET_HALTED
)
2279 LOG_WARNING("target not halted");
2280 return ERROR_TARGET_NOT_HALTED
;
2283 /* sanitize arguments */
2284 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2285 return ERROR_INVALID_ARGUMENTS
;
2287 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2288 return ERROR_TARGET_UNALIGNED_ACCESS
;
2290 /* load the base register with the address of the first word */
2292 arm7_9
->write_core_regs(target
, 0x1, reg
);
2299 while (num_accesses
< count
)
2302 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2303 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2305 if (last_reg
<= thisrun_accesses
)
2306 last_reg
= thisrun_accesses
;
2308 arm7_9
->load_word_regs(target
, reg_list
);
2310 /* fast memory reads are only safe when the target is running
2311 * from a sufficiently high clock (32 kHz is usually too slow)
2313 if (arm7_9
->fast_memory_access
)
2314 retval
= arm7_9_execute_fast_sys_speed(target
);
2316 retval
= arm7_9_execute_sys_speed(target
);
2317 if (retval
!= ERROR_OK
)
2320 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 4);
2322 /* advance buffer, count number of accesses */
2323 buffer
+= thisrun_accesses
* 4;
2324 num_accesses
+= thisrun_accesses
;
2326 if ((j
++%1024) == 0)
2333 while (num_accesses
< count
)
2336 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2337 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2339 for (i
= 1; i
<= thisrun_accesses
; i
++)
2343 arm7_9
->load_hword_reg(target
, i
);
2344 /* fast memory reads are only safe when the target is running
2345 * from a sufficiently high clock (32 kHz is usually too slow)
2347 if (arm7_9
->fast_memory_access
)
2348 retval
= arm7_9_execute_fast_sys_speed(target
);
2350 retval
= arm7_9_execute_sys_speed(target
);
2351 if (retval
!= ERROR_OK
)
2358 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 2);
2360 /* advance buffer, count number of accesses */
2361 buffer
+= thisrun_accesses
* 2;
2362 num_accesses
+= thisrun_accesses
;
2364 if ((j
++%1024) == 0)
2371 while (num_accesses
< count
)
2374 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2375 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2377 for (i
= 1; i
<= thisrun_accesses
; i
++)
2381 arm7_9
->load_byte_reg(target
, i
);
2382 /* fast memory reads are only safe when the target is running
2383 * from a sufficiently high clock (32 kHz is usually too slow)
2385 if (arm7_9
->fast_memory_access
)
2386 retval
= arm7_9_execute_fast_sys_speed(target
);
2388 retval
= arm7_9_execute_sys_speed(target
);
2389 if (retval
!= ERROR_OK
)
2395 arm7_9
->read_core_regs_target_buffer(target
, reg_list
, buffer
, 1);
2397 /* advance buffer, count number of accesses */
2398 buffer
+= thisrun_accesses
* 1;
2399 num_accesses
+= thisrun_accesses
;
2401 if ((j
++%1024) == 0)
2408 LOG_ERROR("BUG: we shouldn't get here");
2413 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2416 for (i
= 0; i
<= last_reg
; i
++)
2417 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
2419 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2420 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2422 LOG_ERROR("JTAG error while reading cpsr");
2423 return ERROR_TARGET_DATA_ABORT
;
2426 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
2428 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32
", size: 0x%" PRIx32
", count: 0x%" PRIx32
")", address
, size
, count
);
2430 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2432 return ERROR_TARGET_DATA_ABORT
;
2438 int arm7_9_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
2440 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2441 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2442 reg_t
*dbg_ctrl
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
];
2445 uint32_t num_accesses
= 0;
2446 int thisrun_accesses
;
2452 #ifdef _DEBUG_ARM7_9_
2453 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address
, size
, count
);
2456 if (target
->state
!= TARGET_HALTED
)
2458 LOG_WARNING("target not halted");
2459 return ERROR_TARGET_NOT_HALTED
;
2462 /* sanitize arguments */
2463 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
2464 return ERROR_INVALID_ARGUMENTS
;
2466 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2467 return ERROR_TARGET_UNALIGNED_ACCESS
;
2469 /* load the base register with the address of the first word */
2471 arm7_9
->write_core_regs(target
, 0x1, reg
);
2473 /* Clear DBGACK, to make sure memory fetches work as expected */
2474 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 0);
2475 embeddedice_store_reg(dbg_ctrl
);
2480 while (num_accesses
< count
)
2483 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2484 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2486 for (i
= 1; i
<= thisrun_accesses
; i
++)
2490 reg
[i
] = target_buffer_get_u32(target
, buffer
);
2494 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2496 arm7_9
->store_word_regs(target
, reg_list
);
2498 /* fast memory writes are only safe when the target is running
2499 * from a sufficiently high clock (32 kHz is usually too slow)
2501 if (arm7_9
->fast_memory_access
)
2502 retval
= arm7_9_execute_fast_sys_speed(target
);
2504 retval
= arm7_9_execute_sys_speed(target
);
2505 if (retval
!= ERROR_OK
)
2510 num_accesses
+= thisrun_accesses
;
2514 while (num_accesses
< count
)
2517 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2518 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2520 for (i
= 1; i
<= thisrun_accesses
; i
++)
2524 reg
[i
] = target_buffer_get_u16(target
, buffer
) & 0xffff;
2528 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2530 for (i
= 1; i
<= thisrun_accesses
; i
++)
2532 arm7_9
->store_hword_reg(target
, i
);
2534 /* fast memory writes are only safe when the target is running
2535 * from a sufficiently high clock (32 kHz is usually too slow)
2537 if (arm7_9
->fast_memory_access
)
2538 retval
= arm7_9_execute_fast_sys_speed(target
);
2540 retval
= arm7_9_execute_sys_speed(target
);
2541 if (retval
!= ERROR_OK
)
2547 num_accesses
+= thisrun_accesses
;
2551 while (num_accesses
< count
)
2554 thisrun_accesses
= ((count
- num_accesses
) >= 14) ? 14 : (count
- num_accesses
);
2555 reg_list
= (0xffff >> (15 - thisrun_accesses
)) & 0xfffe;
2557 for (i
= 1; i
<= thisrun_accesses
; i
++)
2561 reg
[i
] = *buffer
++ & 0xff;
2564 arm7_9
->write_core_regs(target
, reg_list
, reg
);
2566 for (i
= 1; i
<= thisrun_accesses
; i
++)
2568 arm7_9
->store_byte_reg(target
, i
);
2569 /* fast memory writes are only safe when the target is running
2570 * from a sufficiently high clock (32 kHz is usually too slow)
2572 if (arm7_9
->fast_memory_access
)
2573 retval
= arm7_9_execute_fast_sys_speed(target
);
2575 retval
= arm7_9_execute_sys_speed(target
);
2576 if (retval
!= ERROR_OK
)
2583 num_accesses
+= thisrun_accesses
;
2587 LOG_ERROR("BUG: we shouldn't get here");
2593 buf_set_u32(dbg_ctrl
->value
, EICE_DBG_CONTROL_DBGACK
, 1, 1);
2594 embeddedice_store_reg(dbg_ctrl
);
2596 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
2599 for (i
= 0; i
<= last_reg
; i
++)
2600 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
).valid
;
2602 arm7_9
->read_xpsr(target
, &cpsr
, 0);
2603 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2605 LOG_ERROR("JTAG error while reading cpsr");
2606 return ERROR_TARGET_DATA_ABORT
;
2609 if (((cpsr
& 0x1f) == ARMV4_5_MODE_ABT
) && (armv4_5
->core_mode
!= ARMV4_5_MODE_ABT
))
2611 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32
", size: 0x%" PRIx32
", count: 0x%" PRIx32
")", address
, size
, count
);
2613 arm7_9
->write_xpsr_im8(target
, buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8) & ~0x20, 0, 0);
2615 return ERROR_TARGET_DATA_ABORT
;
2621 static int dcc_count
;
2622 static uint8_t *dcc_buffer
;
2624 static int arm7_9_dcc_completion(struct target_s
*target
, uint32_t exit_point
, int timeout_ms
, void *arch_info
)
2626 int retval
= ERROR_OK
;
2627 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2628 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2630 if ((retval
= target_wait_state(target
, TARGET_DEBUG_RUNNING
, 500)) != ERROR_OK
)
2633 int little
= target
->endianness
== TARGET_LITTLE_ENDIAN
;
2634 int count
= dcc_count
;
2635 uint8_t *buffer
= dcc_buffer
;
2638 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2639 * core function repeated. */
2640 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2643 embeddedice_reg_t
*ice_reg
= arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
].arch_info
;
2644 uint8_t reg_addr
= ice_reg
->addr
& 0x1f;
2646 tap
= ice_reg
->jtag_info
->tap
;
2648 embeddedice_write_dcc(tap
, reg_addr
, buffer
, little
, count
-2);
2649 buffer
+= (count
-2)*4;
2651 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2655 for (i
= 0; i
< count
; i
++)
2657 embeddedice_write_reg(&arm7_9
->eice_cache
->reg_list
[EICE_COMMS_DATA
], fast_target_buffer_get_u32(buffer
, little
));
2662 if ((retval
= target_halt(target
))!= ERROR_OK
)
2666 return target_wait_state(target
, TARGET_HALTED
, 500);
2669 static const uint32_t dcc_code
[] =
2671 /* r0 == input, points to memory buffer
2675 /* spin until DCC control (c0) reports data arrived */
2676 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2677 0xe3110001, /* tst r1, #1 */
2678 0x0afffffc, /* bne w */
2680 /* read word from DCC (c1), write to memory */
2681 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2682 0xe4801004, /* str r1, [r0], #4 */
2685 0xeafffff9 /* b w */
2688 int armv4_5_run_algorithm_inner(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
, int (*run_it
)(struct target_s
*target
, uint32_t exit_point
, int timeout_ms
, void *arch_info
));
2690 int arm7_9_bulk_write_memory(target_t
*target
, uint32_t address
, uint32_t count
, uint8_t *buffer
)
2693 armv4_5_common_t
*armv4_5
= target
->arch_info
;
2694 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
2697 if (!arm7_9
->dcc_downloads
)
2698 return target_write_memory(target
, address
, 4, count
, buffer
);
2700 /* regrab previously allocated working_area, or allocate a new one */
2701 if (!arm7_9
->dcc_working_area
)
2703 uint8_t dcc_code_buf
[6 * 4];
2705 /* make sure we have a working area */
2706 if (target_alloc_working_area(target
, 24, &arm7_9
->dcc_working_area
) != ERROR_OK
)
2708 LOG_INFO("no working area available, falling back to memory writes");
2709 return target_write_memory(target
, address
, 4, count
, buffer
);
2712 /* copy target instructions to target endianness */
2713 for (i
= 0; i
< 6; i
++)
2715 target_buffer_set_u32(target
, dcc_code_buf
+ i
*4, dcc_code
[i
]);
2718 /* write DCC code to working area */
2719 if ((retval
= target_write_memory(target
, arm7_9
->dcc_working_area
->address
, 4, 6, dcc_code_buf
)) != ERROR_OK
)
2725 armv4_5_algorithm_t armv4_5_info
;
2726 reg_param_t reg_params
[1];
2728 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2729 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2730 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2732 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
2734 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2737 dcc_buffer
= buffer
;
2738 retval
= armv4_5_run_algorithm_inner(target
, 0, NULL
, 1, reg_params
,
2739 arm7_9
->dcc_working_area
->address
, arm7_9
->dcc_working_area
->address
+ 6*4, 20*1000, &armv4_5_info
, arm7_9_dcc_completion
);
2741 if (retval
== ERROR_OK
)
2743 uint32_t endaddress
= buf_get_u32(reg_params
[0].value
, 0, 32);
2744 if (endaddress
!= (address
+ count
*4))
2746 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32
" got 0x%0" PRIx32
"", (address
+ count
*4), endaddress
);
2747 retval
= ERROR_FAIL
;
2751 destroy_reg_param(®_params
[0]);
2756 int arm7_9_checksum_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint32_t* checksum
)
2758 working_area_t
*crc_algorithm
;
2759 armv4_5_algorithm_t armv4_5_info
;
2760 reg_param_t reg_params
[2];
2763 static const uint32_t arm7_9_crc_code
[] = {
2764 0xE1A02000, /* mov r2, r0 */
2765 0xE3E00000, /* mov r0, #0xffffffff */
2766 0xE1A03001, /* mov r3, r1 */
2767 0xE3A04000, /* mov r4, #0 */
2768 0xEA00000B, /* b ncomp */
2770 0xE7D21004, /* ldrb r1, [r2, r4] */
2771 0xE59F7030, /* ldr r7, CRC32XOR */
2772 0xE0200C01, /* eor r0, r0, r1, asl 24 */
2773 0xE3A05000, /* mov r5, #0 */
2775 0xE3500000, /* cmp r0, #0 */
2776 0xE1A06080, /* mov r6, r0, asl #1 */
2777 0xE2855001, /* add r5, r5, #1 */
2778 0xE1A00006, /* mov r0, r6 */
2779 0xB0260007, /* eorlt r0, r6, r7 */
2780 0xE3550008, /* cmp r5, #8 */
2781 0x1AFFFFF8, /* bne loop */
2782 0xE2844001, /* add r4, r4, #1 */
2784 0xE1540003, /* cmp r4, r3 */
2785 0x1AFFFFF1, /* bne nbyte */
2787 0xEAFFFFFE, /* b end */
2788 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
2793 if (target_alloc_working_area(target
, sizeof(arm7_9_crc_code
), &crc_algorithm
) != ERROR_OK
)
2795 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2798 /* convert flash writing code into a buffer in target endianness */
2799 for (i
= 0; i
< (sizeof(arm7_9_crc_code
)/sizeof(uint32_t)); i
++)
2801 if ((retval
= target_write_u32(target
, crc_algorithm
->address
+ i
*sizeof(uint32_t), arm7_9_crc_code
[i
])) != ERROR_OK
)
2807 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2808 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2809 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2811 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
2812 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2814 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2815 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
2817 if ((retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
2818 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(arm7_9_crc_code
) - 8), 20000, &armv4_5_info
)) != ERROR_OK
)
2820 LOG_ERROR("error executing arm7_9 crc algorithm");
2821 destroy_reg_param(®_params
[0]);
2822 destroy_reg_param(®_params
[1]);
2823 target_free_working_area(target
, crc_algorithm
);
2827 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
2829 destroy_reg_param(®_params
[0]);
2830 destroy_reg_param(®_params
[1]);
2832 target_free_working_area(target
, crc_algorithm
);
2837 int arm7_9_blank_check_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint32_t* blank
)
2839 working_area_t
*erase_check_algorithm
;
2840 reg_param_t reg_params
[3];
2841 armv4_5_algorithm_t armv4_5_info
;
2845 static const uint32_t erase_check_code
[] =
2848 0xe4d03001, /* ldrb r3, [r0], #1 */
2849 0xe0022003, /* and r2, r2, r3 */
2850 0xe2511001, /* subs r1, r1, #1 */
2851 0x1afffffb, /* bne loop */
2853 0xeafffffe /* b end */
2856 /* make sure we have a working area */
2857 if (target_alloc_working_area(target
, sizeof(erase_check_code
), &erase_check_algorithm
) != ERROR_OK
)
2859 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2862 /* convert flash writing code into a buffer in target endianness */
2863 for (i
= 0; i
< (sizeof(erase_check_code
)/sizeof(uint32_t)); i
++)
2864 if ((retval
= target_write_u32(target
, erase_check_algorithm
->address
+ i
*sizeof(uint32_t), erase_check_code
[i
])) != ERROR_OK
)
2869 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2870 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2871 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2873 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
2874 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2876 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2877 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
2879 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
2880 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
2882 if ((retval
= target_run_algorithm(target
, 0, NULL
, 3, reg_params
,
2883 erase_check_algorithm
->address
, erase_check_algorithm
->address
+ (sizeof(erase_check_code
) - 4), 10000, &armv4_5_info
)) != ERROR_OK
)
2885 destroy_reg_param(®_params
[0]);
2886 destroy_reg_param(®_params
[1]);
2887 destroy_reg_param(®_params
[2]);
2888 target_free_working_area(target
, erase_check_algorithm
);
2892 *blank
= buf_get_u32(reg_params
[2].value
, 0, 32);
2894 destroy_reg_param(®_params
[0]);
2895 destroy_reg_param(®_params
[1]);
2896 destroy_reg_param(®_params
[2]);
2898 target_free_working_area(target
, erase_check_algorithm
);
2903 int arm7_9_register_commands(struct command_context_s
*cmd_ctx
)
2905 command_t
*arm7_9_cmd
;
2907 arm7_9_cmd
= register_command(cmd_ctx
, NULL
, "arm7_9", NULL
, COMMAND_ANY
, "arm7/9 specific commands");
2909 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr", handle_arm7_9_write_xpsr_command
, COMMAND_EXEC
, "write program status register <value> <not cpsr | spsr>");
2910 register_command(cmd_ctx
, arm7_9_cmd
, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command
, COMMAND_EXEC
, "write program status register <8bit immediate> <rotate> <not cpsr | spsr>");
2912 register_command(cmd_ctx
, arm7_9_cmd
, "write_core_reg", handle_arm7_9_write_core_reg_command
, COMMAND_EXEC
, "write core register <num> <mode> <value>");
2914 register_command(cmd_ctx
, arm7_9_cmd
, "dbgrq", handle_arm7_9_dbgrq_command
,
2915 COMMAND_ANY
, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable | disable>");
2916 register_command(cmd_ctx
, arm7_9_cmd
, "fast_memory_access", handle_arm7_9_fast_memory_access_command
,
2917 COMMAND_ANY
, "use fast memory accesses instead of slower but potentially safer accesses <enable | disable>");
2918 register_command(cmd_ctx
, arm7_9_cmd
, "dcc_downloads", handle_arm7_9_dcc_downloads_command
,
2919 COMMAND_ANY
, "use DCC downloads for larger memory writes <enable | disable>");
2921 armv4_5_register_commands(cmd_ctx
);
2923 etm_register_commands(cmd_ctx
);
2928 int handle_arm7_9_write_xpsr_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2933 target_t
*target
= get_current_target(cmd_ctx
);
2934 armv4_5_common_t
*armv4_5
;
2935 arm7_9_common_t
*arm7_9
;
2937 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2939 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2943 if (target
->state
!= TARGET_HALTED
)
2945 command_print(cmd_ctx
, "can't write registers while running");
2951 command_print(cmd_ctx
, "usage: write_xpsr <value> <not cpsr | spsr>");
2955 value
= strtoul(args
[0], NULL
, 0);
2956 spsr
= strtol(args
[1], NULL
, 0);
2958 /* if we're writing the CPSR, mask the T bit */
2962 arm7_9
->write_xpsr(target
, value
, spsr
);
2963 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
2965 LOG_ERROR("JTAG error while writing to xpsr");
2972 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
2978 target_t
*target
= get_current_target(cmd_ctx
);
2979 armv4_5_common_t
*armv4_5
;
2980 arm7_9_common_t
*arm7_9
;
2982 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
2984 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
2988 if (target
->state
!= TARGET_HALTED
)
2990 command_print(cmd_ctx
, "can't write registers while running");
2996 command_print(cmd_ctx
, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
3000 value
= strtoul(args
[0], NULL
, 0);
3001 rotate
= strtol(args
[1], NULL
, 0);
3002 spsr
= strtol(args
[2], NULL
, 0);
3004 arm7_9
->write_xpsr_im8(target
, value
, rotate
, spsr
);
3005 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
3007 LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
3014 int handle_arm7_9_write_core_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3019 target_t
*target
= get_current_target(cmd_ctx
);
3020 armv4_5_common_t
*armv4_5
;
3021 arm7_9_common_t
*arm7_9
;
3023 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
3025 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
3029 if (target
->state
!= TARGET_HALTED
)
3031 command_print(cmd_ctx
, "can't write registers while running");
3037 command_print(cmd_ctx
, "usage: write_core_reg <num> <mode> <value>");
3041 num
= strtol(args
[0], NULL
, 0);
3042 mode
= strtoul(args
[1], NULL
, 0);
3043 value
= strtoul(args
[2], NULL
, 0);
3045 return arm7_9_write_core_reg(target
, num
, mode
, value
);
3048 int handle_arm7_9_dbgrq_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3050 target_t
*target
= get_current_target(cmd_ctx
);
3051 armv4_5_common_t
*armv4_5
;
3052 arm7_9_common_t
*arm7_9
;
3054 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
3056 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
3062 if (strcmp("enable", args
[0]) == 0)
3064 arm7_9
->use_dbgrq
= 1;
3066 else if (strcmp("disable", args
[0]) == 0)
3068 arm7_9
->use_dbgrq
= 0;
3072 command_print(cmd_ctx
, "usage: arm7_9 dbgrq <enable | disable>");
3076 command_print(cmd_ctx
, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9
->use_dbgrq
) ? "enabled" : "disabled");
3081 int handle_arm7_9_fast_memory_access_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3083 target_t
*target
= get_current_target(cmd_ctx
);
3084 armv4_5_common_t
*armv4_5
;
3085 arm7_9_common_t
*arm7_9
;
3087 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
3089 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
3095 if (strcmp("enable", args
[0]) == 0)
3097 arm7_9
->fast_memory_access
= 1;
3099 else if (strcmp("disable", args
[0]) == 0)
3101 arm7_9
->fast_memory_access
= 0;
3105 command_print(cmd_ctx
, "usage: arm7_9 fast_memory_access <enable | disable>");
3109 command_print(cmd_ctx
, "fast memory access is %s", (arm7_9
->fast_memory_access
) ? "enabled" : "disabled");
3114 int handle_arm7_9_dcc_downloads_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
3116 target_t
*target
= get_current_target(cmd_ctx
);
3117 armv4_5_common_t
*armv4_5
;
3118 arm7_9_common_t
*arm7_9
;
3120 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
3122 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
3128 if (strcmp("enable", args
[0]) == 0)
3130 arm7_9
->dcc_downloads
= 1;
3132 else if (strcmp("disable", args
[0]) == 0)
3134 arm7_9
->dcc_downloads
= 0;
3138 command_print(cmd_ctx
, "usage: arm7_9 dcc_downloads <enable | disable>");
3142 command_print(cmd_ctx
, "dcc downloads are %s", (arm7_9
->dcc_downloads
) ? "enabled" : "disabled");
3147 int arm7_9_init_arch_info(target_t
*target
, arm7_9_common_t
*arm7_9
)
3149 int retval
= ERROR_OK
;
3150 armv4_5_common_t
*armv4_5
= &arm7_9
->armv4_5_common
;
3152 arm7_9
->common_magic
= ARM7_9_COMMON_MAGIC
;
3154 if ((retval
= arm_jtag_setup_connection(&arm7_9
->jtag_info
)) != ERROR_OK
)
3159 arm7_9
->wp_available
= 0; /* this is set up in arm7_9_clear_watchpoints() */
3160 arm7_9
->wp_available_max
= 2;
3161 arm7_9
->sw_breakpoints_added
= 0;
3162 arm7_9
->sw_breakpoint_count
= 0;
3163 arm7_9
->breakpoint_count
= 0;
3164 arm7_9
->wp0_used
= 0;
3165 arm7_9
->wp1_used
= 0;
3166 arm7_9
->wp1_used_default
= 0;
3167 arm7_9
->use_dbgrq
= 0;
3169 arm7_9
->etm_ctx
= NULL
;
3170 arm7_9
->has_single_step
= 0;
3171 arm7_9
->has_monitor_mode
= 0;
3172 arm7_9
->has_vector_catch
= 0;
3174 arm7_9
->debug_entry_from_reset
= 0;
3176 arm7_9
->dcc_working_area
= NULL
;
3178 arm7_9
->fast_memory_access
= fast_and_dangerous
;
3179 arm7_9
->dcc_downloads
= fast_and_dangerous
;
3181 arm7_9
->need_bypass_before_restart
= 0;
3183 armv4_5
->arch_info
= arm7_9
;
3184 armv4_5
->read_core_reg
= arm7_9_read_core_reg
;
3185 armv4_5
->write_core_reg
= arm7_9_write_core_reg
;
3186 armv4_5
->full_context
= arm7_9_full_context
;
3188 if ((retval
= armv4_5_init_arch_info(target
, armv4_5
)) != ERROR_OK
)
3193 if ((retval
= target_register_timer_callback(arm7_9_handle_target_request
, 1, 1, target
)) != ERROR_OK
)
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